VN710SP ® AUTOMOTIVE GLOW PLUG DRIVER PRELIMINARY DATA TYPE VN710SP ■ ■ ■ ■ ■ ■ ■ ■ RDS(on) 18mΩ IOUT 35 A VCC 16 V CMOS COMPATIBLE INPUT ON STATE OPEN LOAD DETECTION OFF STATE OPENLOAD DETECTION 10 SHORTED LOAD PROTECTION UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN PROTECTION AGAINST LOSS OF GROUND VERY LOW STAND-BY CURRENT WHEN ENABLE PIN IS LOW REVERSE BATTERY PROTECTION (*) DESCRIPTION The VN710SP is a monolithic device made using STMicroelectronics VIPower M0-3 technology, intended for driving any kind of load with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transients compatibility table). Active current limitation combined with thermal shutdown protect the device against 1 PowerSO-10™ overload. After a thermal shutdown event, device stays latched off and diagnostic stays at a low level until next falling edge of input signal. The device detects open load condition both in on state and off state. Output shorted to VCC is detected in the off state. Device automatically turns off in case of ground pin disconnection. Enable pin allows to switch the device to idle state with very low quiescent current from VCC. When enable is low, device turns off regardless of input pin state. BLOCK DIAGRAM V CC OVERVOLTAGE DETECTION VCC CLAMP UNDERVOLTAGE DETECTION GND Power CLAMP DRIVER INPUT OUTPUT LOGIC CURRENT LIMITER ON STATE OPENLOAD DETECTION STATUS ENABLE OFF STATE OPENLOAD AND OUTPUT SHORTED TO VCC DETECTION OVERTEMPERATURE DETECTION (*) See application schematic at page 7 October 2000 1/11 1 VN710SP THERMAL DATA Symbol Rtj-case Rtj-amb (*) Parameter Thermal resistance junction-case Thermal resistance junction-ambient Value 1.4 52 Unit °C/W °C/W Value 41 -0.3 -200 Internally limited -35 +/-10 +/-10 +/-10 2000 89 Internally limited -40 to 150 -55 to 150 Unit V V mA A A mA mA mA V W °C °C °C (*) When mounted on a standard single-sided FR-4 board with 50mm2 of Cu (at least 35µm thick). ABSOLUTE MAXIMUM RATING Symbol VCC -VCC -I GND IOUT -IOUT IIN Ien ISTAT VESD Ptot Tj Tc Tstg Parameter DC supply voltage Reverse DC supply voltage Reverse DC ground pin current DC output current Reverse DC output current DC input current DC enable current DC status current Electrostatic discharge (R=1.5kΩ; C=100pF) Power dissipation at Tc=25°C Junction operating temperature Case operating temperature Storage temperature CONNECTION DIAGRAM (TOP VIEW) 5 4 3 6 7 GROUND ENABLE STATUS INPUT N.C. 8 9 OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT 2 10 1 11 VCC CURRENT AND VOLTAGE CONVENTIONS Ien ICC VCC Ven IIN VCC ENABLE INPUT VIN ISTAT IOUT OUTPUT STATUS VOUT GND VSTAT 2/11 1 IGND VN710SP ELECTRICAL CHARACTERISTICS (7V<VCC<16V; -40°C<Tj<150°C; unless otherwise specified) POWER Symbol VCC VUSD VOV RON IS Parameter Operating supply voltage Undervoltage shutdown Overvoltage shutdown On state resistance Supply current ILGND Output current at Turn-off IL(off1) IL(off2) Off state output current Off state output current Test Conditions Min 5.5 3 16 Typ 13 4 18 IOUT=15A; Tj=25°C IOUT=15A Max 16 5.5 20 20 Unit V V V mΩ 40 mΩ Off state; VCC=13V; Ven=VOUT=0V; VIN=5V 10 25 µA Off state; VCC=13V; Ven=VOUT=0V; VIN=5V; Tj=25°C 10 20 µA On state; VCC=13V; VIN=0V; IOUT=0A; Ven>Venh 2.5 4 mA 2 mA 50 0 µA µA Max Unit VCC=VGND=16V VIN=Ven=n.c.; VOUT=0V VOUT=0V; VIN>VIH VOUT=3.5V; VIN>VIH; Ven>Venh 0 -75 SWITCHING (VCC=13V) Symbol Parameter td(on) Turn-on delay time td(off) Turn-off delay time dVOUT/ dt(on) dVOUT/ dt(off) Turn-on voltage slope Turn-off voltage slope Test Conditions RL=0.85Ω, from VIN falling edge to VOUT=1.3V RL=0.85Ω, from VIN rising edge to VOUT=11.7V RL=0.85Ω, from VOUT=1.3V to VOUT=10.4V RL=0.85Ω, from VOUT=11.7V to VOUT=1.3V Min Typ 40 µs 80 µs 0.1 V/µs 0.1 V/µs INPUT PIN (active low) Symbol VIL IIL VIH Parameter Input low level Low level input current Input high level IIH High level input current VI(hyst) Input hysteresis voltage VICL Input clamp voltage Test Conditions VIN=1.25V; Ven>Venh Min Typ -35 3.25 VIN=3.25V; Ven>Venh VIN=3.25V; Ven=0V IIN=1mA Max 1.25 -4 -300 0.5 6 IIN=-1mA -4 6.8 8 -0.7 Unit V µA V µA µA V V V ENABLE PIN (active high) Symbol Venl Ienl Venh Ienh Vehyst Vencl Parameter Test Conditions Enable low level Low level enable current Ven=1.25V Enable high level High level enable current Ven=3.25V Enable hysteresis voltage Ien=1mA Enable clamp voltage Ien=-1mA Min Typ Max 1.25 4 3.25 35 0.5 6 6.8 -0.7 8 Unit V µA V µA V V V 3/11 1 VN710SP ELECTRICAL CHARACTERISTICS (continued) STATUS PIN (Open Drain) Symbol VSTAT ILSTAT CSTAT VSCL Parameter Status low output voltage Status leakage current Status pin input capacitance Status clamp voltage Test Conditions Max Unit ISTAT=1.6mA 0.5 V Normal operation; VSTAT=5V 10 µA Normal operation; VSTAT=5V 100 pF ISTAT=1mA Min 6 ISTAT=-1mA Typ 6.8 8 -0.7 V V PROTECTIONS Symbol TTSD TR Thyst tSDL Ilim Vdemag Parameter Shut-down temperature Reset temperature Thermal hysteresis Overload detection delay Current limitation Turn-off output clamp voltage Test Conditions Min 170 135 7 Typ 190 35 55 15 Tj>TTSD IOUT=2A; VIN=5V; L=6mH Max 20 80 VCC-41 VCC-48 VCC-55 Unit °C °C °C µs A V OPENLOAD DETECTION Symbol IOL VOL tDOL(off) tDOL(on) Parameter Openload on state Min Typ Max Unit VIN=0V 0.1 1 2 A Openload off state voltage VIN=5V detection threshold 1.5 2.5 3.5 V 500 µs 200 µs detection threshold Test Conditions Openload detection delay at turn-off Openload detection delay at turn-on IOUT=0V OPENLOAD STATUS TIMING (with external pull-up) IOUT<IOL VOUT>VOL VIN OVERTEMP STATUS TIMING VIN Tj>TTSD VSTAT VSTAT tDOL(off) 4/11 2 tDOL(on) tSDL VN710SP Switching Time Waveforms VOUT 90% 80% dVOUT/dt(off) dVOUT/dt(on) 10% t VIN td(off) td(on) t TRUTH TABLE CONDITIONS Normal operation Current limitation Overtemperature Undervoltage Overvoltage Output voltage > VOL Output current < IOL Any ENABLE INPUT OUTPUT STATUS H H L L H H H H L L X H H L H L (*) L L (*) L H L L L X X H L L L H H H L H H L H H L L H H L X L H H H H H H H H H H H H H H L (*) Latched on first overtemperature event; latch cleared on next input falling edge. 5/11 VN710SP ELECTRICAL TRANSIENTS REQUIREMENTS ON VCC PIN TEST LEVELS ISO T/R 7637/1 Test Pulse I II III IV Delays and Impedance 1 -25V -50V -75V -100V 2ms, 10Ω 2 +25V +50V +75V +100V 0.2ms, 10Ω 3a -25V -50V -100V -150V 0.1ms, 50Ω 3b +25V +50V +75V +100V 0.1ms, 50Ω 4 -4V -5V -6V -7V 100ms, 0.01Ω 5 +26.5V +46.5V +66.5V +86.5V 400ms, 2Ω TEST LEVELS RESULT ISO T/R 7637/1 Test Pulse I II III IV 1 C C C C 2 C C C C 3a C C C C 3b C C C C 4 C C C C 5 C E E E CLASS C E CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. SUGGESTED SCHEME FOR ISO TEST PULSE from test generator 10K Ω 10K Ω ENABLE VCC INPUT 10KΩ STATUS OUTPUT GND Warning: Input, Enable, Status Pulled to VCC voltage during negative transient. 6/11 open VN710SP APPLICATION SCHEMATIC +5V +5V VCC Rprot STATUS Dld µC Rprot INPUT OUTPUT Rprot ENABLE GND VGND GND PROTECTION REVERSE BATTERY NETWORK AGAINST Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND ≤ 600mV / (IS(on)max). 2) RGND ≥ (−VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the of the device’s datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggest to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device will be driving an inductive load. RGND DGND This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. LOAD DUMP PROTECTION Dld is necessary (Transil or MOV) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table. µC I/Os PROTECTION: If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot ) in line to prevent the µC I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os. -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V 5kΩ ≤ Rprot ≤ 18.57kΩ. Recommended Rprot value is10kΩ. 7/11 1 VN710SP Figure1: Waveforms NORMAL OPERATION INPUT LOAD VOLTAGE STATUS UNDERVOLTAGE VUSDhyst VCC VUSD INPUT LOAD VOLTAGE STATUS undefined OVERVOLTAGE VOV VCC VCC<VOV VCC>VOV VOVhyst INPUT LOAD VOLTAGE STATUS OPENLOAD INPUT LOAD VOLTAGE STATUS tDOL(on) tDOL(on) OVERTEMPERATURE ENABLE Tj TTSD TR INPUT LOAD CURRENT STATUS SHORT TO VCC INPUT LOAD VOLTAGE STATUS undefined tDOL(off) undefined tDOL(off) 8/11 1 1 VN710SP PowerSO-10™ MECHANICAL DATA mm. DIM. MIN. A A (*) A1 B B (*) C C (*) D D1 E E2 E2 (*) E4 E4 (*) e F F (*) H H (*) h L L (*) α α (*) inch TYP 3.35 3.4 0.00 0.40 0.37 0.35 0.23 9.40 7.40 9.30 7.20 7.30 5.90 5.90 MAX. MIN. 3.65 3.6 0.10 0.60 0.53 0.55 0.32 9.60 7.60 9.50 7.60 7.50 6.10 6.30 0.132 0.134 0.000 0.016 0.014 0.013 0.009 0.370 0.291 0.366 0.283 0.287 0.232 0.232 1.35 1.40 14.40 14.35 0.049 0.047 0.543 0.545 1.80 1.10 8º 8º 0.047 0.031 0º 2º 1.27 TYP. MAX. 0.144 0.142 0.004 0.024 0.021 0.022 0.0126 0.378 0.300 0.374 300 0.295 0.240 0.248 0.050 1.25 1.20 13.80 13.85 0.50 0.053 0.055 0.567 0.565 0.002 1.20 0.80 0º 2º 0.070 0.043 8º 8º (*) Muar only POA P013P B 0.10 A B 10 H E E E2 1 SEATING PLANE e B DETAIL "A" A C 0.25 h E4 D = D1 = = = SEATING PLANE A F A1 A1 L DETAIL "A" α P095A 9/11 1 VN710SP PowerSO-10™ SUGGESTED PAD LAYOUT TUBE SHIPMENT (no suffix) 14.6 - 14.9 CASABLANCA B 10.8- 11 MUAR C 6.30 C A A 0.67 - 0.73 10 9 1 9.5 2 3 B 0.54 - 0.6 All dimensions are in mm. 8 7 4 5 1.27 Base Q.ty Bulk Q.ty Tube length (± 0.5) 6 Casablanca Muar 50 50 1000 1000 532 532 A B C (± 0.1) 10.4 16.4 4.9 17.2 0.8 0.8 TAPE AND REEL SHIPMENT (suffix “13TR”) REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (± 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) All dimensions are in mm. 24 4 24 1.5 1.5 11.5 6.5 2 End Start Top No components Components No components cover tape 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed 10/11 1 1 VN710SP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 11/11