VNB10N07/K10N07FM VNP10N07FI/VNV10N07 ”OMNIFET”: FULLY AUTOPROTECTED POWER MOSFET T YPE VNB10N07 VNK10N07FM VNP10N07FI VNV10N07 ■ ■ ■ ■ ■ ■ ■ ■ ■ V c lamp 70 70 70 70 V V V V R DS(on) 0.1 0.1 0.1 0.1 Ω Ω Ω Ω I l im 10 10 10 10 A A A A LINEAR CURRENT LIMITATION THERMAL SHUT DOWN SHORT CIRCUIT PROTECTION INTEGRATED CLAMP LOW CURRENT DRAWN FROM INPUT PIN DIAGNOSTIC FEEDBACK THROUGH INPUT PIN ESD PROTECTION DIRECT ACCESS TO THE GATE OF THE POWER MOSFET (ANALOG DRIVING) COMPATIBLE WITH STANDARD POWER MOSFET DESCRIPTION The VNB10N07, VNK10N07FM, VNP10N07FI and VNV10N07 are monolithic devices made using STMicroelectronics VIPower M0 Technology, intended for replacement of standard power MOSFETS in DC to 50 KHz applications. Built-in thermal shut-down, linear current limitation and overvoltage clamp protect BLOCK DIAGRAM (∗) 3 1 D2PAK TO-263 SOT82-FM 3 1 ISOWATT220 2 10 1 PowerSO-10 the chip in harsh enviroments. Fault feedback can be detected by monitoring the voltage at the input pin. (∗) PowerSO-10 Pin Configuration : INPUT = 6,7,8,9,10; SOURCE = 1,2,4,5; DRAIN = TAB June 1998 1/14 VNB10N07-VNK10N07FM-VNP10N07FI-VNV10N07 ABSOLUTE MAXIMUM RATING Symbol Parameter Value Pow erSO-10 D2PAK V DS Drain-source Voltage (V in = 0) V in Unit SOT -82FM ISOW AT T220 Internally Clamped V Input Voltage 18 V ID Drain Current Internally Limited A IR Reverse DC O utput Current -14 A 2000 V V esd Electrostatic Discharge (C= 100 pF, R=1.5 KΩ) P tot Total Dissipation at T c = 25 C Tj Tc T stg o 50 9.5 Operating Junction T emperature Case O perating T emperature 31 W Internally Limited o C Internally Limited o C -55 to 150 o C Storage Temperature THERMAL DATA ISOW ATT220 Po werSO -10 SOT82-FM D2PAK R t hj-ca se Thermal Resistance Junction-case Max 4 2.5 13 2.5 o C/W R t hj-a mb Thermal Resistance Junction-ambient Max 62.5 50 100 62.5 o C/W ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symb ol Parameter Test Cond ition s V CLAMP Drain-source Clamp Voltage I D = 200 mA V CL TH Drain-source Clamp Threshold Voltage I D = 2 mA V I NCL Input-Source Reverse Clamp Voltage I in = -1 mA I DSS Zero Input Voltage Drain Current (V in = 0) V DS = 13 V V DS = 25 V V in = 0 V in = 0 I I SS Supply Current from Input Pin V DS = 0 V Vin = 10 V V in = 0 V in = 0 Min. Typ . Max. Un it 60 70 80 V 55 V -1 -0.3 V 50 200 µA µA 250 500 µA Typ . Max. Un it 3 V 0.1 0.14 Ω Ω ON (∗) Symb ol Parameter Test Cond ition s Min. 0.8 V IN(th) Input Threshold Voltage V DS = Vin ID + Ii n = 1 mA R DS( on) Static Drain-source On Resistance V i n = 10 V Vi n = 5 V ID = 5 A ID = 5 A 2/14 VNB10N07-VNK10N07FM-VNP10N07FI-VNV10N07 ELECTRICAL CHARACTERISTICS (continued) DYNAMIC Symb ol g fs (∗) C oss Parameter Test Cond ition s Forward Transconductance V DS = 13 V ID = 5 A Output Capacitance VDS = 13 V f = 1 MHz Min. Typ . 6 8 V in = 0 Max. Un it S 350 500 pF Typ . Max. Un it SWITCHING (**) Symb ol Parameter Test Cond ition s Min. t d(on) tr t d(of f) tf Turn-on Delay Time Rise Time Turn-off Delay Time Fall T ime V DD = 15 V V gen = 10 V (see figure 3) Id = 5 A R gen = 10 Ω 50 80 230 100 100 160 400 180 ns ns ns ns t d(on) tr t d(of f) tf Turn-on Delay Time Rise Time Turn-off Delay Time Fall T ime V DD = 15 V V gen = 10 V (see figure 3) Id = 5 A R gen = 1000 Ω 600 0.9 3.8 1.7 900 2 6 2.5 ns µs µs µs Turn-on Current Slope V DD = 15 V V i n = 10 V Total Input Charge V DD = 12 V (di/dt) on Qi ID = 5 A R gen = 10 Ω ID = 5 A V in = 10 V 60 A/µs 30 nC SOURCE DRAIN DIODE Symb ol Parameter Test Cond ition s V SD (∗) Forward O n Voltage I SD = 5 A t r r (∗∗) Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 5 A di/dt = 100 A/µs Tj = 25 oC V DD = 30 V (see test circuit, figure 5) Q r r (∗∗) I RRM (∗∗) Min. Typ . V in = 0 Max. Un it 1.6 V 125 ns 0.3 µC 4.8 A PROTECTION Symb ol I lim Parameter Test Cond ition s Min. Typ . Max. Un it VDS = 13 V V DS = 13 V 7 7 10 10 14 14 A A 20 50 30 80 µs µs Drain Current Limit V i n = 10 V Vi n = 5 V t dl im (∗∗) Step Response Current Limit V i n = 10 V Vi n = 5 V T jsh (∗∗) Overtemperature Shutdown 150 o C T j rs (∗∗) Overtemperature Reset 135 o C I gf (∗∗) Fault Sink Current V i n = 10 V Vi n = 5 V E as (∗∗) Single Pulse Avalanche Energy starting T j = 25 C V DD = 20 V V i n = 10 V R gen = 1 KΩ L = 10 mH 50 20 VDS = 13 V V DS = 13 V o 0.4 mA mA J (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (∗∗) Parameters guaranteed by design/characterization 3/14 VNB10N07-VNK10N07FM-VNP10N07FI-VNV10N07 PROTECTION FEATURES During normal operation, the Input pin is electrically connected to the gate of the internal power MOSFET. The device then behaves like a standard power MOSFET and can be used as a switch from DC to 50 KHz. The only difference from the user’s standpoint is that a small DC current (Iiss) flows into the Input pin in order to supply the internal circuitry. The device integrates: - OVERVOLTAGE CLAMP PROTECTION: internally set at 70V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads. - LINEAR CURRENT LIMITER CIRCUIT: limits the drain current Id to Ilim whatever the Input pin voltage. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold Tjsh. 4/14 - OVERTEMPERATURE AND SHORT CIRCUIT PROTECTION: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs at minimum 150oC. The device is automatically restarted when the chip temperature falls below 135oC. - STATUS FEEDBACK: In the case of an overtemperature fault condition, a Status Feedback is provided through the Input pin. The internal protection circuit disconnects the input from the gate and connects it instead to ground via an equivalent resistance of 100 Ω. The failure can be detected by monitoring the voltage at the Input pin, which will be close to ground potential. Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit (with a small increase in RDS(on)). VNB10N07-VNK10N07FM-VNP10N07FI-VNV10N07 Thermal Impedance For ISOWATT220 Thermal Impedance For D2PAK / PowerSO-10 Derating Curve Output Characteristics Transconductance Static Drain-Source On Resistance vs Input Voltage 5/14 VNB10N07-VNK10N07FM-VNP10N07FI-VNV10N07 Static Drain-Source On Resistance Static Drain-Source On Resistance Input Charge vs Input Voltage Capacitance Variations Normalized Input Threshold Voltage vs Temperature Normalized On Resistance vs Temperature 6/14 VNB10N07-VNK10N07FM-VNP10N07FI-VNV10N07 Normalized On Resistance vs Temperature Turn-on Current Slope Turn-on Current Slope Turn-off Drain-Source Voltage Slope Turn-off Drain-Source Voltage Slope Switching Time Resistive Load 7/14 VNB10N07-VNK10N07FM-VNP10N07FI-VNV10N07 Switching Time Resistive Load Switching Time Resistive Load Current Limit vs Junction Temperature Step Response Current Limit Source Drain Diode Forward Characteristics 8/14 VNB10N07-VNK10N07FM-VNP10N07FI-VNV10N07 Fig. 1: Unclamped Inductive Load Test Circuits Fig. 2: Unclamped Inductive Waveforms Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Input Charge Test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 6: Waveforms 9/14 VNB10N07-VNK10N07FM-VNP10N07FI-VNV10N07 TO-263 (D2PAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.3 4.6 0.169 0.181 A1 2.49 2.69 0.098 0.106 B 0.7 0.93 0.027 0.036 B2 1.25 1.4 0.049 0.055 C 0.45 0.6 0.017 0.023 C2 1.21 1.36 0.047 0.053 D 8.95 9.35 0.352 0.368 E 10 10.28 0.393 0.404 G 4.88 5.28 0.192 0.208 L 15 15.85 0.590 0.624 L2 1.27 1.4 0.050 0.055 L3 1.4 1.75 0.055 0.068 E A C2 L2 D L L3 B2 B A1 C G P011P6/C 10/14 VNB10N07-VNK10N07FM-VNP10N07FI-VNV10N07 SOT82-FM MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 2.85 3.05 1.122 1.200 A1 1.47 1.67 0.578 0.657 b 0.40 0.60 0.157 0.236 b1 1.4 1.6 0.551 0.630 b2 1.3 1.5 0.511 0.590 c 0.45 0.6 0.177 0.236 D 10.5 10.9 4.133 4.291 e 2.2 2.8 0.866 1.102 E 7.45 7.75 2.933 3.051 L 15.5 15.9 6.102 6.260 L1 1.95 2.35 0.767 0.925 P032R 11/14 VNB10N07-VNK10N07FM-VNP10N07FI-VNV10N07 ISOWATT220 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.4 4.6 0.173 0.181 B 2.5 2.7 0.098 0.106 D 2.5 2.75 0.098 0.108 E 0.4 0.7 0.015 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.7 0.045 0.067 F2 1.15 1.7 0.045 0.067 G 4.95 5.2 0.195 0.204 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 0.409 L2 16 0.630 28.6 30.6 1.126 1.204 L4 9.8 10.6 0.385 0.417 L6 15.9 16.4 0.626 0.645 L7 9 9.3 0.354 0.366 Ø 3 3.2 0.118 0.126 B D A E L3 L3 L6 F F1 L7 F2 H G G1 ¯ 1 2 3 L2 12/14 L4 P011G VNB10N07-VNK10N07FM-VNP10N07FI-VNV10N07 PowerSO-10 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 3.35 3.65 0.132 0.144 A1 0.00 0.10 0.000 0.004 B 0.40 0.60 0.016 0.024 c 0.35 0.55 0.013 0.022 D 9.40 9.60 0.370 0.378 D1 7.40 7.60 0.291 0.300 E 9.30 9.50 0.366 0.374 E1 7.20 7.40 0.283 0.291 E2 7.20 7.60 0.283 0.300 E3 6.10 6.35 0.240 0.250 E4 5.90 6.10 0.232 e 1.27 0.240 0.050 F 1.25 1.35 0.049 0.053 H 13.80 14.40 0.543 0.567 1.80 0.047 h 0.50 L 0.002 1.20 q 1.70 0.067 o α 0.071 8o 0 B 0.10 A B 10 5 e 0.25 B = = = E4 = = = 1 E1 = E3 = E2 = E = = = H 6 SEATING PLANE DETAIL ”A” A C M Q h D = D1 = = = SEATING PLANE A F A1 A1 L DETAIL ”A” α 0068039-C 13/14 VNB10N07-VNK10N07FM-VNP10N07FI-VNV10N07 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical compone nts in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 1998 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. . 14/14