WS57C256F HIGH SPEED 32K x 8 CMOS EPROM KEY FEATURES • Immune to Latch-UP • Fast Access Time — t ACC = 35 ns — Up to 200 mA • ESD Protection Exceeds 2000 Volts • Available in 300 Mil DIP and PLDCC • DESC SMD No. 5962-86063 — t CE = 35 ns • Low Power Consumption — 200 µA Standby ICC GENERAL DESCRIPTION The WS57C256F is a High Performance 32K x 8 UV Erasable EPROM. It is manufactured using an advanced CMOS process technology enabling it to operate at speeds as fast as 35 ns Address Access Time (tACC) and 35 ns Chip Enable Time (t CE). It was designed utilizing WSI's patented self-aligned split gate EPROM cell, resulting in a low power device with a very cost effective die size. The low standby power capability of this 256 K product (200 µA in a CMOS interface environment) is especially attractive. This product, with its high speed capability, is particularly appropriate for use with today's fast DSP processors and high-clock-rate Microprocessors. The WS57C256F's 35 ns speed enables these advanced processors to operate without introducing any undesirable wait states. The WS57C256F is also ideal for use in modem applications, and is recommended for use in these applications by the leading modem chip set manufacturer. The WS57C256F is available in a variety of package types including the space saving 300 Mil DIP, the surface mount PLDCC, and other windowed and non-windowed options. And its standard JEDEC EPROM pinouts provide for automatic upgrade density paths for current 64K and 128K EPROM users. PIN CONFIGURATION MODE SELECTION PINS Read Output Disable CE/ PGM OE A9 A0 TOP VIEW VPP VCC OUTPUTS Chip Carrier VIL VIL X X VCC VCC DOUT X VIH X X VCC VCC High Z CERDIP A7 A12 VPP NC VCC A14 A13 MODE Standby VIH X X X VCC VCC High Z Program VIL VIH X X VPP 2 VCC DIN Program Verify X VIL X X VPP 2 VCC DOUT Program Inhibit VIH VIH X X VPP2 VCC High Z VIL VIL VH2 VIL VCC VCC 23 H4 VIL VIL VH2 VIH VCC VCC EO H 5 Signature3 NOTES: 1. X can be VIL or VIH. 2. VIH = VPP = 12.75 ± 0.25 V. 3. A1 – A8, A10 – A14 = VIL. A6 A5 A4 A3 A2 A1 A0 NC O0 32 31 30 1 5 29 6 28 7 27 8 26 9 25 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20 O1 O2 GND 4 3 2 A8 A9 A11 NC OE A10 CE/PGM O7 O6 NC O3 O4 O5 VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A14 A13 A8 A9 A11 OE A10 CE/PGM O7 O6 O5 O4 O3 4. Manufacturer Signature. 5. Device Signature. PRODUCT SELECTION GUIDE PARAMETER WS57C256F-35 WS57C256F-45 WS57C256F-55 WS57C256F-70 Address Access Time (Max) 35 ns 45 ns 55 ns 70 ns Output Enable Time (Max) 15 ns 20 ns 25 ns 30 ns Return to Main Menu 3-13 WS57C256F ABSOLUTE MAXIMUM RATINGS* *NOTICE: Storage Temperature............................–65° to + 150°C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Voltage on any Pin with Respect to Ground ....................................–0.6V to +7V VPP and A 9 with Respect to Ground ......–0.6V to + 14V ESD Protection ..................................................> 2000V OPERATING RANGE RANGE TEMPERATURE VCC 0°C to +70°C +5V ± 10% Industrial –40°C to +85°C +5V ± 10% Military –55°C to +125°C +5V ± 10% Commercial DC READ CHARACTERISTICS Over Operating Range with VPP = VCC SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNITS VIL Input Low Voltage (Note 4) – 0.1 0.8 V VIH Input High Voltage (Note 4) 2.0 VCC + 0.3 V VOL Output Low Voltage IOL = 16 mA 0.4 V VOH Output High Voltage IOH = – 4 mA ISB1 VCC Standby Current (CMOS) CE = VCC ± 0.3 V (Note 1) ISB2 VCC Standby Current (TTL) CE = VIH (Note 2) ICC1 VCC Active Current (CMOS) ICC2 2.4 V Comm'l Ind/Mil 200 500 µA µA Comm'l 3 mA (Notes 1 and 3) Outputs Not Loaded Ind/Mil Comm'l Ind/Mil 5 25 30 mA mA mA VCC Active Current (TTL) (Notes 2 and 3) Outputs Not Loaded Comm'l Ind/Mil 50 60 mA mA IPP VPP Supply Current VPP = VCC 100 µA VPP VPP Read Voltage VCC – 0.4 VCC V ILI Input Leakage Current VIN = 5.5V or Gnd –10 10 µA ILO Output Leakage Current VOUT = 5.5 V or Gnd –10 10 µA NOTES: 1. CMOS inputs: GND ± 0.3V or VCC ± 0.3V. 2. TTL inputs: VIL ≤ 0.8V, VIH ≥ 2.0V. 3. Add 3 mA/MHz for A.C. power component. 4. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. AC READ CHARACTERISTICS Over Operating Range. with VPP = VCC PARAMETER SYMBOL 57C256F-35 MIN MAX 57C256F-45 MIN MAX 57C256F-55 MIN MAX 57C256F-70 MIN Address to Output Delay tACC 35 45 55 70 CE to Output Delay tCE 35 45 55 70 OE to Output Delay tOE 15 20 25 30 Output Disable to Output Float tDF 20 20 25 30 Address to Output Hold tOH 3-14 0 0 0 0 UNITS MAX ns WS57C256F AC READ TIMING DIAGRAM VALID ADDRESSES tACC tOH CE tCE tDF OE tOE OUTPUTS VALID tDF CAPACITANCE (5) TA = 25°C, f = 1 MHz SYMBOL PARAMETER CONDITIONS TYP (6) MAX UNITS VIN = 0V 4 6 pF C IN Input Capacitance C OUT Output Capacitance VOUT = 0V 8 12 pF C VPP VPP Capacitance VPP = 0 V 18 25 pF NOTES: 5. This parameter is only sampled and is not 100% tested. 6. Typical values are for TA = 25°C and nominal supply voltages. TEST LOAD (High Impedance Test Systems) A.C. TESTING INPUT/OUTPUT WAVEFORM 98 Ω 2.01 V D.U.T. 3.0 30 pF (INCLUDING SCOPE AND JIG CAPACITANCE) 0.0 2.0 0.8 2.0 TEST POINTS 0.8 A.C. testing inputs are driven at 3.0 V for a logic "1" and 0.0 V for a logic "0." Timing measurements are made at 2.0 V for a logic "1" and 0.8 V for a logic "0". NOTE: 7. Provide adequate decoupling capacitance as close as possible to this device to achieve the published A.C. and D.C. parameters. A 0.1 microfarad capacitor in parallel with a 0.01 microfarad capacitor connected between VCC and ground is recommended. Inadequate decoupling may result in access time degradation or other transient performance failures. 3-15 WS57C256F PROGRAMMING INFORMATION DC CHARACTERISTICS (TA = 25 ± 5°C, VCC = 6.25 V ± 0.25 V, VPP = 12.75 ± 0.25 V) SYMBOLS PARAMETER Input Leakage Current (VIN = VCC or Gnd) VPP Supply Current During Programming Pulse (CE/ PGM = VIL) VCC Supply Current (Note 8) Output Low Voltage During Verify (IOL = 16 mA) Output High Voltage During Verify (IOH = –4 mA) ILI IPP ICC VOL VOH NOTE: MIN MAX UNITS –10 10 µA 60 mA 35 mA 0.4 V 2.4 V 8. VCC must be applied either coincidentally or before VPP and removed either coincidentally or after VPP. 9. VPP must not be greater than 13 volts including overshoot. During CE = PGM = VIL, VPP must not be switched from 5 volts to 12.5 volts or vice-versa. 10. During power up the PGM pin must be brought high (≥ VIH) either coincident with or before power is applied to VPP. AC CHARACTERISTICS (TA = 25 ± 5°C, VCC = 6.25 V ± 0.25 V, VPP = 12.75 ± 0.25 V) SYMBOLS PARAMETER MIN TYP MAX tAS Address Setup Time 2 µs tCOH CE High to OE High 2 µs tOES Output Enable Setup Time 2 µs tOS Data Setup Time 2 µs tAH Address Hold Time 0 µs tOH Data Hold Time 2 µs tDF Chip Disable to Output Float Delay 0 tOE Data Valid From Output Enable tVS/tCES VPP Setup Time/CE Setup Time tPW PGM Pulse Width tOCX OE Low to CE "Don't Care" 2 VPP tAH VIH CE/PGM HIGH Z DATA IN STABLE tOH DATA OUT VALID tOE tDF VPP VCC tVS tOCX tCES VIL tPW VIH OE VIL ns tOES µs µs tAS tOS 130 200 ADDRESS STABLE DATA ns µs 100 ADDRESSES 130 2 PROGRAMMING WAVEFORM 3-16 UNITS tCOH WS57C256F ORDERING INFORMATION PART NUMBER WS57C256F-35C WS57C256F-35D WS57C256F-35J WS57C256F-35L WS57C256F-35P WS57C256F-35T WS57C256F-45C WS57C256F-45D WS57C256F-45P WS57C256F-45T WS57C256F-55C WS57C256F-55CMB WS57C256F-55D WS57C256F-55DM WS57C256F-55DMB WS57C256F-55J WS57C256F-55L WS57C256F-55P WS57C256F-55T WS57C256F-55TMB WS57C256F-70CMB* WS57C256F-70D WS57C256F-70DMB* WS57C256F-70J WS57C256F-70JI WS57C256F-70T SPEED (ns) 35 35 35 35 35 35 45 45 45 45 55 55 55 55 55 55 55 55 55 55 70 70 70 70 70 70 PACKAGE TYPE 32 Pad CLLCC 28 Pin CERDIP, 0.6" 32 Pin PLDCC 32 Pin CLDCC 28 Pin Plastic DIP, 0.6" 28 Pin CERDIP, 0.3" 32 Pad CLLCC 28 Pin CERDIP, 0.6" 28 Pin Plastic DIP, 0.6" 28 Pin CERDIP, 0.3" 32 Pad CLLCC 32 Pad CLLCC 28 Pin CERDIP, 0.6" 28 Pin CERDIP, 0.6" 28 Pin CERDIP, 0.6" 32 Pin PLDCC 32 Pin CLDCC 28 Pin Plastic DIP, 0.6" 28 Pin CERDIP, 0.3" 28 Pin CERDIP, 0.3" 32 Pad CLLCC 28 Pin CERDIP, 0.6" 28 Pin CERDIP, 0.6" 32 Pin PLDCC 32 Pin PLDCC 28 Pin CERDIP, 0.3" OPERATING WSI PACKAGE DRAWING TEMPERATURE MANUFACTURING RANGE PROCEDURE C2 D2 J4 L3 P3 T2 C2 D2 P3 T2 C2 C2 D2 D2 D2 J4 L3 P3 T2 T2 C2 D2 D2 J4 J4 T2 Comm’l Comm’l Comm’l Comm’l Comm’l Comm’l Comm’l Comm’l Comm’l Comm’l Comm’l Military Comm’l Military Military Comm’l Comm’l Comm’l Comm’l Military Military Comm’l Military Comm’l Industrial Comm’l Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard MIL-STD-883C Standard Standard MIL-STD-883C Standard Standard Standard Standard MIL-STD-883C MIL-STD-883C Standard MIL-STD-883C Standard Standard Standard NOTE: 11. The actual part marking will not include the initials "WS." *SMD product. See section 4 for DESC SMD number. PROGRAMMING/ALGORITHMS/ERASURE/PROGRAMMERS REFER TO PAGE 5-1 The WS57C256F is programmed using Algorithm D shown on page 5-9. When using Data I/O programmers, algorithm 57C256FB is recommended for use with the WS57C256F for best programming results. Return to Main Menu 3-17