WS57C71C HIGH SPEED 32K x 8 CMOS PROM/RPROM KEY FEATURES • Immune to Latch-UP • Ultra-Fast Access Time — 35 ns — Up to 200 mA • Low Power Consumption • Fast Programming • ESD Protection Exceeds 2000V • Available in 300 Mil DIP and PLDCC GENERAL DESCRIPTION The WS57C71C is a High Performance 256K UV Erasable Electrically Re-Programmable Read Only Memory (RPROM). It is manufactured in an advanced CMOS technology and utilizes WSI's patented self-aligned split gate EPROM cell. The industry standard PROM pin configuration of the WS57C71C provides an easy upgrade path from a 16K x 8 device. This RPROM is capable of operating at speeds as fast as 35 ns address access time, which enables it to be used directly with today's fast microprocessors and DSP processors without introducing any wait states. All inputs and outputs are TTL compatible. The WS57C71C is a low power device even when operated at its fastest speed. The DIP version is packaged in a 300 mil wide DIP package saving board space for the user. BLOCK DIAGRAM PIN CONFIGURATION TOP VIEW Chip Carrier A6 - A14 ROW ADDRESSES ROW DECODER EPROM ARRAY CERDIP A7 A8 A9 NC VCC A10 A11 9 262,144 BITS 9 A0 - A5 COLUMN ADDRESSES A6 A5 A4 A3 A2 A1 A0 NC O0 COLUMN DECODER SENSE AMPLIFIERS CS1/ VPP CS2 32 31 30 1 5 29 6 28 7 27 8 26 9 25 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20 O1 O2 GND 4 3 2 A12 A13 A14 NC CS3 CS2 CS1/VPP O7 O6 NC O3 O4 O5 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A10 A11 A12 A13 A14 CS3 CS2 CS1/VPP O7 O6 O5 O4 O3 CS3 8 OUTPUTS PRODUCT SELECTION GUIDE PARAMETER WS57C71C-35 WS57C71C-45 WS57C71C-55 WS57C71C-70 Address Access Time (Max) 35 ns 45 ns 55 ns 70 ns CS to Output Valid Time (Max) 15 ns 20 ns 20 ns 30 ns Return to Main Menu 2-55 WS57C71C ABSOLUTE MAXIMUM RATINGS* MODE SELECTION Storage Temperature............................–65° to + 150°C Voltage on any Pin with Respect to Ground ....................................–0.6V to +7V VPP with Respect to Ground...................–0.6V to + 13V ESD Protection ..................................................> 2000V *NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. PINS MODE Read CS1/ CS2 CS3 VCC OUTPUTS VPP VIL Output Disable VIH VIH VIL VCC DOUT X X VCC High Z Output Disable X VIL X VCC High Z Output Disable X X VIH VCC High Z Program VPP X VIH VCC DIN Program Verify VIL VIH VIL VCC DOUT Program Inhibit VPP VIH VIL VCC DOUT OPERATING RANGE RANGE TEMPERATURE VCC 0°C to +70°C +5V ± 10% Industrial –40°C to +85°C +5V ± 10% Military –55°C to +125°C +5V ± 10% Commercial DC READ CHARACTERISTICS Over Operating Range. (See Above) SYMBOL TEST CONDITIONS MIN MAX UNITS VIL Input Low Voltage (Note 3) –0.1 0.8 V VIH Input High Voltage (Note 3) 2.0 VCC + 0.3 V VOL Output Low Voltage IOL = 16 mA 0.4 V VOH Output High Voltage IOH = –4 mA ICC1 ICC2 ILI ILO NOTES: 2-56 PARAMETER VCC Active Current (CMOS) VCC Active Current (TTL) 2.4 V VCC = 5.5 V, f = 0 MHz (Note 1), Comm'l 30 mA Output Not Loaded Industrial 35 mA Add 3 mA/MHz for AC Operation Military 35 mA VCC = 5.5 V, f = 0 MHz (Note 2), Comm'l 50 mA Output Not Loaded Industrial 60 mA Add 3 mA/MHz for AC Operation Military 60 mA Input Leakage Current VIN = 5.5V or Gnd –10 10 µA Output Leakage Current VOUT = 5.5 V or Gnd –10 10 µA 1. CMOS inputs: GND ± 0.3V or VCC ± 0.3V. 2. TTL inputs: VIL ≤ 0.8V, VIH ≥ 2.0V. 3. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. WS57C71C AC READ CHARACTERISTICS Over Operating Range. (See Above) PARAMETER SYMBOL 57C71C-35 57C71C-45 57C71C-55 57C71C-70 MIN MIN MIN MIN MAX MAX MAX Address to Output Delay tACC 35 45 55 70 CS to Output Delay tCS 15 20 20 30 Output Disable to Output Float* tDF 20 20 20 25 Address to Output Hold tOH 0 0 0 UNITS MAX ns 0 *Sampled, Not 100% Tested. AC READ TIMING DIAGRAM ADDRESSES VALID tACC tOH CSX, CS2 tCS OUTPUTS VALID tDF 2-57 WS57C71C CAPACITANCE (4) TA = 25°C, f = 1 MHz SYMBOL PARAMETER CONDITIONS TYP (5) MAX UNITS VIN = 0V 4 6 pF C IN Input Capacitance C OUT Output Capacitance VOUT = 0V 8 12 pF C VPP VPP Capacitance VPP = 0 V 18 25 pF NOTES: 4. This parameter is only sampled and is not 100% tested. 5.Typical values are for TA = 25°C and nominal supply voltages. TEST LOAD (High Impedance Test Systems) A.C. TESTING INPUT/OUTPUT WAVEFORM 98 Ω 2.01 V 3.0 1.5 D.U.T. 30 pF (INCLUDING SCOPE AND JIG CAPACITANCE) 0.0 TEST POINTS 1.5 A.C. testing inputs are driven at 3.0 V for a logic "1" and 0.0 V for a logic "0." Timing measurements are made at 1.5 V for input and output transitions in both directions. NOTE: 6. Provide adequate decoupling capacitance as close as possible to this device to achieve the published A.C. and D.C. parameters. A 0.1 microfarad capacitor in parallel with a 0.01 microfarad capacitor connected between VCC and ground is recommended. Inadequate decoupling may result in access time degradation or other transient performance failures. 2-58 WS57C71C NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.60 40.0 35.0 1.40 DELTA Taa (ns) NORMALIZED I CC 30.0 1.20 1.00 25.0 20.0 15.0 10.0 0.80 5.0 0.60 0.0 4.0 4.5 5.0 5.5 6.0 0.0 200 SUPPLY VOLTAGE ( V ) 400 600 800 1000 CAPACITANCE ( pF ) NORMALIZED Taa vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.6 1.2 1.4 NORMALIZED I CC NORMALIZED Taa 1.1 1.2 1.0 1.0 0.9 0.8 0.6 0.8 -55 -35 -15 5 25 45 65 85 AMBIENT TEMPERATURE (°C ) 105 125 -55 -35 -15 5 25 45 65 85 105 125 AMBIENT TEMPERATURE (°C) 2-59 WS57C71C PROGRAMMING INFORMATION DC CHARACTERISTICS (TA = 25 ± 5°C, VCC = 6.25 V ± 0.25 V, VPP = 12.75 ± 0.25 V) SYMBOLS PARAMETER Input Leakage Current (VIN = VCC or Gnd) VPP Supply Current During Programming Pulse VCC Supply Current Output Low Voltage During Verify (IOL = 16 mA) Output High Voltage During Verify (IOH = –4 mA) ILI IPP ICC VOL VOH NOTE: MIN MAX UNITS –10 10 µA 60 mA 25 mA 0.45 V 2.4 V 7. VPP must not be greater than 13 volts including overshoot. AC CHARACTERISTICS (TA = 25 ± 5°C, VCC = 6.25 V ± 0.25 V, VPP = 12.75 ± 0.25 V) SYMBOLS PARAMETER MIN tAS Address Setup Time tDF Chip Disable Setup Time tDS Data Setup Time tPW Program Pulse Width tDH Data Hold Time tCS Chip Select Delay tRF VPP Rise and Fall Time TYP MAX 2 µs 30 2 200 2 30 1 ADDRESS STABLE tAS VIH DATA OUT VIL tDF tPW tDS tDH VPP VIH CS1/VPP VIL tRF tRF VIH DON'T CARE CS2 VIL VIH CS3 VIL 2-60 ns µs VIH DATA IN µs µs PROGRAMMING WAVEFORM VIL ns µs 100 ADDRESSES UNITS tCS WS57C71C ORDERING INFORMATION PART NUMBER WS57C71C-35J WS57C71C-35L WS57C71C-35T WS57C71C-45CI WS57C71C-45D WS57C71C-45J WS57C71C-45T WS57C71C-45TMB WS57C71C-55CMB WS57C71C-55D WS57C71C-55DMB WS57C71C-55J WS57C71C-55JI WS57C71C-55L WS57C71C-55T WS57C71C-55TI WS57C71C-55TMB WS57C71C-70L WS57C71C-70T WS57C71C-70TMB SPEED (ns) 35 35 35 45 45 45 45 45 55 55 55 55 55 55 55 55 55 70 70 70 PACKAGE TYPE 32 Pin PLDCC 32 Pin CLDCC 28 Pin CERDIP, 0.3" 32 Pad CLLCC 28 Pin CERDIP, 0.6" 32 Pin PLDCC 28 Pin CERDIP, 0.3" 28 Pin CERDIP, 0.3" 32 Pad CLLCC 28 Pin CERDIP, 0.6" 28 Pin CERDIP, 0.6" 32 Pin PLDCC 32 Pin PLDCC 32 Pin CLDCC 28 Pin CERDIP, 0.3" 28 Pin CERDIP, 0.3" 28 Pin CERDIP, 0.3" 32 Pin CLDCC 28 Pin CERDIP, 0.3" 28 Pin CERDIP, 0.3" WSI PACKAGE OPERATING TEMPERATURE MANUFACTURING DRAWING RANGE PROCEDURE J4 L3 T2 C2 D2 J4 T2 T2 C2 D2 D2 J4 J4 L3 T2 T2 T2 L3 T2 T2 Comm’l Comm’l Comm’l Industrial Comm’l Comm’l Comm’l Military Military Comm’l Military Comm’l Industrial Comm’l Comm’l Industrial Military Comm’l Comm’l Military Standard Standard Standard Standard Standard Standard Standard MIL-STD-883C MIL-STD-883C Standard MIL-STD-883C Standard Standard Standard Standard Standard MIL-STD-883C Standard Standard MIL-STD-883C NOTE: 8. The actual part marking will not include the initials "WS." PROGRAMMING/ALGORITHMS/ERASURE/PROGRAMMERS REFER TO PAGE 5-1 The WS57C71C is programmed using Algorithm D shown on page 5-9. Return to Main Menu 2-61