Preliminary Revised June 2005 USB1101 USB 2.0 FS Peripheral Transceiver (Preliminary) General Description Features The USB1101 provides a USB FS Transceiver functionality with voltage level translation that is compliant to USB Specification Rev 2.0. The device allows interfacing of USB Application specific devices with supply voltages ranging from 1.65V to 3.6V with the physical layer of Universal Serial Bus. It is capable of operating at 12Mbits/s (full speed) data rates and hence is fully compliant to USB Specification Rev 2.0. It supports the DAT_VP/SE0_VM interface on the host side but offers reduced pin count and package size. The USB1101 has host side supply rail for 1.65V to 3.6V. ■ Complies with USB Specification Rev 2.0 ■ Supports DAT_VP/SE0_VM host mode ■ Utilizes digital inputs and outputs to transmit and receive USB cable data ■ Supports full speed (12Mbits/s) data rates ■ Ideal for portable electronic devices ■ MicroPak¥ technology package (10 pin) 1.6mm x 2.1mm ■ Host side VCCIO 1.65V to 3.6V Applications • PDA • PC Peripherals • Cellular Phones • MP3 Players • Digital Cameras • Information Appliance Ordering Code: Order Package Package Number Number Top Mark MAC010A UB USB1101L10X Package Description Supplied As 10-Lead MicroPak, 1.6 mm x 2.1mm 5k Units on Tape and Reel Connection Diagram (Bottom View) MicroPak¥ is a trademark of Fairchild Semiconductor Corporation. © 2005 Fairchild Semiconductor Corporation DS500923 www.fairchildsemi.com USB1101 USB 2.0 FS Peripheral Transceiver (Preliminary) June 2005 USB1101 Preliminary Pin Description Pin Number Pin Name I/O Pin Description 1 Config I USB connect or disconnect software control input. Configures 3.3V to internal 1.5k: resistor on D when HIGH. If device is used as Downstream port then this pin is hard-wired to GND. 2 OE I Output Enable (active LOW) When OE L transmit mode is enabled When OE H receive mode (CMOS level is relative to V CCIO) is enabled. 3 DAT_VP I/O When in transmit mode(Note 2) DAT_VP is a single-ended host data input (CMOS level relative to VCCIO). When in receive mode(Note 1) and Suspnd L DAT_VP is a single ended data output comprised of the differential input data from the D/D inputs (see Table 2); When in receive mode(Note 1) with Suspnd H DAT_VP outputs the D data. (see Table 1 and Table 2) Output drive is 2mA (min) buffer 4 SE0_VM I/O When in transmit mode(Note 2) SE0_VM is a data input (CMOS level relative to VCCIO). When in receive mode(Note 1) and Suspnd L, SE0_VM is used as an output (see Table 2) (see Table 1 and Table 2). Output drive is 4ma (min) buffer 5 GND GND 6 Suspnd I 7, 8 D, D AI/O Data, Data. Differential data bus conforming to the USB standard 9 VCCIO Pwr Supply Voltage for host side digital I/O pins (1.65V to 3.6V) 10 VCC Pwr Supply Voltage Input (3.0V to 3.6V) Note 1: OE H Note 2: OE L GND Enables a low power state (CMOS level is relative to VCCIO). In receive mode(Note 1) with Suspnd L the DAT_VP pin will be a function of the D/D lines. In receive mode(Note 1) with Suspnd H DAT_VP will have the value of D such that the device can still monitor out-of-suspend signaling. Functional Description The USB1101 transceiver is designed as an Upstream facing port device to convert CMOS data into USB differential bus signal levels and to convert USB differential bus signal to CMOS data. If you wish to use these as downstream devices, Config must be hard-wired to GND. The USB1101 supports the DAT_VP/SE0_VM format from the OTG Transceiver Specification using the DAT_SE0 Mode. Table 1 describes the specific pin functionality selection and Table 2 describes the specific Truth Tables for Driver, Receiver, and Suspended operating functions. To minimize EMI and noise the outputs are edge rate controlled with the rise and fall times controlled and defined for full speed data rates only (12Mbits/s). The rise and fall times are balanced between the differential pins to minimize skew. The USB1101 has the capability of serving Self Powered power supply configurations only but interfaces to mixed voltage supply applications. TABLE 1. Function Select Suspnd OE D, D DAT_VP SE0_VM Function L L Transmitting Host Data Input SE0_VM Host Input Normal Driving L H Receiving (Note 3) D, D Diff Output SE0_VM Output Receiving H L Transmitting (Note 4) Host Data Input SE0_VM Host Input Driving while Suspended H H Driver is 3-STATE (Note 4) DAT_VP Output SE0_VM Output Suspended (Internal Low Power Mode) Note 3: Signal levels is function of connection, Config and/or pull-up/pull-down resistors. Note 4: For Suspnd HIGH mode the differential receiver is inactive. www.fairchildsemi.com 2 Preliminary USB1101 TABLE 2. Driver, Receiver, and Suspend Function Select Suspnd L Transmit Mode Inputs Outputs OE DAT_VP SEO_VM D D L L L L H Differential Logic 0 L H L H L Differential Logic 1 L L H L L SE0 L H H L L SE0 Suspnd L Receive Mode Inputs Outputs OE D D DAT_VP SEO_VM H L L DIFF (Note 5) H H H L H L H L H L L H H H DIFF (Note 5) L Suspnd L Receive Mode While Suspended Inputs Outputs OE D D DAT_VP SEO_VM H L L L (Note 6) H H H L H (Note 6) L H L H L (Note 6) L H H H H (Note 6) L Suspnd H Transmit Mode Inputs Outputs OE DAT_VP SEO_VM D D L L L L H Differential Logic 0 L H L H L Differential Logic 1 L L H L L SE0 L H H L L SE0 Note 5: DIFF denotes that the output of the differential receiver is output via DAT_VP when Suspnd L. This output should also not be gated by the SE0 or SE1 condition when a skew between D and D signals could result in the short SE0 or SE1 conditions. Please refer to Expectation Notes for further information. Note 6: This is the internal single ended output that is output on to DAT_VP when Suspnd H and in receive mode. Power Supply Configurations and Options the D and D bus lines. Internally the circuitry limits leakage from D and D pins (maximum 10PA) and VCCIO such that the device is in low power state. The modes of power supply operation include: 1. Self Powered Mode: VCC is connected to 3.3V source (3.0V to 3.6V). This external supply connection provides the 3.3V for the USB pull-up source, the receiver input and driver output circuitry. 2. Sharing Mode: VCCIO is connected and VCC is d 0.8V. In this mode the D and D pins are 3-STATE and the USB1101 allows external signals up to 3.6V to share 3. Disable Mode: VCCIO is d 0.5V and VCC is connected. In this mode the D and D pins are 3-STATE and the device is in low power state. A summary of the Supply Configuration is described in Table 3. TABLE 3. Power Supply Configuration Options Pin Power Supply Mode Configuration Sharing Self Powered Disable VCC d 0.8V or Not Connected Connected to 3.3V Source Connected to 3.3V Source VCCIO 1.65V to 3.6V Source 1.65V to 3.6V Source d 0.5V or Not Connected D, D 3-STATE Function of Mode Set Up 3-STATE DAT_VP, SE0_VM H Function of Mode Set Up (Invalid) 3 www.fairchildsemi.com USB1101 Preliminary Absolute Maximum Ratings(Note 7) Symbol Parameter Conditions VCC Supply Voltage VCCIO I/O Supply Voltage IIK DC Input Current VI DC Input Voltage (Note 8) IOK DC Output Diode Current VO ! VCC or 0 VO DC Output Voltage (Note 8) IO DC Output Source or Sink VO Limits Min Max 0.5 0.5 4.6 Units V 4.6 V 18.0 VCCIO 0.5 r18.0 VCCIO 0.5 mA r12.0 r12.0 r100 mA mA 2000 TBD V 200 TBD V 1000 2000 V VI 0 0.5 0.5 V mA V 0 to VCC Current for D, D Pins SE0_VM/DAT_VP ICC, IGND DC VCC or GND Current VESD ESD Immunity Voltage IO, GND, VCC HBM (Mil-std. 883E) Pins (Note 8) MM (ESD_STM 5.2) VCCIO 0.5 Pins (Note 9) CDM (ESD_STM 5.3.1) IO, GND, VCC Pins (Note 10) HBM (Mil-std. 883E) TSTO Storage Temperature Range PTOT Power Dissipation Pins D, D (Note 11) TBD TBD V USB Connector TBD TBD V 40.0 125 qC 60.0 mW ICC System ESD Testing System ESDsys Parameter IEC61000-4-2 (Note 12) Conditions USB Connector Limits Min Max TBD TBD Units V Recommended Operating Conditions Symbol Parameter Conditions Limits Min Max Units VCC DC Supply Voltage 3.0 3.6 VCCIO I/O DC Voltage 1.65 3.6 V VI DC Input Voltage Range 0 3.6 V VAI/O DC Input Range for AI/O TAMB Operating Ambient Temperature Pins D and D V 0 3.6 V 40.0 85.0 qC Note 7: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics table are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 8: HBM: Mil-Std_883E compliance. Socketed testing of three units per zap voltage (3 pulses and 3 pulses). IO v IO, IO v GND, IO v VCC, VCC v GND. Note 9: MM: ESD_STM 5.2 compliance. Socketed testing of three units per zap voltage (3 pulses and 3 pulses). IO v IO, IO v GND, IO v VCC, VCC v GND. Note 10: CDM: ESD_STM 5.3.1 compliance. Devices (3 per level) are charged, entire package, and discharged through a single pin contacted to each individual pin on the DUT. NC pins are not stressed. Positive and negative charge is placed on the DUT (sitting atop a metallic plate). Maximum stress voltage applicable at FSME is 2000V. Note 11: This test is an extension of HBM Mil_Std 883E. However, this test is confined to the differential pins only. Note 12: IEC61000-4-2 system level testing: System level testing done on this parts evaluation system boar. www.fairchildsemi.com 4 Preliminary 3.0V to 3.6V, VCCIO 1.65V to 3.6V Limits Symbol Parameter Conditions Temperature Min ICC Operating Supply Current (VCC) Transmitting and receiving at 12Mbit/s; ICC(DISABLE) 8.0 mA PA Supply Current During FS IDLE and IDLE: VD t 2.7, VD d 1.3V; 300 SE0 (VCC) SE0: VD d 0.3V, VD d 1.3V (Note 14) Disabled Supply Current Suspnd Config D H or L; OE H or L; 20.0 PA 40.0 PA L D DAT_VP SE0_VM = H or L d 0.3V VCCIO ICC(SUSPNDR) Max 4.0 50pF (D, D) CLOAD ICC(IDLE) 40qC to 85qC Units Typ Suspend VCC Supply Current Suspnd (Internal Resistor Pull-up) D ICCIO(STATIC) I/O Static VCCIO Supply Current IDLE, SE0 20.0 PA ICCIO(SHARING) I/O Sharing Mode VCCIO Supply Current VCC Not Connected or d 0.5V or 0V 20.0 PA Suspnd 20.0 PA 10.0 PA ICCIO(SUSPNDR) Suspend VCCIO Supply Current OE IDr(SHARING) Sharing Mode Load Current on D, D Pins Config H Config HIGH; HIGH or LOW D Open VCC Not Connected or d 0.8V Config VCCTH OE Open LOW; VDr VCC Threshold Detection Voltage 3.0 d VCC d 3.6V (Self Powered) Supply Lost 10.0 3.6V 0.8 Supply Present VCCHYS VCC Threshold Detection Hysteresis Voltage VCCIO VCCIOTH VCCIO Threshold Detection Voltage 3.0V d VCC d 3.6V 1.8V 450 Supply Lost VCCIOHYS VCCIO Threshold Detection Hysterias Voltage VCC mV 0.5 Supply Present V 2.4 (Note 15) V 1.4 3.3V 450 mV Note 13: Not tested in production, value based on characterization. Note 14: Excludes any current from load and VSW current to the 1.5k: and 15k: pull-up/pull-down resistors (200 PA typ). Note 15: Minimum value for VCCTH 2.0V for supply present condition for VCCIO 5 1.8V. www.fairchildsemi.com USB1101 DC Electrical Characteristics (Supply Pins) Over recommended range of supply voltage and operating free air temperature (unless otherwise noted): VCC USB1101 Preliminary DC Electrical Characteristics (Digital Pins - excludes D, D Pins) Over recommended range of supply voltage and operating free air temperature (unless otherwise noted). VCCIO 1.65V to 3.6V Limits Symbol Parameter Condition Temperature 40qC to 85qC Min Unit Max INPUT LEVELS VIL LOW Level Input Voltage VIH HIGH Level Input Voltage 0.3 VCCIO 0.6 VCCIO V V OUTPUT LEVELS VOL VOH LOW Level Output Voltage HIGH Level Output Voltage IOL 2 mA 0.4 IOL 100 PA 0.15 IOH 2 mA VCCIO 0.4 IOH 100 PA VCCIO0.15 V V LEAKAGE CURRENT ILI Input Leakage Current VCCIO r1.0 PA 10.0 pF 40qC to 85qC Unit 1.65V to 3.6V CAPACITANCE CIN, CI/O Input Capacitance Pin to GND DC Electrical Characteristics (Analog I/O Pins - D, D Pins) Over recommended range of supply voltage and operating free air temperature (unless otherwise noted). VCC 3.0V to 3.6V Limits Symbol Parameter Condition Temperature Min Max INPUT LEVELS - Differential Receiver VDI Differential Input Sensitivity VCM Differential Common Mode Voltage | VI(D) - VI(D) | 0.2 0.8 V 2.5 V 0.8 V 0.7 V 0.3 V INPUT LEVELS - Single-ended Receiver VIL LOW Level Input Voltage VIH HIGH Level Input Voltage 2.0 VHYS Hysteresis Voltage 0.4 V Output Levels VOL LOW Level Output Voltage Config VOH HIGH Level Output Voltage RL HIGH for Internal 1.5k: to 3.6V 15K: to GND 2.8 (Note 16) V LEAKAGE CURRENT IOZ Input Leakage Current OFF State r1.0 PA 20.0 pF 44.0 : CAPACITANCE CI/O I/O Capacitance Pin to GND ZDRV Driver Output Impedance Steady State ZIN Driver Input Impedance RPU Pull-up Resistance (Note 18) RSW Switch Resistance RESISTANCE Note 16: If VOHmin M: 10.0 IDLE 900 VCC 0.2V. Note 17: Includes external 33: r 1% on both pins D and D. Note 18: See USB2.0 Resistor ECN. Note 19: Not production tested, guaranteed by design. www.fairchildsemi.com 34.0 (Note 17) 6 1575 : 10.0 (Note 19) : Preliminary USB1101 AC Electrical Characteristics (A I/O Pins, Full Speed) Over recommended range of supply voltage and operating free air temperature (unless otherwise noted). VCC 3.0V to 3.6V, VCCIO 1.65V to 3.6V, CL 50pF Limits Symbol Parameter Condition Temperature Min 40qC to 85qC Typ Unit Max Figure Number DRIVER CHARACTERISTICS 50 125pF tR Output Rise Time CL 4.0 20.0 tF Output Fall Time 10% to 90% |VOH - VOL | 4.0 20.0 tRFM Rise/Fall Time Match tR / tF Excludes First Transition from IDLE State 90.0 111.1 % VCRS (Note 20) Output Signal Crossover Voltage Excludes First Transition from IDLE State 1.3 2.0 V VCC/2 r 200 mV (Note 21) ns Figures 1, 5 Figures 2, 4 DRIVER TIMING tPLH Propagation Delay 18.0 tPHL (DAT_VP, SE0_VM to D / D) 18.0 tPHZ Driver Disable Delay 15.0 tPLZ (OE to D / D) 15.0 tPZH Driver Enable Delay 15.0 tPZL (OE to D / D) 15.0 ns Figures 2, 5 ns Figures 4, 6 ns Figures 4, 6 ns Figures 3, 7 ns Figures 3, 7 RECEIVER TIMING tPLH Propagation Delay (Diff) 18.0 tPHL (D / D to DAT_VP) 18.0 tPLH Single Ended Receiver Propagation Delay 18.0 tPHL (D / D to DAT_VP, SE0_VM) 18.0 tPLH Suspend to DAT_VP 15.0 tPHL 15.0 ns Note 20: Not production tested, guaranteed by design. Note 21: Typical conditions (25qC, 3.3V). 7 www.fairchildsemi.com USB1101 Preliminary Loading and Waveforms FIGURE 1. Rise and Fall Time FIGURE 2. DAT_VP, SE0_VM to D / D FIGURE 3. D / D to DAT_VP, SE0_VM FIGURE 4. OE to D / D FIGURE 5. Load for D / D FIGURE 6. Load for Enable and Disable Time FIGURE 7. Load for DAT_VP, SE0_VM in Receive Mode www.fairchildsemi.com 8 Preliminary Tape Format For Micropak 10 Package Tape Number Cavity Section Cavities Status Status Leader (Start End) 125 (typ) Empty Sealed Designator L10X Cover Tape Carrier 5000 Filled Sealed Trailer (Hub End) 75 (typ) Empty Sealed REEL DIMENSIONS inches (millimeters) Tape Size 8 mm A B C D N W1 W2 W3 7.0 0.059 0.512 0.795 2.165 0.331 0.059/0.000 0.567 W1 0.078/0.039 (177.8) (1.50) (13.00) (20.20) (55.00) (8.40 1.50/0.00) (14.40) (W1 2.00/1.00) 9 www.fairchildsemi.com USB1101 Tape and Reel Specification USB1101 USB 2.0 FS Peripheral Transceiver (Preliminary) Preliminary Physical Dimensions inches (millimeters) unless otherwise noted 10-Lead MicroPak, 1.6 mm x 2.1mm Package Number MAC010A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10