VISHAY TFDT6502E-TR3

TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Fast Infrared Transceiver Module Family
(FIR, 4 Mbit/s) for 2.6 V to 5.5 V Operation
Description
The
TFDU6102E,
TFDS6402,
TFDS6502E,
TFDT6502E are a family of low–power infrared
transceiver modules compliant to the IrDA physical
layer standard for fast infrared data communication,
supporting IrDA speeds up to 4.0 Mbit/s (FIR),
HP-SIR, Sharp ASK and carrier based remote control
modes up to 2 MHz. Integrated within the transceiver
modules are a photo PIN diode, an infrared emitter
(IRED), and a low–power CMOS control IC to provide
a total front–end solution in a single package.
Vishay Telefunken’s FIR transceivers are available in
four package options, including our Baby Face
package (TFDU610xE), the standard setting, once
smallest FIR transceiver available on the market. This
wide selection provides flexibility for a variety of
applications and space constraints. The transceivers
are capable of directly interfacing with a wide variety
of I/O devices which perform the modulation/
demodulation
function,
including
National
Semiconductor’s PC87338, PC87108 and PC87109,
SMC’s FDC37C669, FDC37N769 and CAM35C44,
and Hitachi’s SH3. At a minimum, a current–limiting
resistor in series with the infrared emitter and a
VCC bypass capacitor are the only external
components required implementing a complete
solution.
Features
Compliant to the IrDA physical layer specification
(Up to 4 Mbit/s),
HP–SIR, Sharp ASK and TV Remote Control
High Efficiency Emitter
For 3.0 V and 5.0 V Applications
Baby Face (Universal) Package Capable of
Surface Mount Soldering to Side and Top View
Orientation
Operates from 2.6 V to 5.5 V within specification,
operational down to 2.4 V
Directly Interfaces with Various Super I/O and
Controller Devices
Low Power Consumption (3 mA Supply Current)
Power Shutdown Mode (1 A Shutdown Current)
Four Surface Mount Package Options
–
Universal (9.7 × 4.7 × 4.0 mm)
–
Side View (13.0 × 5.95 × 5.3 mm)
–
Top View (13.0 × 7.6 × 5.95 mm)
–
Dracula (11.2 × 5.6 × 2.2 mm)
Push-Pull-Receiver Output, grounded in
shutdown mode
Built–In EMI Protection – No External Shielding
Necessary
Few External Components Required
Backward Pin to Pin Compatible to all Vishay
Telefunken SIR and FIR Infrared Transceivers
Split power supply, transmitter and receiver can be
operated from two power supplies with relaxed
requirements, thus saving costs
Applications
Notebook Computers, Desktop PCs,
Palmtop Computers (Win CE, Palm PC), PDAs
Telecommunication Products
(Cellular Phones, Pagers)
Digital Still and Video Cameras
Internet TV Boxes, Video Conferencing Systems
Printers, Fax Machines, Photocopiers,
Screen Projectors
Document Number 82526
Rev. B1.6, 02–Nov–00
External Infrared Adapters (Dongles)
Medical and Industrial Data Collection Devices
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1
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Package Options
TFDU6102E
Baby Face (Universal)
weight 0.20 g
TFDS6402
Dracula Side View
weight 0.30 g
TFDS6502E
Side View
weight 0.39 g
TFDT6502E
Top View
weight 0.39 g
Ordering Information
Part Number
TFDU6102E–TR3
TFDU6102E–TT3
TFDS6402–TR3
TFDS6502E–TR3
TFDT6502E–TR3
Qty / Reel
1000 pcs
1000 pcs
1000 pcs
750 pcs
750 pcs
Description
Oriented in carrier tape for side view surface mounting
Oriented in carrier tape for top view surface mounting
Side View
Side View
Top View
Functional Block Diagram
VCC
Driver
Amplifier
Comparator
Rxd
IRED Anode
SD/Mode
AGC
Logic
Txd
IRED Cathode
Open Drain Driver
GND
Figure 1. Functional Block Diagram
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Document Number 82526
Rev. B1.6, 02–Nov–00
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Pin Description
Pin Number
“U” and “T” Option “S” Option
1
8
2
1
3
4
7
2
5
6
7
6
3
5
8
4
Function
IRED anode, to be externally connected
to VCC through a current control resistor.
This pin is allowed to be supplied from
an uncontrolled power supply separated
from the controlled VCC supply
IRED Cathode IRED cathode, internally connected to
driver transistor
Txd
Transmit Data Input
Rxd
Received Data Output, push-pull CMOS
driver output capable of driving a standard CMOS or TTL load. No external
pull-up or pull-down resistor is required.
Pin is floating when
device is in shutdown mode
SD/Mode
Shutdown/ Mode
VCC
Supply Voltage
Mode
HIGH: High speed mode;
LOW: Low speed mode, SIR only
(see chapter “Mode Switching”)
GND
Ground
14885
I/O
Active
I
O
HIGH
LOW
I
HIGH
IRED Anode
“U” Option Baby Face (Universal)
and Dracula
IRED
Description
Descri
tion
“S” Option Side View
“T” Option Top View
IRED
Detector
IRED
I
Detector
Detector
Figure 2. Pinnings
Document Number 82526
Rev. B1.6, 02–Nov–00
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TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Absolute Maximum Ratings
Reference point Pin: GND unless otherwise noted.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameters
Supply Voltage Range,
Transceiver
Supply Voltage Range,
Transmitter
Input Currents
Output Sinking Current
Power Dissipation
Junction Temperature
Ambient Temperature
Range (Operating)
Storage Temperature
Range
Soldering Temperature
Test Conditions
0 V <VCC2 <6 V
0 V <VCC1 <6 V
Min.
– 0.5
VCC2
– 0.5
Typ.
For all Pins, Except IRED
Anode Pin
See Derating Curve
Max.
6
Unit
V
6
V
10
mA
mA
mW
°C
°C
PD
TJ
Tamb
–25
25
350
125
+85
Tstg
–25
+85
°C
240
°C
130
600
mA
mA
See Recommended Solder
Profile (see Figure 11)
Average Output Current
Repetitive Pulsed Output <90 µs, ton <20%
Current
IRED Anode Voltage
Transmitter Data Input
Voltage
Receiver Data Output
Voltage
Virtual Source Size
Method:
(1–1/e) encircled energy
Maximum Intensity for
EN60825, 1997,
Class 1 Operation of
unidirectional operation,
IEC825–1 or EN60825–1 worst case test mode
(worst case IrDA FIR
pulse pattern)
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4
Symbol
VCC1
IIRED (DC)
IIRED (RP)
VIREDA
VTxd
– 0.5
– 0.5
6
VCC1 +0.5
V
V
VRxd
– 0.5
VCC1 +0.5
V
d
2.5
2.8
mm
320
mW/sr
Document Number 82526
Rev. B1.6, 02–Nov–00
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Electrical Characteristics
Tamb = 25_C, VCC = 2.6V to 5.5 V unless otherwise noted.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameters
Transceiver
Supply Voltage
Dynamic Supply Current
Standby Supply Current
Operating Temperature
Range
Output Voltage Low
Output Voltage High
Input Voltage Low
(Txd, SD/ Mode, Mode)
Input
In
ut Voltage High
(Txd, SD/ Mode, Mode)
Input Leakage Current
(Txd, SD/ Mode)
Input Leakage Current,
Mode
Input Capacitance
*)
**)
Test Conditions / Pins
Symbol
Min.
VCC
2.6
Typ.
Max.
Unit
5.5
V
Receive mode only.
In transmit mode, add additional 85 mA (typ) for IRED current
SD = Low, Ee = 0 klx
ICC
3
4.5
SD = Low, Ee = 1 klx *)
ICC
3
4.5
SD = High,
ISD
Mode = Floating,
T = 25°C, Ee = 0 klx
1
T = 25°C, Ee = 1 klx *)
1.5
SD = High, T = 85°C,
ISD
5
Mode = Floating,
Not Ambient Light
Sensitive
TA
–25
+85
Rload = 2.2 kW,
Cload = 15 pF
Rload = 2.2 kW,
Cload = 15 pF
CMOS level **)
TTL level, VCC ≥ 4.5 V
VOL
0.5
VOH
VCC–0.5
VIL
0
VIH
VIH
IL
IL
CI
0.8
mA
mA
µA
µA
µA
°C
V
V
0.8
V
0.9 x VCC
2.4
–10
+10
V
V
µA
–80
+80
µA
5
pF
Standard Illuminant A
The typical threshold level is between 0.5 x VCC/2 (VCC = 3 V) and 0.4 x VCC (VCC = 5.5 V) .
It is recommended to use the specified min/ max values to avoid increased operating current.
Document Number 82526
Rev. B1.6, 02–Nov–00
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TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Optoelectronic Characteristics
Tamb = 25_C, VCC = 2.6 V to 5.5 V unless otherwise noted.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameters
Receiver
Minimum Detection
Threshold Irradiance,
SIR Mode
Minimum Detection
Threshold Irradiance,
MIR Mode
Minimum Detection
Threshold Irradiance,
FIR Mode
Maximum Detection
Threshold Irradiance
Logic LOW Receiver
Input Irradiance
Rise Time of Output
Signal––,,,,klll
Fall Time of Output
Signal
Rxd Pulse Width of
Output Signal, 50%
SIR Mode
Rxd Pulse Width of
Output Signal, 50%
MIR Mode
Rxd Pulse Width of
Output Signal
Signal, 50%
FIR Mode
Stochastic Jitter,
Leading Edge,
FIR Mode
Latency
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Test Conditions
TFDS6502E/ TFDT6502E
9.6 kbit/s to 115.2 kbit/s
l = 850 nm to 900 nm
TFDU6102E, TFDS6402
9.6 kbit/s to 115.2 kbit/s
l = 850 nm to 900 nm
TFDS6502E/ TFDT6502E
1.152 Mbit/s
l = 850 nm to 900 nm
TFDU6102E, TFDS6402
1.152 Mbit/s
l = 850 nm to 900 nm
TFDS6502E/ TFDT6502E
4.0 Mbit/s
l = 850 nm to 900 nm
TFDU6102E, TFDS6402
4.0 Mbit/s
l = 850 nm to 900 nm
l = 850 nm to 900 nm
Symbol
Min.
Typ.
Max.
Unit
Ee
20
35
mW/m 2
Ee
25
40
mW/m 2
Ee
50
mW/m 2
Ee
65
mW/m 2
Ee
65
100
mW/m 2
Ee
85
100
mW/m 2
kW/m 2
Ee
5
10
Ee
4
10% to 90%, @2.2 kΩ, 15 pF
tr (Rxd)
10
40
ns
90% to 10%, @2.2 kΩ, 15 pF
tf (Rxd)
10
40
ns
Input pulse length 20 µs, 9.6 kbit/s
Input pulse length 1.41 ms,
115.2 kbit/s
Input pulse length 217 ns,
1.152 Mbit/s
tPW
tPW
1.2
1.2
µs
µs
tPW
110
20
1/2 bit
length
260
Input pulse length 125 ns, 4.0 Mbit/s
tPW
100
160
ns
Input pulse length 250 ns, 4.0 Mbit/s
tPW
200
290
ns
mW/m 2
10
±10
Input Irradiance = 100 mW/m2,
4.0 Mbit/s
tL
120
ns
ns
300
µs
Document Number 82526
Rev. B1.6, 02–Nov–00
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Optoelectronic Characteristics (continued)
Tamb = 25_C, VCC = 2.6 V to 5.5 V unless otherwise noted.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameters
Transmitter
IRED Operating Current
Output Radiant Intensity
(see Figure 3)
Output Radiant Intensity
Test Conditions
R1*) = 7.2 Ω, VCC = 5.0 V
VCC = 5.0 V, α = 0_, 15_
Txd = High, SD = Low, R1 = 7.2 Ω
VCC = 5.0 V, α = 0_, 15_
Txd = Low, SD = High,
(Receiver is inactive as long as
SD = High) R1 = 7.2 Ω
Output Radiant Intensity,
Angle of Half Intensity
Peak – Emission
Wavelength
Optical Output Pulse
Input pulse width 217 ns,
Duration
1.152 Mbit/s
Input pulse width 125 ns,
4 Mbit/s
Input pulse width 250 ns,
4 Mbit/s
Input pulse width t < 80 µs
Input pulse width t ≥ 80 µs
Optical Rise Time,
Fall Time
Optical Overshoot
*)
Symbol
ID
Ie
Min.
Typ.
Max.
Unit
120
0.4
170
0.55
350
A
mW/sr
0.04
mW/sr
Ie
±24
a
lP
880
topt
207
topt
topt
900
nm
217
227
ns
117
125
133
ns
242
250
258
ns
topt
tropt,
tfopt
°
µs
t
10
80
40
ns
10
%
R1: control series resistor for current limitation
Document Number 82526
Rev. B1.6, 02–Nov–00
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TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Recommended Circuit Diagram
The only required component for designing an
IrDA 1.3
solution
using
Vishay
Telefunken
transceivers is a current limiting resistor, R1, to the
IRED. However, depending on the entire system
design and board layout, additional components may
be required (see figure 3).
VCC2
R1
VCC1
IRED
Cathode
R2
Rxd
IRED
Anode
Txd
Rxd
TFDx6x0xE
C1
C2
Vcc
GND
GND
SD/Mode
Mode
SD/Mode
Txd
Note: outlined components are optional depending
on the quality of the power supply
Figure 3. Recommended Application Circuit
Vishay Telefunken transceivers integrate a sensitive
receiver and a built-in power driver. The combination
of both needs a careful circuit board layout. The use of
thin, long, resistive and inductive wiring should be
avoided. The inputs (Txd, SD/ Mode) and the output
Rxd should be directly (DC) coupled to the I/O circuit.
R1 is used for controlling the current through the
IR emitter. For increasing the output power of the
IRED, the value of the resistor should be reduced.
Similarly, to reduce the output power of the IRED, the
value of the resistor should be increased. For typical
values of R1 see figure 4. For IrDA compliant
operation, a current control resistor of 7.2 Ω is
recommended. For compensating losses of the cosmetic window, reducing that value to 5.6 Ω is
acceptable. The upper drive current limitation is
dependent on the duty cycle and is given by the
absolute maximum ratings on the data sheet.
R2, C1 and C2 are optional and dependent on the
quality of the supply voltage VCC and injected noise.
An unstable power supply with dropping voltage during
transmission may reduce sensitivity (and transmission
range) of the transceiver.
The placement of these parts is critical. It is strongly
recommended to position C2 as near as possible to the
transceiver power supply pins. An electrolytic
capacitor should be used for C1 while a ceramic
capacitor is used for C2.
Table 1. Recommended Application Circuit Components
Component
Recommended Value
C1
4.7 mF, Tantalum
C2
0.1 µF, Ceramic
R1
5 V supply voltage: 7.2 Ω , 0.25 W
(recommend using
two 3.6 W, 0.125 W resistors in series)
3.3 V supply voltage: 3.6 Ω , 0.25 W
(recommend using
two 1.8 W, 0.125 W resistors in series)
R2
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8
47 Ω , 0.125 W
Vishay Part Number
293D 475X9 016B 2T
VJ 1206 Y 104 J XXMT
CRCW–1206–3R60–F–RT1
CRCW–1206–1R80–F–RT1
CRCW–1206–47R0–F–RT1
Document Number 82526
Rev. B1.6, 02–Nov–00
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
drivers are available from SMSC and Vishay
Semiconductor GmbH. This software is intended to
work with Windows 95, too. Alternatively the
HP/ Sharp settings can be selected. The Microsoft
Operating
Systems
NT 5.0
Beta 2
and

Windows 2000 provide Miniport device drivers.
500
max. intensity in
emission cone 15°
5.25V
5.0V
Intensity (mW/sr)
400
min. Rdson, min. VF
300
Mode Switching
5.0V
200
max.Rdson, max.VF
100
Vcc=4.75V
min. intensity in emission cone 15°
0
0
2
4
6
8
10
12
14
16
Current Control Resistor ( W )
14379
Figure 4. Intensity Ie vs. Current Control Resistor R1,
5 V Applications
700
max. intensity in
emission cone 15°
3.6V
Intensity (mW/sr)
600
min. Rdson, min. VF
500
min. intensity in
emission cone 15°
400
3.3V
300
max. Rdson, max. VF
200
The TFDU6102E, TFDS6402, TFDS6502E and
TFDT6502E do not power on with a default mode,
therefore the data transfer rate has to be set by a programming sequence using the Txd and SD/ Mode
inputs as described below or selected by setting the
Mode Pin. The Mode Pin can be used to statically set
the mode (Mode Pin: LOW: SIR, HIGH: 0.576 Mbit/s
to 4.0 Mbit/s). When using the Mode Pin, the standby
current may increase to about 50 to 60 mA when high
or low. If not used or in standby mode, the mode input
should float to minimize standby current. The low
frequency mode covers speeds up to 115.2 kbit/s. Signals with higher data rates should be detected in the
high frequency mode. Lower frequency data can also
be received in the high frequency mode but with reduced sensitivity. To switch the transceivers from low
frequency mode to the high frequency mode and vice
versa, the programming sequences described below
are required.
50%
SD/Mode
3.3V
100
Vcc=3.0V
0
ts
0
15111
2
4
6
8
10
Current Control Resistor ( W )
th
12
Figure 5. Intensity Ie vs. Current Control Resistor R1,
3 V Applications
In addition, when connecting the described circuit to
the power supply, low impedance wiring should be
used.
I/O and Software
High : FIR
Txd
50%
50%
Low : SIR
14873
Figure 6. Mode Switching Timing Diagram
Setting to the High Bandwidth Mode
(0.576 Mbit/s to 4.0 Mbit/s)
In the description, already different I/Os are
mentioned. Differnt combinations are tested and the
function verified with the special drivers available from
the I/O suppliers. In special cases refer to the I/O
manual, the Vishay application notes, or contact
directly Vishay Sales, Marketing or Application.
1. Set SD/MODE input to logic “HIGH”.
Control: Differences to TFDx6000 Series
4. After waiting th ≥ 200 ns Txd can be set to logic
“LOW”. The hold time of Txd is limited by the
maximum allowed pulse length.
For applications using I/Os from NSC, Winbond and TI
no software upgrade is necessary. In combination with
the latest SMSC controllers for Microsoft
Windows 98 a software upgrade is necessary,
Document Number 82526
Rev. B1.6, 02–Nov–00
2. Set Txd input to logic “HIGH”. Wait ts ≥ 200 ns.
3. Set SD/MODE to logic “LOW” (this negative edge
latches state of Txd, which determines speed
setting).
Txd is now enabled as normal Txd input for the high
bandwidth mode.
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TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Setting to the Lower Bandwidth Mode
(2.4 kbit/s to 115.2 kbit/s)
3. Set SD/MODE to logic “LOW” (this negative edge
latches state of Txd, which determines speed
setting).
1. Set SD/MODE input to logic “HIGH”.
4. Txd must be held for th ≥ 200 ns.
2. Set Txd input to logic “LOW”. Wait ts ≥ 200 ns.
Txd is now enabled as normal Txd input for the lower
bandwidth mode.
Recommended SMD Pad Layout
The leads of the device should be soldered in the center position of the pads.
7x1=7
0.6 (≤ 0.7)
2.5 (≥ 2.0)
1
8
1
16524
Figure 7. TFDU6102E BabyFace (Universal)
Figure 8. TFDS6402 (Dracula)
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Document Number 82526
Rev. B1.6, 02–Nov–00
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
11.8
5.08
2.54
8
7
2.54
6
5
1.8
0.63
1.1
1.0
0.63
8.3
1
2.2
1
2.54
2
2.54
3
4
5.08
15069
Figure 9. TFDS6502E Side View Package
Pad 1 is longer to designate Pin 1 connection to transceiver.
8.89
1.27
0.8
1.8
1
8
15068
Figure 10. TFDT6502E Top View Package
Pad 1 is longer to designate Pin 1 connection to transceiver.
Note: Leads of the device should be at least 0.3 mm within the ends of the pads.
Recommended Solder Profile
10 s max.
@ 230°C
210
2 - 4°C/s
180
150
120
120 - 180 s
90
60
90 s max.
2 - 4°C/s
30
Peak Operating Current ( mA )
600
240
Temperature ( ° C )
Current Derating Diagram
0
0
50
100
14874
150 200 250
Time ( s )
300
Document Number 82526
Rev. B1.6, 02–Nov–00
400
300
200
Current derating as a function of
the maximum forward current of
IRED. Maximum duty cycle: 25%.
100
0
–40 –20 0
350
Figure 11. Recommended Solder Profile
500
14875
20 40 60 80 100 120 140
Temperature ( °C )
Figure 12. Current Derating Diagram
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TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
TFDU6102E – Baby Face (Universal) Package
(Mechanical Dimensions)
12249
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12
Document Number 82526
Rev. B1.6, 02–Nov–00
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
TFDS6402 Package (Mechanical Dimensions)
15971
Document Number 82526
Rev. B1.6, 02–Nov–00
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13
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductors
TFDS6502E – Side View Package (Mechanical Dimensions)
14322
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14
Document Number 82526
Rev. B1.6, 02–Nov–00
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductors
TFDT6502E – Top View Package (Mechanical Dimensions)
14325
Document Number 82526
Rev. B1.6, 02–Nov–00
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15
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductors
Revision History:
B1.1, 01/03/1999: New edition for optimized E family. TFDxxx01E – RXD output is grounded when the device
is switched to shutdown mode.
B1.2, 15/03/1999: A clean tri-state version with floating output in shutdown mode was added as 02 version. The
output radiant intensity was increased.
B1.4a, 26/10/1999:TR3 changed to TR4 for 01 types, weight of packages added.
B1.4b, 22/11/1999:Max. operating current changed from 4.0 mA to 4.5 mA, Dracula package version added,
some typos corrected.
B1.5, 13/10/2000: First typos corrected
B1.6, 02/11/2000: SMD pad layout tolerances added
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Document Number 82526
Rev. B1.6, 02–Nov–00
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductors
Ozone Depleting Substances Policy Statement
It is the policy of Vishay Semiconductor GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating
systems with respect to their impact on the health and safety of our employees and the public, as well as
their impact on the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and
forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban
on these substances.
Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of
ODSs listed in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting
substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer application
by the customer. Should the buyer use Vishay Semiconductors products for any unintended or unauthorized application, the
buyer shall indemnify Vishay Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or
indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use.
Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 ( 0 )7131 67 2831, Fax number: 49 ( 0 )7131 67 2423
Document Number 82526
Rev. B1.6, 02–Nov–00
www.vishay.com
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