TSM55N03 Preliminary N-Channel Enhancement Mode MOSFET VDS = 25V ID = 55A RDS (on), Vgs @ 10V, Ids @ 30A = 6mΩ RDS (on), Vgs @ 4.5V, Ids @ 30A = 9mΩ Pin assignment: 1. Gate 2. Drain 3. Source Features High Density Cell Design for Ultra Low On-Resistance Fully Characterized Avalanche Voltage and Current Improved Shoot-Through FOM Drivers Advanced trench process technology Block Diagram Specially Designed for DC/DC Converters and Motor Ordering Information Part No. Packing Package TSM55N03CP Tape & Reel TO-252 Absolute Maximum Rating (TA = 25 oC unless otherwise noted) Parameter Symbol Limit Unit Drain-Source Voltage VDS 25 V Gate-Source Voltage VGS ±20 V Continuous Drain Current ID 55 Pulsed Drain Current IDM 350 Maximum Power Dissipation TA = 25 oC o TA = 75 C Operating Junction Temperature PD Single Pulse Drain to Source Avalanche Energy (VDD = 100V, VGS=10V, IAS=2A, L=10mH, RG=25Ω) 70 W 42 W/oC +150 o C TJ, TSTG - 55 to +150 o C EAS 300 mJ Symbol Limit Unit TL 10 S Rθjc 1.8 Rθja 40 TJ Operating Junction and Storage Temperature Range A Thermal Performance Parameter Lead Temperature (1/8” from case) Junction-to-case Thermal Resistance Junction to Ambient Thermal Resistance (PCB mounted) Note: 1. Maximum DC current limited by the package 2. 1-in2 2oz Cu PCB board TSM55N03 1-3 2005/04 rev. B o C/W Electrical Characteristics TJ = 25 oC, unless otherwise noted Parameter Conditions Symbol Min Typ Max Unit Static Drain-Source Breakdown Voltage VGS = 0V, ID = 250uA BVDSS 30 -- -- V Drain-Source On-State Resistance VGS = 4.5V, ID = 30A RDS(ON) -- 7.5 9.0 mΩ Drain-Source On-State Resistance VGS = 10V, ID = 30A RDS(ON) -- 4.5 6.0 mΩ Gate Threshold Voltage VDS = VGS, ID = 250uA VGS(TH) 1.0 1.6 3.0 V Zero Gate Voltage Drain Current VDS = 25V, VGS = 0V IDSS -- -- 1.0 uA Gate Body Leakage VGS = ± 20V, VDS = 0V IGSS -- -- ± 100 nA Rg -- -- -- gfs -- -- -- Qg -- 26 -- Qgs -- 6.0 -- Qgd -- 5.0 -- td(on) -- 17 -- tr -- 3.5 -- td(off) -- 40 -- tf -- 6.0 -- Ciss -- 2134 -- Coss -- 343 -- Crss -- 134 -- IS -- -- 20 A VSD -- 0.85 1.3 V Gate Resisrance Forward Transconductance VDS =15V, ID = 15A S Dynamic Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 15V, ID = 25A, VGS = 10V VDD = 15V, RL = 15Ω, ID = 1A, VGEN = 10V, RG = 6Ω VDS = 15V, VGS = 0V, f = 1.0MHz nC nS pF Source-Drain Diode Max. Diode Forward Current Diode Forward Voltage IS = 20A, VGS = 0V Note: 1. pulse test: pulse width <=300uS, duty cycle <=2% 2. Negligible, Dominated by circuit inductance. TSM55N03 2-3 2005/04 rev. B TO-252 Mechanical Drawing E J A A B C D E F G TO-252 DIMENSION MILLIMETERS INCHES MIN MAX MIN MAX 6.570 6.840 0.259 0.269 9.250 10.400 0.364 0.409 0.550 0.700 0.022 0.028 2.560 2.670 0.101 0.105 2.300 2.390 0.090 0.094 0.490 0.570 0.019 0.022 1.460 1.580 0.057 0.062 H I J 0.520 5.340 1.460 F DIM I B G D TSM55N03 C H 3-3 0.570 5.550 1.640 0.020 0.210 0.057 2005/04 rev. B 0.022 0.219 0.065