0 XC9572XL High Performance CPLD DS057 (v1.1) August 28, 2000 0 5 Features • • • • • • • • • • • 5 ns pin-to-pin logic delays System frequency up to 178 MHz 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (38 user I/O pins) - 64-pin VQFP (52 user I/O pins) - 100-pin TQFP (72 user I/O pins) Optimized for high-performance 3.3V systems - Low power operation - 5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V signals - 3.3V or 2.5V output capability - Advanced 0.35 micron feature size CMOS FastFLASH™ technology Advanced system features - In-system programmable - Superior pin-locking and routability with FastCONNECT II™ switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks - Individual output enable per output pin - Input hysteresis on all user and boundary-scan pin inputs - Bus-hold circuitry on all user pin inputs - Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles - 20 year data retention - ESD protection exceeding 2,000V Pin-compatible with 5V-core XC9572 device in the 44-pin PLCC package and the 100-pin TQFP package Preliminary Product Specification cations and computing systems. It is comprised of four 54V18 Function Blocks, providing 1,600 usable gates with propagation delays of 5 ns. See Figure 2 for architecture overview. Power Estimation Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XL device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power. For a general estimate of ICC, the following equation may be used: ICC (mA) = MCHP(0.5) + MCLP(0.3) + MC(0.0045 mA/MHz) f Where: MCHP = Macrocells in high-performance (default) mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) This calculation is based on typical operating conditions using a pattern of 16-bit up/down counters in each Function Block with no output loading. The actual ICC value varies with the design application and should be verified during normal system operation. Figure 1 shows the above estimation in a graphical form. 100 178 MHz 80 60 Typical ICC (mA) R gh Hi 40 L ow Po we ma nc e 104 MHz r 20 Description 0 The XC9572XL is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communi- Pe r rfo 100 50 150 Clock Frequency (MHz) 200 DS057_01_081500 Figure 1: Typical ICC vs. Frequency for XC9572XL © 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS057 (v1.1) August 28, 2000 Preliminary Product Specification www.xilinx.com 1-800-255-7778 1 R XC9572XL High Performance CPLD 3 JTAG Port 1 JTAG Controller In-System Programming Controller 54 18 I/O Function Block 1 Macrocells 1 to 18 I/O FastCONNECT II Switch Matrix I/O I/O I/O Blocks I/O I/O I/O 54 18 Function Block 2 Macrocells 1 to 18 54 18 Function Block 3 Macrocells 1 to 18 I/O 3 I/O/GCK 54 1 18 I/O/GSR I/O/GTS 2 Function Block 4 Macrocells 1 to 18 DS057_02_082800 Figure 2: XC9572XL Architecture Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. 2 www.xilinx.com 1-800-255-7778 DS057 (v1.1) August 28, 2000 Preliminary Product Specification R XC9572XL High Performance CPLD Absolute Maximum Ratings Symbol Description Value Units VCC Supply voltage relative to GND –0.5 to 4.0 V VIN GND(1) –0.5 to 5.5 V Input voltage relative to output(1) VTS Voltage applied to 3-state TSTG Storage temperature (ambient) TSOL TJ –0.5 to 5.5 V –65 to +150 oC Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 oC Junction temperature +150 oC Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operation Conditions Symbol VCCINT VCCIO Parameter Supply voltage for internal logic and input buffers Commercial TA = Industrial TA = 0oC –40oC to 70oC to +85oC Min Max Units 3.0 3.6 V 3.0 3.6 V Supply voltage for output drivers for 3.3V operation 3.0 3.6 V Supply voltage for output drivers for 2.5V operation 2.3 2.7 V VIL Low-level input voltage 0 0.80 V VIH High-level input voltage 2.0 5.5 V VO Output voltage 0 VCCIO V Quality and Reliability Characteristics Symbol Parameter Min Max Units 20 - Years TDR Data Retention NPE Program/Erase Cycles (Endurance) 10,000 - Cycles VESD Electrostatic Discharge (ESD) 2,000 - Volts DC Characteristic Over Recommended Operating Conditions Symbol Parameter Test Conditions Min Max Units Output high voltage for 3.3V outputs IOH = –4.0 mA 2.4 V Output high voltage for 2.5V outputs IOH = –500 µA 90% VCCIO V Output low voltage for 3.3V outputs IOL = 8.0 mA - 0.4 V Output low voltage for 2.5V outputs IOL = 500 µA - 0.4 V IIL Input leakage current VCC = Max VIN = GND or VCC - ±10 µA IIH I/O high-Z leakage current VCC = Max VIN = GND or VCC - ±10 µA CIN I/O capacitance VIN = GND f = 1.0 MHz - 10 pF ICC Operating supply current (low power mode, active) VI = GND, No load f = 1.0 MHz 20 (Typical) VOH VOL DS057 (v1.1) August 28, 2000 Preliminary Product Specification www.xilinx.com 1-800-255-7778 mA 3 R XC9572XL High Performance CPLD AC Characteristics XC9572XL-5 Symbol Parameter XC9572XL-7 XC9572XL-10 Min(1) Max(1) Min Max Min Max Units - 5.0 - 7.5 - 10.0 ns TPD I/O to output valid TSU I/O setup time before GCK 3.7 - 4.8 - 6.5 - ns TH I/O hold time after GCK 0.0 - 0.0 - 0.0 - ns GCK to output valid - 3.5 - 4.5 - 5.8 ns fSYSTEM Multiple FB internal operating frequency - 178.6 - 125.0 - 100.0 MHz TPSU I/O setup time before p-term clock input 1.7 - 1.6 - 2.1 - ns TPH I/O hold time after p-term clock input 2.0 - 3.2 - 4.4 - ns P-term clock output valid - 5.5 - 7.7 - 10.2 ns TOE GTS to output valid - 4.0 - 5.0 - 7.0 ns TOD GTS to output disable - 4.0 - 5.0 - 7.0 ns TPOE Product term OE to output enabled - 7.0 - 9.5 - 11.0 ns TPOD Product term OE to output disabled - 7.0 - 9.5 - 11.0 ns TAO GSR to output valid - 10.0 - 12.0 - 14.5 ns TPAO P-term S/R to output valid - 10.5 - 12.6 - 15.3 ns TWLH GCK pulse width (High or Low) 2.8 - 4.0 - 4.5 - ns TPLH P-term clock pulse width (High or Low) 5.0 - 6.5 - 7.0 - ns TCO TPCO Advance Preliminary Notes: 1. Please contact Xilinx for up-to-date information on advance specifications. VTEST R1 Output Type VCCIO VTEST R1 R2 CL 3.3V 3.3V 320 Ω 360 Ω 35 pF 2.5V 2.5V 250 Ω 660 Ω 35 pF Device Output R2 CL DS058_03_081500 Figure 3: AC Load Circuit 4 www.xilinx.com 1-800-255-7778 DS057 (v1.1) August 28, 2000 Preliminary Product Specification R XC9572XL High Performance CPLD Internal Timing Parameters XC9572XL-5 Symbol Parameter Min(1) XC9572XL-7 XC9572XL-10 Max(1) Min Max Min Max Units Buffer Delays TIN Input buffer delay - 1.5 - 2.3 - 3.5 ns TGCK GCK buffer delay - 1.1 - 1.5 - 1.8 ns TGSR GSR buffer delay - 2.0 - 3.1 - 4.5 ns TGTS GTS buffer delay - 4.0 - 5.0 - 7.0 ns TOUT Output buffer delay - 2.0 - 2.5 - 3.0 ns TEN Output buffer enable/disable - 0.0 - 0.0 - 0.0 ns - 1.6 - 2.4 - 2.7 ns delay Product Term Control Delays TPTCK Product term clock delay TPTSR Product term set/reset delay - 1.0 - 1.4 - 1.8 ns TPTTS Product term 3-state delay - 5.5 - 7.2 - 7.5 ns - 0.5 - 1.3 - 1.7 ns Internal Register and Combinatorial Delays TPDI Combinatorial logic propagation delay TSUI Register setup time 2.3 - 2.6 - 3.0 - ns THI Register hold time 1.4 - 2.2 - 3.5 - ns TECSU Register clock enable setup time 2.3 - 2.6 - 3.0 - ns TECHO Register clock enable hold time 1.4 - 2.2 - 3.5 - ns TCOI Register clock to output valid time - 0.4 - 0.5 - 1.0 ns TAOI Register async. S/R to output delay - 6.0 - 6.4 - 7.0 ns TRAI Register async. S/R recover before clock TLOGI Internal logic delay - 1.0 - 1.4 - 1.8 ns Internal low power logic delay - 5.0 - 6.4 - 7.3 ns - 1.9 - 3.5 - 4.2 ns Incremental product term allocator delay - 0.7 - 0.8 - 1.0 ns Slew-rate limited delay - 3.0 - 4.0 - 4.5 ns TLOGILP 5.0 7.5 10.0 ns Feedback Delays TF FastCONNECT II feedback delay Time Adders TPTA TSLEW Advance Preliminary Notes: 1. Please contact Xilinx for up-to-date information on advance specifications. DS057 (v1.1) August 28, 2000 Preliminary Product Specification www.xilinx.com 1-800-255-7778 5 R XC9572XL High Performance CPLD XC9572XL I/O Pins Function Block Macrocell 1 1 - - - - 16 1 2 1 39 D7 8 13 1 3 - - D4 12 1 4 - - - 1 5 2 40 D6 1 6 3 41 C7 10 15 198 3 6 - 1 7 - - - - 25 195 3 7 - 1 8 4 42 C6 11 17 192 3 8 13 7 43(1) B7(1) 15(1) 22(1) PC44 VQ44 CS48 Func -tion Block Macrocell 213 3 1 - - 210 3 2 11 5 18 207 3 3 - - 13 20 204 3 4 - 9 14 201 3 5 12 VQ64 BScan TQ100 Order PC44 VQ64 TQ100 BScan Order - - 41 105 B5 22 32 102 C4 31 49 99 - - 32 50 96 6 A4 24 35 93 - - 34 53 90 - - - 54 87 B4 25 37 84 VQ44 CS48 1 9 5(1) 189 3 9 14 8 A3 27 42 81 1 10 - - - 18 28 186 3 10 - - D3 39 60 78 1 11 6(1) 44(1) B6(1) 16(1) 23(1) 183 3 11 18 12 B2 33 52 75 1 12 - - - 23 33 180 3 12 - - - 40 61 72 1 13 - - - - 36 177 3 13 - - - - 63 69 1 14 7(1) 1(1) A7(1) 17(1) 27(1) 174 3 14 19 13 B1 35 55 66 1 15 8 2 A6 19 29 171 3 15 20 14 C2 36 56 63 1 16 - - - - 39 168 3 16 24 18 D2 42 64 60 1 17 9 3 C5 20 30 165 3 17 22 16 C3 38 58 57 1 18 - - - - 40 162 3 18 - - - - 59 54 2 1 - - - - 87 159 4 1 - - - - 65 51 2 2 35 29 F4 60 94 156 4 2 25 19 E1 43 67 48 2 3 - - - 58 91 153 4 3 - - - 46 71 45 2 4 - - - 59 93 150 4 4 - - - 47 72 42 2 5 36 30 G5 61 95 147 4 5 26 20 E2 44 68 39 2 6 37 31 F5 62 96 144 4 6 - - E4 49 76 36 2 7 - - - - 3(2) 141 4 7 - - - - 77 33 2 8 38 32 G6 63 97 138 4 8 27 21 F1 45 70 30 2 9 39(1) 33(1) G7(1) 64(1) 99(1) 135 4 9 - - - - 66 27 2 10 - - - 1 1 132 4 10 - - - 51 81 24 2 11 40(1) 34(1) F6(1) 2(1) 4(1) 129 4 11 28 22 G1 48 74 21 2 12 - - - 4 6 126 4 12 - - - 52 82 18 2 13 - - - - 8 123 4 13 - - - - 85 15 2 14 42(3) 36(3) E6(3) 5(3) 9(3) 120 4 14 29 23 F2 50 78 12 2 15 43 37 E7 6 11 117 4 15 33 27 E3 56 89 9 2 16 - - - - 10 114 4 16 - - - - 86 6 2 17 44 38 E5 7 12 111 4 17 34 28 G4 57 90 3 2 18 - - - - 92 108 4 18 - - - - 79 0 Notes: 1. Global control pin. 2. GTS1 for TQ100. 3. GTS1 for PC44, VQ44, CS48, and VQ64. 6 www.xilinx.com 1-800-255-7778 DS057 (v1.1) August 28, 2000 Preliminary Product Specification R XC9572XL High Performance CPLD XC9572XL Global, JTAG and Power Pins Pin Type PC44 VQ44 CS48 VQ64 TQ100 I/O/GCK1 5 43 B7 15 22 I/O/GCK2 6 44 B6 16 23 I/O/GCK3 7 1 A7 17 27 I/O/GTS1 42 36 E6 5 3 I/O/GTS2 40 34 F6 2 4 I/O/GSR 39 33 G7 64 99 TCK 17 11 A1 30 48 TDI 15 9 B3 28 45 TDO 30 24 G2 53 83 TMS 16 10 A2 29 47 VCCINT 3.3V 21, 41 15, 35 C1, F7 3, 37 5, 57, 98 VCCIO 2.5V/3.3V 32 26 G3 26, 55 26, 38, 51, 88 GND 10, 23, 31 4, 17, 25 A5, D1, F3 14, 21, 41, 54 21, 31, 44, 62, 69, 75, 84, 100 No Connects - - - - 2, 7, 19, 24, 34, 43, 46, 73, 80 DS057 (v1.1) August 28, 2000 Preliminary Product Specification www.xilinx.com 1-800-255-7778 7 R XC9572XL High Performance CPLD Ordering Information Example: XC9572XL -7 TQ 100 C Device Type Temperature Range Number of Pins Speed Grade Package Type Device Ordering Options Speed Package Temperature -10 10 ns pin-to-pin delay PC44 44-pin Plastic Lead Chip Carrier (PLCC) C = Commercial TA = 0°C to + 70°C -7 7.5 ns pin-to-pin delay VQ44 44-pin Quad Flat Pack (VQFP) I = Industrial TA = –40°C to + 85°C -5 5 ns pin-to-pin delay CS48 48-pin Chip Scale Package VQ64 64-pin Quad Flat Pack (VQFP) TQ100 100-pin Thin Quad Flat Pack (TQFP) Component Availability Pins Type Code XC9572XL 44 44 48 64 100 Plastic Plastic Plastic Plastic Plastic PLCC VQFP CSP VQFP TQFP PC44 VQ44 CS48 VQ64 TQ100 -10 C, I C, I - C, I C, I -7 C, I C, I C C, I C, I -5 (C) (C) - (C) (C) Notes: 1. C = Commercial (TA = 0oC to +70oC); I = Industrial (TA = –40oC to +85oC) 2. ( ) Parenthesis indicate future products. Please contact Xilinx for up-to-date information. Revision History The following table shows the revision history for this document. 8 Date Version Revision 09/28/98 1.0 Initial Xilinx release. 08/28/00 1.1 Added VQ44 package. www.xilinx.com 1-800-255-7778 DS057 (v1.1) August 28, 2000 Preliminary Product Specification