ACTEL MC-ACT

MC-ACT-VME2416
VME2416
February 25, 2003
Datasheet v1.3
MemecCore Product Line
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TM
Product Summary
Intended Use
•
Medical systems
•
Industrial controls: robotic, factory automation
Key Features
•
Flexible slave VME controller
•
Full interrupt controller (ROAK)
•
Control signals for external drivers and drivers on chip
•
Synchronous user side interface for registers, peripherals and memories
•
User definable waitstates
•
•
Synchronous, reliable design
Expandible to full set of VME features
•
Silicon proven design
Targeted Devices
•
SX-A Family
•
Axcelerator Family
•
ProASIC
PLUS
Family
General Description
The MC-ACT-VME2416 core is used as interface for the VME standard bus. One side contains all VME bus
signals and the other side all the user signals. With the defined address and address modifier, the user allows
any masters on the VME bus to access the IO, peripherals or memory placed on the user side.
The user has to describe two blocks which are connected to the “address decoding” and to the “user side”. The
“address decoding” is used to detect the access and to allow the transfer on the corresponding board. It allows
the user to built its own address decoding without changing the code of the MC-ACT-VME2416.
The MC-ACT-VME2416 core provides a full interrupt controller based on seven interrupt lines connected to the
bus. The system release the interrupt on the acknowledge (ROAK). The acknowledge is done on all boards
connected on the bus through a daisy-chain.
A complete VHDL test bench verifies every functions and addressing mode and interrupts. These testbenches
are built as a self testing regression-test suite.
February 25, 2003
Optimized for
1
VME2416
Memec Design
Core Deliverables
•
Netlist Version
o Netlist compatible with the Actel Designer place and route tool
•
RTL Version
o VHDL Source Code
o Test Bench
•
All
o
User Guide
Synthesis and Simulation Support
•
Synthesis: Synplicity
•
Simulation: ModelSim
•
Other tools supported upon request
Verification
•
Test Bench
System
CLK
RESET_N
Address decoding
VME_IACK_N
VME_IACKOUT_N
VME_IACKIN_N
VME_IRQ_N[6 :0]
USER_ADDR[23 :1]
USER_AM[5 :0]
USER_RW_N
USER_WR_DATA[15 :0]
USER_BE1
USER_BE2
USER_RD_DATA[15 :0]
USER_ACC_REQ
USER_ACC_RDY
USER_IREQ
USER_ILEV[2 :0]
USER_IVEC[15 :0]
USER_IACK
INT_USER_AM[5 :0]
INT_USER_ADDR[15 :1]
USER_ACC
User Address
Decode
Interrupt port
VMEbus signals
VME_ADDR[23:1]
VME_AM[5:0]
VME_DATA_IN[15:0]
VME_DATA_OUT[15:0]
VME_EXT_DRV_N
VME_EXT_DDIR
VME_INT_DRV_N
VME_DTACK_N
VME_AS_N
VME_DS0_N
VME_DS1_N
VME_LWORD_N
VME_WRITE_N
VME_BERR_N
User side signals
MC-ACT-VME2416
Figure 1: MC-ACT-VME2416 Pinout
February 25, 2003
Optimized for
2
VME2416
Memec Design
Functional Description
The falling edge of VME_AS (address strobe) will synchronize all the addresses (VME_ADDR and VME_AM)
allowing the controller to decode them in order to define if the present board is addressed or not. Since this
moment, all signals on the VME bus have to be stable and the controller will execute the command depending on
the control signals (VME_DS0_N, VME_DS1_N, VME_WRITE_N, VME_IACK_N). The VME master has to release
the VME_AS_N signal at the end of a transfer to execute a new command.
WRITE DATA TRANSFER
When the VME_WRITE_N defines a write data transfer, the controller will assign the address (VME_ADDR) on the
USER_ADDR bus, the address modifier (VME_AM) on the USER_AM bus and the data (VME_DATA) on the
USER_DATA bus. The signals VME_DS0_N and VME_DS1_N select the corresponding data location according
the following table (for this model of VME controller-MC-ACT-VME2416-, the signals VME_LWORD and
VME_ADDR01 are don’t care):
Data Locations Selected
VME_DS0_N
VME_DS1_N
VME_ADDR01
VME_LWORD_N
VME_DATA_IN(7:0)
low
high
X
X
VME_DATA_IN(15:8)
high
low
X
X
VME_DATA_IN(15:0)
low
low
X
X
To execute the transfer on the user part, the controller will active a request signal (USER_ACC_REQ) with valid
control signals. The data locations selected are enabled with the signals USER_BE1 (bits 7:0) and USER_BE2 (bits
15:8). The transfer will be ended with the acknowledge of the user part (USER_ACC_ACK).
Once the transfer executed, the controller will acknowledge the data transfer on the VME bus with the
VME_DTACK_N. When seeing this acknowledge, the master will release the VME_AS_N signal ending the actual
data transfer.
READ DATA TRANSFER
When the VME_WRITE_N defines a read data transfer, the controller will assign the address (VME_ADDR) on the
USER_ADDR bus and the address modifier (VME_AM) on the USER_AM bus. As the write data transfer, the
signals USER_BE1/2 are depending on the VME_DS0/1_N.
The controller will active a request signal (USER_ACC_REQ) until the acknowledge (USER_ACC_ACK) coming
from the user part. The read data have to be valid during this acknowledge.
Once ready, the data are transferred on the VME_DATA_OUT bus and acknowledged with the signal
VME_DTACK_N. When seeing this acknowledge, the master will release the VME_AS_N signal ending the actual
data transfer.
INTERRUPT
The interrupts on the VME bus are generated by the different modules connected on the bus and are acknowledged
through a daisy-chain interrupt line as shown on the figure below:
iackout_
n
MC-ACTVME
iack_n
VME
Interface
iackin_n
IO Board
(user part)
iackout_
n
iackin_n
iackout_
n
iack_n
iackin_n
MC-ACTVME
Interrupt
Handler
iack_n
Memory Board
(user part)
iack_n
February 25, 2003
Optimized for
3
VME2416
Memec Design
Between the user part and the VME controller, the transfer of interrupt information is based on the
request/acknowledge protocol.
When an interrupt occurs on the user part, it generates an interrupt request on the VME controller through the
signal USER_IREQ. Depending on the value defined by the user part on the vector USER_ILEV, the VME controller
activates an interrupt on the respective interrupt line VME_IRQ_N(x) (USER_ILEV = 1 -> VME_IRQ_N(1),
USER_ILEV = 7 -> VME_IRQ_N(7)). Interrupt level 7 has the highest priority and interrupt level 1 has the lowest.
Since there, the interrupt handler acknowledges the interrupt by asserting a low state on the signal VME_IACK_N.
This signal will be transmitted to all modules and as well in the first module of the daisy-chain. The modules which
didn’t generate an interrupt just assert the VME_IACKIN_N signal to the VME_IACKOUT_N. A module which
generated an interrupt will detect the acknowledge at the falling edge and compare the VME_ADDR(3:1) with the
interrupt level register (USER_ILEV) to determine if it has the priority (depending on the level) to execute the
interrupt or not. In case of not, it will assign the VME_IACKIN_N to VME_IACKOUT_N. In the other case (the
corresponding module has the priority), the high state is asserted to the VME_IACKOUT_N signal in order to break
the daisy-chain and avoid other modules taking the interrupt acknowledge. During the acknowledge, the module
transfers the interrupt vector register defined by the user (USER_IVEC) on the VME data bus (VME_DATA_OUT).
When the data are valid, the VME controller drives the VME_DTACK_N signal low, allowing the master and
interrupt handler executing next commands.
On the user part, the interrupt is acknowledged with the signal USER_IACK which clears the pending interrupt
request.
Device Requirements
Family
SX-A
PLUS
ProASIC
Axcelerator
Device
COMB
66 (4%)
n/a
65 (2%)
SX32A-STD
APA150-STD
AX500-STD
Utilization
SEQ
135 (13%)
n/a
135 (5%)
Performance
Total
201 (7%)
295 (5%)
200 (3%)
138 MHz
112 MHz
159 MHz
Table 1: Device Utilization and Performance
Verification and Compliance
Complete functional and timing simulation has been performed on the VME using ModelSim 5.5e. This core has
also been used successfully in customer designs.
February 25, 2003
Optimized for
4
VME2416
Memec Design
Signal Descriptions
The following signal descriptions define the IO signals.
Signal
Direction Description
CLK
Input
RESET_N
VME_ADDR[23:1]
Input
Input
VME_AM[5:0]
Input
VME_DATA_IN[15:0]
Input
VME_DATA_OUT[15:0]
Output
VME_EXT_DRV_N
Output
VME_INT_DRV_N
Output
VME_EXT_DDIR
Output
VME_LWORD_N
Input
VME_DTACK_N
Output
VME_AS_N
Input
VME_DS0_N
Input
VME_DS1_N
Input
VME_WRITE_N
Input
VME_BERR_N
Input
VME_IACK_N
Input
VME_IACKIN_N
Input
VME_IACKOUT_N
Output
VME_IRQ_N[6:0]
Output
INT_USER_ADDR[23:1]
Output
INT_USER_AM[5:0]
Output
USER_ACCESS
February 25, 2003
Input
Clock: System clock. This clock is provided by the user side interface which is
part of the 40MHz clock domain.
System reset: Asynchronous system reset, active low.
VME Address Bus: The smallest addressable unit is the byte location. Masters
use address lines to select the data which has to be accessed
VME Address Modifier Bus: Allow the master to pass additional binary
information to the slave during data transfer cycles.
VME Data Bus In: 16 write data lines are available. Depending on the control
signals, only one byte can be used for the transfer on the user part.
VME Data Bus Out: 16 read data lines. For each access, the 16 data bits are
read.
VME External Data Drive: Active low drive enable signal for external bidirectional
data bus drivers.
VME Internal Data Drive: Active low drive enable signal for internal bidirectional
data bus drivers.
VME External Data Direction: Direction control signal for internal bidirectional
data bus drivers. High indicates data to VME bus and low from VME bus.
VME Long Word: Active low signal indicating long word access. This signal is not
used in the MC-ACT-VME2416.
VME Data Acknowledge: This active low signal acknowledges the data transfer.
It has to be connected to an open collector driver.
VME Address Strobe: clocks with falling edge the internal synchronization
signals like VME_ADDR and VME_AM. It is also used as data signal for access
start detection.
VME Data Strobe 0: Active low signal used for the selected location part of the
data. Data strobe 0 is dedicated to the data[7:0].
VME Data Strobe 1: Active low signal used for the selected location part of the
data. Data strobe 1 is dedicated to the data[15:8].
VME Read/Write: Active low signal which is used by the master to indicate the
data direction.
VME Bus Error: Active low signal driven by other modules indicating that the data
transfer was unsuccessful.
VME Interrupt Acknowledge: When driven low, the VME_IACKIN_N causes the
IACK daisy-chain driver, located in slot 1, to propagate a falling edge down the
interrupt acknowledge daisy-chain.
VME Interrupt Acknowledge Input Daisy-Chain: This active low signal is used
as input of the module for the daisy-chain interrupt acknowledge.
VME Interrupt Acknowledge Output Daisy-Chain: This active low signal is used
as output of the module for the daisy-chain interrupt acknowledge.
VME Interrupt Request Lines: Interrupters request interrupts by driving an
interrupt request line low. VME_IRQ_N[7] has the highest priority. These signals
have to be connected to open collector drivers.
Registered VME Address Bus: Synchronized on the falling edge of VME_AS_N.
This bus is used to decode the address and to active an access signal on the user
part.
Registered VME Address Modifier Bus: Synchronized on the falling edge of
VME_AS_N. This bus is used to decode the address modifier and to active an
access signal on the user part.
User Access Signal: The user has 50 ns time to decode the address and
asserting the USER_ACCESS signal when addressed.
Optimized for
5
VME2416
Signal
Memec Design
Direction
USER_ACC_REQ
Output
USER_ACC_RDY
Input
USER_ADDR[23:1]
USER_AM[5:0]
USER_WR_DATA[15:0]
Output
Output
Output
USER_RD_DATA[15:0]
USER_RW_N
Input
Output
USER_BE1
USER_BE2
USER_IREQ
Output
Output
Input
USER_IACK
Output
USER_ILEV[2:0]
Input
USER_IVEC[15:0]
Input
Description
User Access Request: Active high signal which requests for an access on the
VME bus. Valid until USER_ACC_RDY acknowledges the request (or VME bus
error occurs).
User Side Acknowledgement Signal: Acknowledge the request of the access on
the VME bus of the user part.
User Address: Address used for the access on the user part.
User Address Modifier: Address modifier used for the access on the user part.
User Write Data: The MSB data [15:8] are valid while USER_BE2 is high and
LSB data [7:0] while USER_BE1 is high.
User Read Data: The read data has to be valid when USER_ACC_RDY is high.
User Read/Write Signal: A low signal indicates that the data are written in the
user part and a low signal, that the data are read.
User Byte 1 Enable: Active high signal enabling the low byte [7:0] of the data.
User Byte 2 Enable: Active high signal enabling the high byte [15:8] of the data.
User Interrupt request: This active high signal indicates that an interrupt is
pending on a VME interrupt will be generated. It will return to zero with
USER_IACK active.
User Interrupt Acknowledge: An active one event which indicates the end of a
valid interrupt acknowledge cycle.
User Interrupt Level: This bus indicates the level of priority of the pending
interrupt. It will generate the corresponding VME_IRQ.
User Interrupt Vector: The interrupt vector will be transmitted on the VME data
bus during the acknowledgement of the interrupt.
Table 2: VME Core Signal List
February 25, 2003
Optimized for
6
VME2416
Memec Design
Recommended Design Experience
For the source version, users should be familiar with HDL entry and Actel design flows. Users should be familiar
with Actel Libero v2.2 Integrated Design Environment (IDE) and preferably with Synplify and ModelSim.
Ordering Information
Part Number
MC-ACT-VME2416-NET
MC-ACT-VME2416-VHD
Description
Core Netlist
Core VHDL
Table 3: Core Part Numbers
The CORE is provided under license from Memec Design for use in Actel programmable logic devices. Please
contact Memec Design for pricing and more information.
Information furnished by Memec Design is believed to be accurate and reliable. Memec Design reserves the right to
change specifications detailed in this data sheet at any time without notice, in order to improve reliability, function or
design, and assumes no responsibility for any errors within this document. Memec Design does not make any
commitment to update this information.
Memec Design assumes no obligation to correct any errors contained herein or to advise any user of this text of any
correction, if such be made, nor does the Company assume responsibility for the functioning of undescribed
features or parameters. Memec Design will not assume any liability for the accuracy or correctness of any support
or assistance provided to a user.
Memec Design does not represent that products described herein are free from patent infringement or from any
other third-party right. No license is granted by implication or otherwise under any patent or patent rights of Memec
Design.
MemecCore products are not intended for use in life support appliances, devices, or systems. Use of a MemecCore
product in such application without the written consent of the appropriate Memec Design officer is prohibited.
All trademarks, registered trademarks, or service marks are property of their respective owners.
Datasheet Revision History
Version
Datasheet 1.0
Datasheet 1.1
Datasheet 1.2
Datasheet 1.3
February 25, 2003
Date
January 8, 2003
January 23, 2003
January 29, 2003
February 25, 2003
Description
Initial Release
Modification done in section core deliverables; Added logo to footer
Modification done in section device requirements
Modification done in section device requirements, new URL and address
inserted
Optimized for
7