Optimized for VME64 Slave Controller Description Features The VMEbus was first standardized in 1981 and is still in wide use. With the advances in integration technologies, custom integrated VME controllers open the door for smaller and cheaper systems. Inicore offers a wide range of different VME slave controllers. Each one optimized for a certain application. The difference lies mainly in the address and data bus width and the supported data modes. The VME slave controller shields all the complexity of the asynchronous VMEbus and provides an easy-to-use, synchronous parallel user side interface towards custom logic. A built-in interrupter handles all local interrupt requests and acknowledgments. INTCmod on-chip bus VM E Slave Controller • VME slave controller • Data modes: D8, D16, D32 • Address modes: A16, A24, D32 • Supports read, write, readmodify-write, D32-BLT and MBLT cycles • Configurable D8, D16 or D32 interrupter TIM ERmod VMEbus • ANSI/VITA 1-1994 compliant GPIOmod • Fully synchronous user side interface UARTmod Bus Bridge • User selectable wait-states User Decode • Synchronous design VMEchip Figure 1: Sample application The figure above illustrates a typical application where several peripheral functions together with the VME slave core as well as a bus bridge are integrated into one FPGA. Applications • Industrial control • Military Supported modes • Aerospace • Data modes: D8, D16, D32 • Address modes: A16, A24, A32 • Access modes: Read, write, read-modify-write, D32-BLT, MBLT • Interrupter: D8, D16, D32, RORA, ROAK • Telecom • Medical Sample Utilization and Performance Table Optimized for Actel Devices Family Device - (speed grade) Utilization s-mod ProASIC PLUS APA600 Axcelerator AX500-3 225 SX72A-3 225 SXA RTSX RTSX72S-1 MIL 223 c-mod Performance Total [MHz] 3% 43 354 7% 101 355 10% 74 334 10% 47 Tiles 729 RAM INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 Tel: 510 445 1529 Fax: 510 656 0995 www.inicore.com Page 1/2 About Inicore U s e r S id e B u s a d dr _ in [ 3 1 :1 ] a d dr _ o ut [ 3 1 :1 a d dr _ in t _ d r v _ addr_ drv _ n a d d r _ d ir a m [ 5 :0 ] da t a _ in [ 3 1 :0 ] da t a _ o ut [ 3 1 :0 da t a _ in t _ d r v _ da t a _ drv _ n d a t a _ d ir ds0 _ n ds1 _ n lw o r d _ i n _ n lw o r d _ o u t _ n a s_ n w r it e _ n dt ac k _ n be rr_ n ia c k _ n ia c k _ i n _ n ia c k _ o u t _ n ir q _ n [ 6 :0 ] ] n ] n use r _ use r _ use r _ use r _ use r _ use r _ use r _ use r _ a d d r [ 3 1 :2 ] a m [ 5 :0 ] acc_ req acc_ rdy da t a _ r d [ 3 1 :0 ] da t a _ w r [ 3 1 :0 ] rwn b y t e _ v a li d [ 3 : 0 ] In t e rru p t s e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ use r _ use r _ use r _ use r _ ia c k ir e q il e v [ 2 : 0 ] iv e c [ 3 1 :0 ] Decode m m m m m m m m m m m m m m m m m m m m m m m VM E B u s v v v v v v v v v v v v v v v v v v v v v v v in t _ u s e r _ a m [ 5 :0 ] in t _ u s e r _ a d d r [ 3 1 : 1 ] use r _ a c c e ss_ e bl u s e r _ a c c e s s _ e b l _ m b lt Figure 2: Symbol Interfaces Pin Name Type Description Global Signals clk in System clock reset_n in Asynchronous system reset, active low VME Bus vme_addr_in[31:1] in Address bus input vme_addr_out[31:1] out Address bus output vme_addr_int_drv_n out Internal i/o driver enable Pin Name Type Description vme_iack_in_n in Interrupt acknowledge chain in vme_iack_out_n out Interrupt acknowledge chain out vme_irq_n[6:0] out Interrupt request user_addr[31:2] out Address bus user_am[5:0] out Address modifier code user_acc_req out Data access request User Side Bus vme_addr_drv_n out External address bus driver enable user_acc_rdy in vme_addr_dir out External address bus driver direction Data access request ready user_data_rd[31:0] in Data read bus vme_am[5:0] in Address modifier code user_data_wr[31:0] out Data write bus vme_data_in[31:0] in Data bus input user_rwn out vme_data_out [31:0] out Data bus output Data read or write access vme_data_int_drv_n out Internal i/o driver enable user_byte_valid [3:0] out Data byte valid vme_data_drv_n out External data bus driver enable User Decode vme_data_dir out External data bus driver direction vme_ds0_n in Data strobe 0 vme_ds1_n in Data strobe 1 vme_lword_in_n in Long word indicator, in vme_lword_out_n out Long word indicator, out vme_as_n in Address strobe vme_write_n in Read write not indicator vme_dtack_n out Data acknowledge vme_berr_n in Bus error vme_iack_n in Interrupt acknowledge Easy-to-use IP Cores System-on-Chip Solutions Consulting Services ASIC to FPGA Migration Obsolete ASIC Replacements r e se t _ n c lk _ sy s V M E S la v e FPGA and ASIC Design Inicore is an experienced system design house providing FPGA / ASIC and SoC design services. The company's expertise in architecture, intellectual property, methodology and tool handling provides a complete design environment that helps customers shorten their design cycle and speed time to market. Our offering covers feasibility study, concept analysis, architecture definition, code generation and implementation. When ready, we deliver you a FPGA or take your design to an ASIC provider, whatever is more suitable for your unique solution. Deliverables The core is available as Actel optimized netlist or as RTL version. Actel Optimized Netlist: int_user_addr[31:1] out Address bus int_user_am[5:0] out Address modifier code user_access_ebl in Valid user access user_access_ebl_ mblt in Valid user access mblt mode Interrupt user_iack out Interrupt acknowledge user_ireq in Interrupt request user_ivec[31:0] in Interrupt vector user_ilevel[2:0] in Interrupt request level • Netlist for target FPGA, EDIF, Verilog and VHDL format • User Guide RTL Source Code: • VHDL or Verilog source code • Funtional verification testbench • Synthesis script • Timing constraints • User guide © 2003, Inicore Inc, All rights reserved. All brands or product names mentioned are the property of their respective holders. 51415.71.02 Sept/2003 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 Tel: 510 445 1529 Fax: 510 656 0995 www.inicore.com Page 2/2