ASAHI KASEI [AK9844A] AK9844A 4Kbit EEPROM with 4ch 8bit D/A Converter General Description The AK9844A includes 4 channel, 8-bit D/A converters with on-chip output buffer amps and it is capable to store the input digital data of each D/A converter by on-chip non-volatile CMOS EEPROM. The AK9844A is optimally designed for various circuit adjustments for consumer and industrial equipments and it is ideally suited for replacing mechanical trimmers. Features EEPROM section ・4 word x 8-bit organization (Dedicated for DAC data) ・256 word x 16-bit organization (General purpose memory) ・Serial data interface ・Sequential register read ・Automatic write cycle ・100K write cycles ・10 year data retention D/A section ・4 channels ・Resolution ・Differential Non-Linearity ・Linearity Error ・Output Voltage Range : 8-bits : ±1.0 LSB : ±1.5 LSB : GND to VCC AUTO READ Function Power down mode SK PROTECT DI DO CS VREF1 Control Logic Latch Decoder Instruction Register Data Register 8 8bit Latch 8 8bit D/A -+ AO0 8bit Latch 8 8bit D/A -+ AO1 8bit Latch 8 8bit D/A -+ AO2 8bit Latch 8 8bit D/A -+ AO3 8 VCC GND EEPROM 4128bit 256 x 16bit + 4 x 8bit PD VREF2 Block Diagram DAD05E-00 2005/03 - 1 - ASAHI KASEI [AK9844A] Ordering Guide AK9844AV -40°C to +85°C 16-pin TSSOP Pin Layout AK9844AV GND PROTECT PD VCC NC VREF1 AO0 AO1 1 2 3 4 5 6 7 8 DI DO SK CS NC VREF2 AO3 AO2 16 15 14 13 12 11 10 9 16pin TSSOP Pin Description No. 1 Pin Name GND I/O - 2 PROTECT I Protect Pin "L" : Programming to the D/A Section of EEPROM is disabled. "H" : Normal operation 3 PD I Power-down Pin "L" : Power down mode "H" : Normal mode 4 VCC - Power Supply 6 VREF1 I Voltage Reference Input1 The analog output ranges of the AO0 and the AO1 are set by the VREF1 pin. 7 8 9 10 AO0 AO1 AO2 AO3 O Analog Output Pins (8-bit D/A outputs) 11 VREF2 I Voltage Reference Input1 The analog output ranges of the AO2 and the AO3 are set by the VREF2 pin. 13 CS I Chip Select Pin (Schmitt-trigger input) 14 SK I Serial Clock Pin (Schmitt-trigger input) 15 DO O Serial Data Output Pin 16 DI I Serial Data Input Pin - Not Connected 5, 12 NC Function Ground Pin, 0V DAD05E-00 2005/03 - 2 - ASAHI KASEI [AK9844A] Functional Description The AK9844A includes the EEPROM section and the D/A converter section which consists of 4 channel, 8bit D/A converters with output buffer amps. The EEPROM section is divided into memory block and DAC register block. The capacity of the memory block is 4096bits which are organized into 256 registers of 16bits each. The DAC digital input data for D/A converters are stored in the DAC register block which is organized into 4 registers of 8bits each. The address for the memory block is "000000000" to "011111111". The address for the DAC register is "100000000" to "100000011". The configuration of the EEPROM section is showed on figure.1. The AK9844A can connect to the serial communication port of popular one chip microcontrollers directly (3 line negative clock synchronous interface). At write operation, the AK9844A takes in the write data from the DI pin to a register synchronously with rising edge of the SK pin. At read operation, the AK9844A takes out the read data from a register to the DO pin synchronously with falling edge of the SK pin. The AK9844A has 6 instructions such as READ, WRITE, WREN, WRDS, PDEN and PDDS. The each instruction is organized by op-code block(8bits), address block(8bits), and data(8bits x 2). The output of DAC is set by storing the DAC digital input data in the DAC register block. The DO pin is high impedance except that the DO pin outputs the read data and the status signal. 000000000 $000 Memory Block 011111111 100000000 100000011 DAC Register Block $0FF $100 $103 100000000 Digital input data for DAC (A00) $100 100000001 Digital input data for DAC (A01) $101 100000010 Digital input data for DAC (A02) $102 100000011 Digital input data for DAC (A03) $103 Figure 1. Configuration of the EEPROM section DAD05E-00 2005/03 - 3 - ASAHI KASEI [AK9844A] Data Protection To protect against accidental data disturb, the AK9844A has programming enable state and programming disable state. In programming disable state, the programming operation is not executed. When VCC is applied to the AK9844A, the AK9844A is powered up in the programming disable mode. The programming instruction should be preceded by the WREN instruction. Once the WREN instruction is executed, the programming state remains enabled until the WRDS instruction is executed or VCC is removed from the device. Execution of the READ instruction is independent of both WREN and WRDS instructions. The AK9844A also can prohibit to program into the DAC register block by the control of the PROTECT pin. When the PROTECT pin is "L", the programming into the DAC register block is not executed. PROTECT pin PROTECT="H" PROTECT="L" Programming State Enable Disable Enable Disable Memory Block ○ × ○ × DAC Register Block ○ × × × ○: Programming into the block is executed. ×: Programming into the block is not executed. Table 1. Relation between the programming operation and the PROTECT pin DAD05E-00 2005/03 - 4 - ASAHI KASEI [AK9844A] Output of D/A converter The AK9844A includes 4 channel, 8bit D/A converter. The output voltage ranges for AO0 and AO1 are set by the VREF1 pin and the output voltage ranges for AO2 and AO3 are set by the VREF2 pin. The output voltage can be set by the READ or WRITE instruction. When the DAC register block is specified in the WRITE instruction, the output voltage for the specified D/A converter is set. When the WRITE instruction is executed in case that the PROTECT pin is "H" and the programming state is enabled, the output voltage for the specified D/A converter is set and the specified address in the DAC register block in EEPROM is written with the data specified in the instruction. When the WRITE instruction is executed in case that the PROTECT pin is "H" and the programming state is disabled, the output voltage for the specified D/A converter is set and the specified address in the DAC register block in EEPROM is not written with the data specified in the instruction. When the WRITE instruction is executed in case that the PROTECT pin is "L", the output voltage for the specified D/A converter is not set and the specified address in the DAC register block in EEPROM is not written with the data specified in the instruction. The relation between the WRITE instruction and the DAC register block is showed on the Table 2. When the DAC register block is specified in the READ instruction, the output voltage for the specified D/A converter is set by the data which is stored in the DAC register block in EEPROM, and the DO pin outputs the data in the specified address. Execution of the READ instruction is independent of the PROTECT pin and the programming state. PROTECT pin Programming State Enable "H" Disable DAC register block (EEPROM section) Output of DAC (D/A Converter section) The specified address in the The output voltage for the DAC register block is written with the data specified in the specified D/A converter is set by the data specified in the instruction. instruction. The data in the DAC register section does not change. Enable The output of the DAC does not change. "L" Disable Table 2. Relation between the WRITE instruction and the DAC register block ○ AUTO READ Function When VCC is applied to the AK9844A, the data on EEPROM are read out and loaded at a time to each corresponding D/A (4 channels total) automatically, starting from AO0 to AO3 in ascending order. Then each D/A analog output is settled to pre-determined value. If the CS pin goes to "H" and then goes to "L" after "power-up" with the PROTECT pin and the CS pin left "L", AUTO READ cycle is initiated. After the CS pin goes to "L", 4 channel D/A outputs are settled to pre-determined value within 2ms. In AUTO READ cycle, the SK pin and the DI pin become "don't care" and the serial data do not output. If the WREN instruction is executed after AUTO READ cycle is completed, programming into the memory block on the internal EEPROM is enabled. DAD05E-00 2005/03 - 5 - ASAHI KASEI [AK9844A] Instruction and Data Format The instructions consist of op-code(8bits), address(8bits) and data(8bits x 2). the instruction and data set at WRITE execution. First MSB The followings are Last LSB 1 0 1 0 0 1 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D2 D1 D0 Op-code Address Function A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Memory Block 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 Data for A02 1 0 0 0 0 0 0 1 1 Data for A03 Data for A00 Data for A01 DAC Register Block Data D/A Output Voltage D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 X X X X X X X X ≒ ( VREF / 256 ) x1 0 0 0 0 0 0 0 1 X X X X X X X X ≒ ( VREF / 256 ) x2 1 1 1 1 1 1 1 0 X X X X X X X X ≒ ( VREF / 256 ) x255 1 1 1 1 1 1 1 1 X X X X X X X X ≒ DAD05E-00 VREF 2005/03 - 6 - ASAHI KASEI [AK9844A] Power Down Function There are the power down mode and the normal mode in AK9844A. When the AK9844A is in power down mode, the outputs of D/A are "High impedance" and the DAC section is in the standby mode and the power consumption of the AK9844A is decreased. The power down mode of AK9844A can be determined by the control of the PD pin or the PDEN/PDDS instructions. When the PD pin is low level, the AK9844A is in power down mode. When the PD pin is high level, the state of the AK9844A can be determined by PDEN/PDDS instructions. When the PD pin is High level and the PDEN instruction is executed, the AK9844A becomes the power down mode. Once the AK9844A becomes the power down mode, the AK9844A is in the power down mode until the PDDS instruction is executed. When the PDDS instruction is executed, the AK9844A becomes the normal mode. If the CS pin is High level in the power down mode, the EEPROM section also becomes the standby mode and the AK9844A becomes the lower power-down mode. The relation between the PD pin and the PDEN/PDDS instructions is showed on Table 3. The relation between the power down mode and the DAC/EEPROM section is showed on Table 4. The state at the time AK9844A is powered up is showed on Table 5. PD pin Low level High level instruction PDEN PDDS PDEN PDDS mode power down mode power down mode normal mode Table 3. Relation between the PD pin and the PDEN/PDDS instructions State normal mode power down mode1 power down mode2 CS pin="L" CS pin="H" DAC section normal mode standby mode standby mode EEPROM section normal mode normal mode standby mode Table 4. Relation between the power down mode and the DAC/EEPROM section Condition at the time AK9844A is powered on CS pin="L" PD pin="L" CS pin="H" PD pin="H" State power down mode1 power down mode2 normal mode Table 5. State at the time AK9844A is powered up Precautions for use 1) Output voltage of D/A converter at the time the AK9844A is powered up At the time the AK9844A is powered up, the D/A converters output "VREF/2" until the instruction or AUTO READ is executed. 2) Power Supply Decoupling On the boards, decoupling capacitors(0.1µF) between power supply pins(VCC,VREF1,VREF2) and GND should be located as near as possible to the part. DAD05E-00 2005/03 - 7 - ASAHI KASEI [AK9844A] Instruction Set The AK9844A has 6 instructions such as READ, WRITE, WREN, WRDS, PDEN, PDDS. Each instruction consists of Op-code, address and data. The instruction set is showed on Table 6. When the instructions are executed consecutively, the CS pin should be brought to high level for a minimum of 250ns(tCS) between consecutive instruction cycle. Instruction Op-code Address Data READ 1010100 WRITE Comments A8 A7 A6 A5 A4 A3 A2 A1 A0 D15-D0 Read register 1010010 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15-D0 Write register WREN 1010001 1 X X X X X X X X X Write enable WRDS 1010000 0 X X X X X X X X X Write disable PDEN 1010110 0 X X X X X X X X X Power down enable PDDS 1010011 0 X X X X X X X X X Power down disable X: Don't care Table 6. Instruction set WRITE The WRITE instruction is followed by 16 bits of data to be written into the specified address. After the 32nd rising edge of SK to read DO in, the AK9844A will be put into the automatic write time-out period. During the automatic write time-out period (Busy status), the CS pin need not be high level. The DO pin indicates the Ready/Busy status of the EEPROM in AK9844A. After the 32nd rising edge of SK to read DO in, the AK9844A will be put into the automatic write time-out period. When the automatic write time-out period start, the DO pin outputs the Ready/Busy status. When the DO pin outputs low level, the AK9844A is in the automatic write time-out and the next instruction can not be accepted. When the DO pin outputs high level, the automatic write time-out period has ended and the AK9844A is ready for a next instruction. When the CS pin is changed to high level after confirmation of Ready/Busy signal on the DO pin, the DO pin becomes "Hi-Z". The Ready/Busy signal can be confirmed until the initial 1 bit of the next instruction inputs from the execution of the WRITE instruction. CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 31 32 1 0 1 0 0 1 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D1 D0 SK DI DO Hi-Z BUSY Status output (READY), if previous instruction is WRITE. READY tE/W WRITE instruction DAD05E-00 2005/03 - 8 - ASAHI KASEI [AK9844A] READ The read instruction is the only instruction which outputs serial data on the DO pin. After a read instruction is received, the instruction and address are decoded, followed by data transfer from the memory register into a 16 bit serial-out shift register. When the 17th falling edge of SK is received, the DO pin will come out of high impedance state and shift out the data from D15 first in descending order which is located at the address specified in the instruction. ○ Sequential register read The data in the next address can be read sequentially to provide clock. The memory automatically cycles to the next register after each 16 data bits are clocked out. The sequential register read function is effective for address: A7~A0. When the highest address is reached ($0FF/$103), the address counter rolls over to address $000/$100 allowing the read cycle to be continued indefinitely. CS 1 2 3 4 5 6 7 8 1 0 1 0 1 0 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 31 32 33 34 35 9 10 11 12 13 14 15 16 17 18 19 SK DI Hi-Z DO D15 D14 D13 Status output (READY), if previous instruction is WRITE. D1 D0 D15 D14 D13 1st Data Hi-Z 2nd Data READ instruction WREN / WRDS When VCC is applied to the part, it powers up in the programming disable(WRDS) state. Programming must be preceded by a programming enable(WREN) instruction. Programming remains enabled until a programming disable(WRDS) instruction is executed or VCC is removed from the part. The programming disable instruction is provided to protect against accidental data disturb. Execution of a read instruction is not affected by both WREN and WRDS instruction. CS 1 2 3 4 5 6 1 0 1 0 0 0 7 8 9 10 11 12 13 14 15 16 17 SK DI X X X WREN=11 WRDS=00 X X X X X Hi-Z DO Status output (READY), if previous instruction is WRITE. WREN / WRDS instruction DAD05E-00 2005/03 - 9 - ASAHI KASEI [AK9844A] PDEN / PDDS The AK9844A has the power-down mode and the normal mode. When the PDEN instruction is executed while the PD pin is high level, the AK9844A becomes the power-down mode. The AK9844A is in the power-down mode until PDDS instruction is executed. After the PDDS instruction is executed, the AK9844A changed to normal mode from power-down mode. In case that the PD pin is low level, the PDEN/PDDS instructions are invalid and are not executed. CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 0 1 0 1 1 0 0 X SK DI X X X X X X X Hi-Z DO Status output (READY), if previous instruction is WRITE. PDEN instruction CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 0 1 0 0 1 1 0 X SK DI DO X X X X X X X Hi-Z Status output (READY), if previous instruction is WRITE. PDDS instruction DAD05E-00 2005/03 - 10 - ASAHI KASEI [AK9844A] Absolute Maximum Ratings Parameter Power Supply Input Voltage Ambient Temperature Storage Temperature Symbol VCC VIO Ta Tst Condition Relative to GND Relative to GND Min -0.6 -0.6 -40 -65 Max +7.0 VCC+0.6 +85 +150 Unit V V °C °C Recommended Operating Condition Parameter Power Supply Analog Output Load Capacitance Symbol VCC1 VCC2 AOC Condition DAC operation EEPROM operation DAD05E-00 Min 2.7 1.8 Typ Max 5.5 5.5 100 Unit V V pF 2005/03 - 11 - ASAHI KASEI [AK9844A] Electrical Characteristics D.C. ELECTRICAL CHARACTERISTICS ( 1.8V ≤ VCC ≤ 5.5V, GND=0V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified ) Parameter Power Consumption (Note1, Note2) Symbol Condition IDD1 Max. Unit Normal mode WRITE, 1/tSKP=2MHz 6.5 mA IDD2 Normal mode READ, 1/tSKP=2MHz 3.3 mA IDD3 Power down mode1 READ, 1/tSKP=2MHz 0.75 mA IDD4 Power down mode2 0.8 µA Input High Voltage1 CS, SK, PROTECT pin VIH1 Input High Voltage2 PD, DI pin VIH2 VIH3 Input Low Voltage1 CS, SK, PROTECT pin VIL1 Input Low Voltage2 PD, DI pin VIL2 Min. Typ. 0.8xVCC V 2.2V ≤ VCC ≤ 5.5V 0.7xVCC V 1.8V ≤ VCC < 2.2V 0.8xVCC V 0.2xVCC V 2.2V ≤ VCC ≤ 5.5V 0.3xVCC V VIL3 1.8V ≤ VCC < 2.2V 0.2xVCC V Output High Voltage VOH IOH=-50µA Output Low Voltage VOL1 2.2V ≤ VCC ≤ 5.5V IOL=1.0mA 0.4 V VOL2 1.8V ≤ VCC < 2.2V IOL=0.1mA 0.4 V Input Leakage ILI VIN=VCC ±1.0 µA 3 State Leakage Current IOZ CS="H" ±1.0 µA VCC-0.3 V Note1 : VCC=5.5V, VIN=VCC/GND, DO=OPEN Note2 : Please refer to "Power Down Function" regarding power down mode. DAD05E-00 2005/03 - 12 - ASAHI KASEI [AK9844A] A.C. ELECTRICAL CHARACTERISTICS 1) EEPROM section ( 1.8V ≤ VCC ≤ 5.5V, GND=0V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified ) Parameter Symbol Condition Min. Typ. Max. Unit SK Cycle Time tSKP1 500 ns 2.5V ≤ VCC ≤ 5.5V SK Pulse Width SK High Pulse Width (Note3) tSKP2 1.8V ≤ VCC < 2.5V 1.5 µs tSKW1 2.5V ≤ VCC ≤ 5.5V 250 ns tSKW2 1.8V ≤ VCC < 2.5V 750 ns tSKH1 4.0V ≤ VCC ≤ 5.5V 250 ns tSKH2 2.5V ≤ VCC < 4.0V 500 ns tSKH3 1.8V ≤ VCC < 2.5V 750 ns 100 ns 100 ns 1000 ns 100 ns CS Setup Time tCSS CS Hold Time tCSH1 READ, WREN, WRDS, PDEN, PDDS tCSH2 WRITE (Note4) SK Setup Time tSKS Data Setup Time tDIS1 4.0V ≤ VCC ≤ 5.5V 100 ns tDIS2 2.5V ≤ VCC < 4.0V 150 ns tDIS3 1.8V ≤ VCC < 2.5V 200 ns tDIH1 4.0V ≤ VCC ≤ 5.5V 100 ns tDIH2 2.5V ≤ VCC < 4.0V 150 ns tDIH3 1.8V ≤ VCC < 2.5V 200 ns tPD1 4.0V ≤ VCC ≤ 5.5V 150 ns tPD2 2.5V ≤ VCC < 4.0V 250 ns tPD3 2.2V ≤ VCC < 2.5V 300 ns (Note5) Data Output Delay (RDY/BUSY) (Note5) Selftimed Programming Time tPD4 1.8V ≤ VCC < 2.2V 500 ns 1000 ns Write Recovery Time tRC 100 ns Min CS High Time tCS 250 ns DO High-Z Time tOZ Data Hold Time Data Output Delay (READ) tPD tE/W1 2.5V ≤ VCC ≤ 5.5V 7 ms tE/W2 1.8V ≤ VCC < 2.5V 10 ms 500 ns Note3 : tSKH is the high pulse width of 16th SK pulse in READ operation. When the data in the next address are read sequentially by continuing to provide clock, tSKH are applied to the high pulse width of 32nd and 48th (multiple of 16) SK pulse in READ operation. Note4 : In case that the data of the DAC section is not changed and the output of the DAC is changed, tCSH is min. 1µs. In case of the other WRITE instruction, tCSH is min. 100ns. Note5 : CL=100pF DAD05E-00 2005/03 - 13 - ASAHI KASEI [AK9844A] 2) DAC section ( 2.7V ≤ VCC ≤ 5.5V, GND=0V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified ) Parameter D/A Reference Voltage A0, A1 A2, A3 D/A Reference Current Resolution Differential Non-Linearity Integral Non-Linearity (Note7) Error for Input data "00" (Note6) Error for Input data "FF" (Note6) Buffer-AMP Output Voltage Range(1) 3.6V ≤ VCC ≤ 5.5V (Note8) Buffer-AMP Output Voltage Range(2) 2.7V ≤ VCC < 3.6V Setup Time in AUTO READ D/A Settling Time (CL=100pF) Symbol VREF1 VREF2 IREF DNL NL EZERO Condition Min. Typ. 2.7 2.7 VREF=5.0V Monotonicity VCC=VREF=5.0V 1LSB=VREF/256 IAO=0.0µA CL=100pF 200 -1 -1.5 0 0 EFULL Max. Unit VCC VCC 400 8 +1 +1.5 V V µA bit LSB LSB +0.1 V +0.1 V VAO1 |IAO| = 0µA 0.1 VCC-0.1 V VAO2 |IAO| ≤ 200µA 0.2 VCC-0.2 V VAO3 |IAO| ≤ 1mA 0.3 VCC-0.3 V VAO4 |IAO| = 0µA 0.1 VCC-0.1 V VAO5 |IAO| ≤ 500µA 0.3 VCC-0.3 V tARS tLDD1 tLDD2 µs 500 3.6V ≤ VCC ≤ 5.5V 2.7V ≤ VCC < 3.6V 100 200 400 µs µs Note6 : Please refer to the Figure 2. Note7 : Integral Non-Linearity is the error between the actual line and the ideal line. The ideal line exhibits a perfect linear DAC output characteristics between the input digital data "00" and the input digital data "FF". Note8 : VCC=VREF * Please refer to "Instruction and Data Format" regarding the relation between input digital data and DAC output voltage. DAC Output Voltage 5.0V VCC=VREF=5V CL=100pF 5.0V EFULL EZERO 00 FF 00 FF Input digital data Figure 2. DAC output characteristics (IAO=0.0µA) DAD05E-00 2005/03 - 14 - ASAHI KASEI [AK9844A] Timing Waveform tCS tCSS CS tSKP tSKS tSKW tSKW SK tDIS DI 1 tDIH 0 1 tRC Hi-Z DO Input Waveform CS tSKH SK DI tCSH 16 A0 tPD DO D15 D2 D1 tOZ D0 tLDD D/A Waveform in READ instruction DAD05E-00 2005/03 - 15 - ASAHI KASEI [AK9844A] CS tCSH SK DI D2 D1 D0 tLDD D/A Programming Waveform in WRITE instruction CS SK DI D0 tPD tE/W DO tOZ BUSY READY tLDD D/A Status Output (Note) In case that the data of the DAC section is not changed and the output of the DAC is changed, Ready/Busy signal does not output on DO pin. VCC tARS min. 2ms CS PROTECT AO0 (D/A OUT) : AO3 (D/A OUT) Waveform in AUTO READ DAD05E-00 2005/03 - 16 - IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. 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