CTLDM7181-M832D SURFACE MOUNT N-CHANNEL AND P-CHANNEL ENHANCEMENT-MODE COMPLEMENTARY SILICON MOSFETS w w w. c e n t r a l s e m i . c o m DESCRIPTION: The CENTRAL SEMICONDUCTOR CTLDM7181-M832D is a Dual complementary N-Channel and P-Channel Enhancement-mode MOSFET, designed for high speed pulsed amplifier and driver applications. These MOSFETs offer Low rDS(ON) and Low Threshold Voltages. MARKING CODE: CFK • Device is Halogen Free by design TLM832D CASE FEATURES: APPLICATIONS: • Switching Circuits • DC - DC Converters • Battery powered portable devices • • • • MAXIMUM RATINGS: (TA=25°C) Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (Steady State) Continuous Drain Current, t<5.0s Continuous Source Current (Body Diode) Maximum Pulsed Drain Current, tp=10μs Maximum Pulsed Source Current, tp=10μs Power Dissipation (Note 1) Operating and Storage Junction Temperature Thermal Resistance (Note 1) ELECTRICAL CHARACTERISTICS: (TA=25°C) SYMBOL TEST CONDITIONS IGSSF, IGSSR VGS=8.0V, VDS=0 IDSS VDS=20V, VGS=0 BVDSS VGS=0, ID=250μA VGS(th) VDS=10V, ID=1.0mA VGS(th) VDS=VGS, ID=250μA VSD VGS=0, IS=1.0A VSD VGS=0, IS=360mA rDS(ON) VGS=4.5V, ID=0.5A rDS(ON) VGS=4.5V, ID=0.95A rDS(ON) VGS=2.5V, ID=0.5A rDS(ON) VGS=4.5V, ID=0.77A rDS(ON) VGS=1.5V, ID=0.1A rDS(ON) VGS=2.5V, ID=0.67A rDS(ON) VGS=1.8V, ID=0.2A Qg(tot) VDS=10V, VGS=4.5V, ID=1.0A Qgs VDS=10V, VGS=4.5V, ID=1.0A Qgd VDS=10V, VGS=4.5V, ID=1.0A Dual complementary MOSFETs Low rDS(ON) High current Logic level compatibility SYMBOL VDS VGS ID ID IS IDM ISM PD TJ, Tstg ΘJA N-CH (Q1) P-CH (Q2) 20 20 8.0 8.0 1.0 0.86 0.95 0.36 4.0 4.0 4.0 1.65 -65 to +150 76 N-CH (Q1) MIN TYP MAX 10 10 20 0.5 1.2 1.1 .075 0.10 0.10 0.14 0.17 0.25 2.4 0.25 0.65 - Notes: (1) FR-4 Epoxy PCB with copper mounting pad area of 54mm2. UNITS V V A A A A A W °C °C/W P-CH (Q2) MIN TYP MAX .001 .05 .005 0.5 20 24 0.45 0.76 1.0 0.9 .085 0.15 .085 0.142 0.13 0.20 0.19 0.24 3.56 0.36 1.52 - UNITS μA μA V V V V V Ω Ω Ω Ω Ω Ω Ω nC nC nC R2 (2-August 2011) CTLDM7181-M832D SURFACE MOUNT N-CHANNEL AND P-CHANNEL ENHANCEMENT-MODE COMPLEMENTARY SILICON MOSFETS ELECTRICAL CHARACTERISTICS - Continued: SYMBOL TEST CONDITIONS gFS VDS=10V, ID=0.5A gFS VDS=10V, ID=810mA Crss VDS=10V, VGS=0, f=1.0MHz Crss VDS=16V, VGS=0, f=1.0MHz Ciss VDS=10V, VGS=0, f=1.0MHz Ciss VDS=16V, VGS=0, f=1.0MHz Coss VDS=10V, VGS=0, f=1.0MHz Coss VDS=16V, VGS=0, f=1.0MHz ton VDD=10V, VGS=5.0V, ID=0.5A ton VDD=10V, VGS=4.5V, ID=950mA, RG=6.0Ω toff VDD=10V, VGS=5.0V, ID=0.5A toff VDD=10V, VGS=4.5V, ID=950mA, RG=6.0Ω N-CH (Q1) TYP 4.2 45 220 120 25 140 - P-CH (Q2) MIN TYP 2.0 80 200 60 20 25 UNITS S S pF pF pF pF pF pF ns ns ns ns TLM832D CASE - MECHANICAL OUTLINE PIN CONFIGURATION LEAD CODE: 1) Gate Q1 2) Source Q1 3) Gate Q2 4) Source Q2 5) Drain Q2 6) Drain Q2 7) Drain Q1 8) Drain Q1 MARKING CODE: CFK R2 (2-August 2011) w w w. c e n t r a l s e m i . c o m