74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop Features General Description ■ Input voltage level translation from 5V to 3V The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. ■ Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance Asynchronous Inputs: ■ LOW input to SD (Set) sets Q to HIGH level ■ LOW input to CD (Clear) sets Q to LOW level ■ Clear and Set are independent of clock ■ Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Information Order Number Package Number Package Description 74LVX74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVX74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1993 Fairchild Semiconductor Corporation 74LVX74 Rev. 1.4.0 www.fairchildsemi.com 74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop February 2008 Logic Symbols IEEE/IEC Pin Description Pin Names Description D1, D2 Data Inputs CP1, CP2 Clock Pulse Inputs CD1, CD2 Direct Clear Inputs SD1, SD2 Direct Set Inputs Q1, Q1, Q2, Q2 Outputs Truth Table (Each Half) Inputs Outputs SD CD CP D Q Q L H X X H L H L X X L H X L L X H H H H H H L H H L L H H H X Q0 Q0 L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Q0(Q0) = Previous Q(Q) before LOW-to-HIGH Transition of Clock ©1993 Fairchild Semiconductor Corporation 74LVX74 Rev. 1.4.0 www.fairchildsemi.com 2 74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop Connection Diagram Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC Parameter Rating Supply Voltage –0.5V to +7.0V IIK DC Input Diode Current, VI = –0.5V VI DC Input Voltage IOK DC Output Diode Current –20mA –0.5V to 7V VO = –0.5V –20mA VO = VCC + 0.5V +20mA VO DC Output Voltage –0.5V to VCC + 0.5V IO DC Output Source or Sink Current ±25mA ICC or IGND DC VCC or Ground Current TSTG Storage Temperature P ±50mA –65°C to +150°C Power Dissipation 180mW Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC Parameter Rating Supply Voltage 2.0V to 3.6V VI Input Voltage 0V to 5.5V VO Output Voltage 0V to VCC TA Operating Temperature ∆t / ∆V Input Rise and Fall Time –40°C to +85°C 0ns/V to 100ns/V Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1993 Fairchild Semiconductor Corporation 74LVX74 Rev. 1.4.0 www.fairchildsemi.com 3 74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop Absolute Maximum Ratings TA = +25°C Symbol VIH VIL VOH VOL Parameter VCC Conditions Min. Typ. Max. TA = –40°C to +85°C Min. Max. HIGH Level Input Voltage 2.0 1.5 1.5 3.0 2.0 2.0 3.6 2.4 LOW Level Input Voltage 2.0 0.5 0.5 3.0 0.8 0.8 3.6 0.8 0.8 HIGH Level Output Voltage LOW Level Output Voltage Units V 2.4 2.0 VIN = VIL or VIH, IOH = –50µA 1.9 2.0 1.9 3.0 VIN = VIL or VIH, IOH = –50µA 2.9 3.0 2.9 VIN = VIL or VIH, IOH = –4mA 2.58 V V 2.48 2.0 VIN = VIL or VIH, IOL = 50µA 0.0 0.1 0.1 3.0 VIN = VIL or VIH, IOL = 50µA 0.0 0.1 0.1 VIN = VIL or VIH, IOL = 4mA 0.36 0.44 V IIN Input Leakage Current 3.6 VIN = 5.5V or GND ±0.1 ±1.0 µA ICC Quiescent Supply Current 3.6 VIN = VCC or GND 2.0 20.0 µA Noise Characteristics(2) TA = 25°C Symbol Parameter VCC (V) CL (pF) Typ. Limit Units VOLP Quiet Output Maximum Dynamic VOL 3.3 50 0.3 0.5 V VOLV Quiet Output Minimum Dynamic VOL 3.3 50 –0.3 –0.5 V VIHD Minimum HIGH Level Dynamic Input Voltage 3.3 50 2.0 V VILD Maximum LOW Level Dynamic Input Voltage 3.3 50 0.8 V Note: 2. Input tr = tf = 3ns ©1993 Fairchild Semiconductor Corporation 74LVX74 Rev. 1.4.0 www.fairchildsemi.com 4 74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop DC Electrical Characteristics TA = –40°C to +85°C TA = +25°C Symbol Parameter tPLH, tPHL Propagation Delay, CPn to Qn or Qn VCC (V) CL (pF) 2.7 3.3 ± 0.3 tPLH, tPHL Propagation Delay, 2.7 CDn to SDn to Qn or Qn 3.3 ± 0.3 tW tS tH tREC fMAX CPn or CDn or SDn Pulse Width Typ. Max. Min. Max. Units 15 7.3 15 1.0 18.5 ns 50 9.8 18.5 1.0 22 15 5.7 9.7 1.0 11.5 50 8.2 13.2 1.0 15 15 8.4 15.6 1.0 18.5 50 10.9 19.1 1.0 22 15 6.6 10.1 1.0 12 50 9.1 13.6 1.0 15.5 2.7 8.5 10 3.3 ± 0.3 6 7 Setup Time, Dn to CPn 2.7 8.0 9.5 3.3 ± 0.3 5.5 6.5 2.7 0.5 0.5 3.3 ± 0.3 0.5 0.5 2.7 6.5 7.5 3.3 ± 0.3 5.0 5.0 Hold Time, Dn to CPn Recovery Time, CPn or SDn to CPn Min. Maximum Clock Frequency 2.7 3.3 ± 0.3 tOSLH, tOSHL Output to Output Skew(3) 2.7 15 55 135 50 50 45 60 40 15 95 145 80 50 60 85 50 50 3.3 ns ns ns ns ns MHz 1.5 1.5 1.5 1.5 ns Note: 3. Parameter guaranteed by design tOSLH = |tPLHm–tPLHn|, tOSHL = |tPHLm–tPHLn| Capacitance TA = –40°C to +85°C TA = +25°C Symbol Parameter Min. Typ. Max. 10 CIN Input Capacitance 4 CPD Power Dissipation Capacitance(4) 25 Min. Max. 10 Units pF pF Note: 4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. C PD × V CC × f IN × I CC Average operating current can be obtained by the eqation: ICC(opr.) = -------------------------------------------------------2 ( per, F ⁄ F ) ©1993 Fairchild Semiconductor Corporation 74LVX74 Rev. 1.4.0 www.fairchildsemi.com 5 74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop AC Electrical Characteristics 74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop Physical Dimensions 8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 1.27 LAND PATTERN RECOMMENDATION M C B A (0.33) 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13 0.50 X 45° 0.25 R0.10 R0.10 8° 0° 0.90 0.50 (1.04) SEATING PLANE DETAIL A SCALE: 20:1 Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1993 Fairchild Semiconductor Corporation 74LVX74 Rev. 1.4.0 www.fairchildsemi.com 6 74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1993 Fairchild Semiconductor Corporation 74LVX74 Rev. 1.4.0 www.fairchildsemi.com 7 0.65 0.43 TYP 1.65 6.10 0.45 12.00° TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1993 Fairchild Semiconductor Corporation 74LVX74 Rev. 1.4.0 www.fairchildsemi.com 8 74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop Physical Dimensions (Continued) ACEx® Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK® EZSWITCH™ * ™ PDP-SPM™ Power220® POWEREDGE® Power-SPM™ PowerTrench® Programmable Active Droop™ QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ SMART START™ SPM® STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 FPS™ FRFET® Global Power ResourceSM Green FPS™ Green FPS™e-Series™ GTO™ i-Lo™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ Motion-SPM™ OPTOLOGIC® OPTOPLANAR® ® Fairchild® Fairchild Semiconductor® FACT Quiet Series™ FACT® FAST® FastvCore™ FlashWriter® * ® SupreMOS™ SyncFET™ ® The Power Franchise® TinyBoost™ TinyBuck™ TinyLogic® TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ µSerDes™ UHC® Ultra FRFET™ UniFET™ VCX™ * EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I33 ©1993 Fairchild Semiconductor Corporation 74LVX74 Rev. 1.4.0 www.fairchildsemi.com 9 74LVX74 — Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.