DS5000(T) Soft Microcontroller Module www.maxim-ic.com FEATURES PIN ASSIGNMENT 8-Bit 8051-Compatible Microcontroller Adapts to Task at Hand 8 or 32 kbytes of Nonvolatile RAM for Program and/or Data Memory Storage Initial Downloading of Software in End System via On-Chip Serial Port Capable of Modifying Its Own Program and/or Data Memory in End Use Crashproof Operation Maintains All Nonvolatile Resources for 10 Years in the Absence of VCC at Room Temperature Power-Fail Reset Early Warning Power-Fail Interrupt Watchdog Timer Software Security Feature Executes Encrypted Software to Prevent Unauthorized Disclosure On-Chip, Full-Duplex Serial I/O Ports Two On-Chip Timer/Event Counters 32 Parallel I/O Lines Compatible with Industry Standard 8051 Instruction Set and Pinout Optional Permanently Powered Real-Time Clock (DS5000T) P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD P3.0 TXD P3.1 INT0 P3.2 INT1 P3.3 T0 P3.4 T1 P3.5 WR P3.6 RD P3.7 XTAL2 XTAL1 GND 1 40 2 39 3 DS5000(T) 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 VCC P0.0 AD0 P0.1 AD1 P0.2 AD2 P0.3 AD3 P0.4 AD4 P0.5 AD5 P0.6 AD6 P0.7 AD7 EA ALE PSEN P2.7 A15 P2.6 A14 P2.5 A13 P2.4 A12 P2.3 A11 P2.2 A10 P2.1 A9 P2.0 A8 40-Pin Encapsulated Package DESCRIPTION The DS5000(T) Soft Microcontroller Module is a fully 8051-compatible 8-bit CMOS microcontroller that offers “softness” in all aspects of its application. This is accomplished through the comprehensive use of nonvolatile technology to preserve all information in the absence of system VCC. The internal program/data memory space is implemented using either 8 or 32 kbytes of nonvolatile CMOS SRAM. Furthermore, internal data registers and key configuration registers are also nonvolatile. An optional realtime clock (RTC) gives permanently powered timekeeping. The clock keeps time to a hundredth of a second using an on-board crystal. Note: This data sheet provides ordering information, pinout, and electrical specifications. Refer to the Secure Microcontroller User’s Guide for operating information. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 19 REV: 070706 DS5000(T) ORDERING INFORMATION RAM SIZE (kB) MAX CRYSTAL SPEED (MHz) TIMEKEEPING? DS5000-32-16 32 16 No DS5000-32-16+ 32 16 No DS5000T-32-16 32 16 Yes DS5000T-32-16+ 32 16 Yes PART + Denotes a lead-free package. DS5000(T) BLOCK DIAGRAM Figure 1 2 of 19 DS5000(T) PIN DESCRIPTION PIN NAME 1–8 P1.0–P1.7 9 RST Active-High Reset Input. A logic 1 applied to this pin will activate a reset state. This pin is pulled down internally so this pin can be left unconnected if not used. 10 P3.0/RXD General-Purpose I/O Port Pin 3.0/Receive Signal for On-Board UART. This pin should not be connected directly to a PC COM port. 11 P3.1/TXD General-Purpose I/O Port Pin 3.1/Transmit Signal for On-Board UART. This pin should not be connected directly to a PC COM port. 12 P3.2/INT0 General-Purpose I/O Port Pin 3.2/Active-Low External Interrupt 0 13 P3.3/INT1 General-Purpose I/O Port Pin 3.3/Active-Low External Interrupt 1 14 P3.4/T0 General-Purpose I/O Port Pin 3.4/Timer 0 Input 15 P3.5/T1 General-Purpose I/O Port Pin 3.5/Timer 1 Input 16 P3.6/WR General-Purpose I/O Port Pin 3.6/Active-Low Write Strobe for Expanded Bus Operation 17 P3.7/RD General-Purpose I/O Port Pin 3.7/Active-Low Read Strobe for Expanded Bus Operation 18, 19 XTAL2, XTAL1 Crystal Connection. Used to connect an external crystal to the internal oscillator. XTAL1 is the input to an inverting amplifier and XTAL2 is the output. 20 GND 21–28 P2.0–P2.7/ A8–A15 29 30 FUNCTION General-Purpose I/O Port 1 Logic Ground General-Purpose I/O Port 2/MSB of the Expanded Address Bus PSEN Active-Low Program Store Enable. Used to enable an external program memory when using the expanded bus. It is normally an output and should be unconnected if not used. PSEN also is used to invoke the bootstrap loader. At this time, PSEN is pulled down externally. This should only be done once the DS5000(T) is already in a reset state. The device that pulls down should be open drain since it must not interfere with PSEN under normal operation. ALE Address Latch Enable. Used to demultiplex the multiplexed expanded address/data bus on Port 0. This pin is normally connected to the clock input on a ’373 type transparent latch. When using a parallel programmer, this pin also assumes the PROG function for programming pulses. 31 EA 32-39 P0.7–P0.0/ AD7–AD0 40 VCC Active-Low External Access. This pin forces the DS5000(T) to behave like an 8031. No internal memory (or clock) is available when this pin is at a logic low. Since this pin is pulled down internally, it should be connected to +5V to use NV RAM. In a parallel programmer, this pin also serves as VPP for super voltage pulses. General-Purpose I/O Port 0/Multiplexed Expanded Address/Data Bus. This port is open drain and cannot drive a logic 1. It requires external pullups. When used in the multiplexed expanded address data/bus mode, this pin does not require pullups. +5V Power Supply 3 of 19 DS5000(T) INSTRUCTION SET The DS5000(T) executes an instruction set which is object code-compatible with the industry standard 8051 microcontroller. As a result, software development packages that have been written for the 8051, including cross-assemblers, high-level language compilers, and debugging tools, are compatible with the DS5000(T). A complete description for the DS5000(T) instruction set is available in Secure Microcontroller User’s Guide. MEMORY ORGANIZATION Figure 2 illustrates the address spaces, which are accessed by the DS5000(T). As illustrated in the figure, separate address spaces exist for program and data memory. Since the basic addressing capability of the machine is 16 bits, a maximum of 64 kbytes of program memory and 64 kbytes of data memory can be accessed by the DS5000(T) CPU. The 8- or 32-kbyte RAM area inside of the DS5000(T) can be used to contain both program and data memory. The real-time clock (RTC) in the DS5000T is reached in the memory map by setting a SFR bit. The MCON.2 bit (ECE2) is used to select an alternate data memory map. While ECE2 = 1, all MOVXs will be routed to this alternate memory map. The RTC is a serial device that resides in this area. A full description of the RTC access and example software is given in the Secure Microcontroller User’s Guide. If the ECE2 bit is set on a DS5000 without a timekeeper, the MOVXs will simply go to a nonexistent memory. Software execution would not be affected otherwise. 4 of 19 DS5000(T) DS5000(T) LOGICAL ADDRESS SPACES Figure 2 PROGRAM LOADING The Program Load Modes allow initialization of the NV RAM Program/Data Memory. This initialization may be performed in one of two ways: 1. Serial Program Loading that can perform Bootstrap Loading of the DS5000(T). This feature allows the loading of the application program to be delayed until the DS5000(T) is installed in the end system. Dallas Semiconductor strongly recommends the use of serial program loading because of its versatility and ease of use. 2. Parallel Program Load cycles that perform the initial loading from parallel address/data information presented on the I/O port pins. This mode is timing-set compatible with the 8751H microcontroller programming mode. The DS5000(T) is placed in its Program Load configuration by simultaneously applying a logic 1 to the RST pin and forcing the PSEN line to a logic 0 level. Immediately following this action, the DS5000(T) will look for a parallel Program Load pulse, or a serial ASCII carriage return (0DH) character received at 9600, 2400, 1200, or 300 bps over the serial port. The hardware configurations used to select these modes of operation are illustrated in Figure 3. 5 of 19 DS5000(T) PROGRAM LOADING CONFIGURATIONS Figure 3 Table 1 summarizes the selection of the available Parallel Program Load cycles. The timing associated with these cycles is illustrated in the electrical specs. SERIAL BOOTSTRAP LOADER The Serial Program Load Mode is the easiest, fastest, most reliable, and most complete method of initially loading application software into the DS5000(T) nonvolatile RAM. Communication can be performed over a standard asynchronous serial communications port. A typical application would use a simple RS232C serial interface to program the DS5000(T) as a final production procedure. The hardware configuration required for the Serial Program Load mode is illustrated in Figure 3. Port pins 2.7 and 2.6 must be either open or pulled high to avoid placing the DS5000(T) in a parallel load cycle. Although an 11.0592 MHz crystal is shown in Figure 3, a variety of crystal frequencies and loader baud rates are supported, shown in Table 2. The serial loader is designed to operate across a 3-wire interface from a standard UART. The receive, transmit, and ground wires are all that are necessary to establish communication with the DS5000(T). The Serial Bootstrap Loader implements an easy-to-use command line interface that allows an application program in an Intel hex representation to be loaded into and read back from the device. Intel hex is the typical format which existing 8051 cross-assemblers output. The serial loader responds to single character commands, which are summarized below: 6 of 19 DS5000(T) COMMAND C D F K L R T U V W Z P G FUNCTION Return CRC-16 checksum of embedded RAM Dump Intel hex file Fill embedded RAM block with constant Load 40-bit encryption key Load Intel hex file Read MCON register Trace (echo) incoming Intel hex data Clear security lock Verify embedded RAM with incoming Intel hex Write MCON register Set security lock Put a value to a port Get a value from a port PARALLEL PROGRAM LOAD CYCLES Table 1 MODE RST PSEN PROG EA P2.7 P2.6 P2.5 Program 1 0 0 VPP 1 0 X Security Set 1 0 0 VPP 1 1 X Verify 1 X X 1 0 0 X Prog Expanded 1 0 0 VPP 0 1 0 Verify Expanded 1 0 1 1 0 1 0 Prog MCON or Key registers 1 0 0 VPP 0 1 1 Verify MCON registers 1 0 1 1 0 1 1 The Parallel Program Cycle is used to load a byte of data into a register or memory location within the DS5000(T). The Verify Cycle is used to read this byte back for comparison with the originally loaded value to verify proper loading. The Security Set Cycle may be used to enable and the Software Security feature of the DS5000(T). One may also enter bytes for the MCON register or for the five encryption registers using the Program MCON cycle. When using this cycle, the absolute register address must be presented at Ports 1 and 2 as in the normal program cycle (Port 2 should be 00H). The MCON contents can likewise be verified using the Verify MCON cycle. When the DS5000(T) first detects a Parallel Program Strobe pulse or a Security Set Strobe pulse while in the Program Load Mode following a Power-On Reset, the internal hardware of the DS5000(T) is initialized so that an existing 4-kbyte program can be programmed into a DS5000(T) with little or no modification. This initialization automatically sets the Range Address for 8 kbytes and maps the lowest 4kbyte bank of Embedded RAM as program memory. The next 4 kbytes of Embedded RAM are mapped as Data Memory. In order to program more than 4 kbytes of program code, the Program/Verify Expanded cycles can be used. Up to 32 kbytes of program code can be entered and verified. Note that the expanded 32-kbyte Program/ Verify cycles take much longer than the normal 4-kbyte Program/Verify cycles. 7 of 19 DS5000(T) A typical parallel loading session would follow this procedure. First, set the contents of the MCON register with the correct range and partition only if using expanded programming cycles. Next, the encryption registers can be loaded to enable encryption of the program/data memory (not required). Then, program the DS5000(T) using either normal or expanded program cycles and check the memory contents using Verify cycles. The last operation would be to turn on the security lock feature by either a Security Set cycle or by explicitly writing to the MCON register and setting MCON.0 to a 1. SERIAL LOADER BAUD RATES FOR DIFFERENT CRYSTAL FREQUENCIES Table 2 CRYSTAL FREQ (MHz) 14.7456 11.0592 9.21600 7.37280 5.52960 1.84320 BAUD RATE 300 1200 2400 9600 19200 57600 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y ADDITIONAL INFORMATION Refer to the Secure Microcontroller User’s Guide for a complete description for all operational aspects of the DS5000(T). DEVELOPMENT SUPPORT The DS89C450-K00 evaluation kit (www.maxim-ic.com/DS89C450evkit) can be used to develop and test user code. It allows the user to download Intel hex-formatted code to the DS5000(T) from a PC. Refer to the Secure Microcontroller User’s Guide for more information. 8 of 19 DS5000(T) ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground…………………………………………………….-0.3V to +7.0V Operating Temperature…………………………………………………………………….….0°C to +70°C Storage Temperature………………………………………………………………………...-40°C to +70°C Soldering Temperature.…………………………………………See IPC/JEDEC J-STD-020 Specification This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. (tA=0°C to 70°C; VCC=5V ± 5%) DC CHARACTERISTICS PARAMETER SYMBOL MIN Input Low Voltage VIL Input High Voltage TYP MAX UNITS NOTES -0.3 0.8 V 1 VIH1 2.0 VCC+0.3 V 1 Input High Voltage RST, XTAL1 VIH2 3.5 VCC+0.3 V 1 Output Low Voltage @ IOL=1.6 mA (Ports 1, 2, 3) VOL1 0.15 0.45 V Output Low Voltage @ IOL=3.2 mA (Ports 0, ALE, PSEN ) VOL2 0.15 0.45 V 1 Output High Voltage @ IOH=-80 µA (Ports 1, 2, 3) VOH1 2.4 4.8 V 1 Output High Voltage @ IOH=-400 µA (Ports 0, ALE, PSEN ) VOH2 2.4 4.8 V 1 Input Low Current VIN = 0.45V (Ports 1, 2, 3) IIL -50 µA Transition Current; 1 to 0 VIN=2.0V (Ports 1, 2, 3) ITL -500 µA Input Leakage Current 0.45 < VIN < VCC (Port 0) IL ±10 µA 125 kΩ 80 µA 4 RST, EA Pulldown Resistor RRE Stop Mode Current ISM 40 Power-Fail Warning Voltage VPFW 4.15 4.6 4.75 V 1 Minimum Operating Voltage VCCmin 4.05 4.5 4.65 V 1 Programming Supply Voltage (Parallel Program Mode) VPP 12.5 13 V 1 Program Supply Current IPP 15 20 mA Operating Current DS5000-8k @ 8MHz DS5000-32k @ 12 MHz DS5000(T)-32-16 @ 16 MHz ICC 25.2 35.7 45.6 43 48 54 mA 2 Idle Mode Current @ 12 MHz ICC 4.5 6.2 mA 3 9 of 19 DS5000(T) AC CHARACTERISTICS: EXPANDED BUS MODE TIMING SPECIFICATIONS # PARAMETER 1 (tA=0°C to 70°C; VCC=5V ± 5%) SYMBOL MIN MAX UNITS Oscillator Frequency 1/tCLK 1.0 16 MHz 2 ALE Pulse Width tALPW 2tCLK -40 ns 3 Address Valid to ALE Low tAVALL tCLK -40 ns 4 Address Hold After ALE Low tAVAAV tCLK -35 ns 5 ALE Low to Valid Instr. In 6 ALE Low to PSEN Low tALLPSL tCLK -25 ns 7 PSEN Pulse Width tPSPW 3tCLK -35 ns 8 PSEN Low to Valid Instr. In 9 Input Instr. Hold after PSEN Going High tPSIV 10 Input Instr. Float after PSEN Going High tPSIX 11 Address Hold after PSEN Going High tPSAV 12 Address Valid to Valid Instr. In @ 12 MHz @ 16 MHz tAVVI 13 PSEN 14 RD 15 WR 16 RD 17 Data Hold after RD High tRDHDV 18 Data Float after RD High tRDHDZ 2tCLK -70 ns 19 ALE Low to Valid Data In @ 12 MHz @ 16 MHz tALLVD 8CLK -150 8tCLK -90 ns ns 20 Valid Addr. to Valid Data In @ 12 MHz @ 16 MHz tAVDV 9tCLK -165 9tCLK -105 ns ns 21 ALE Low to RD or WR Low tALLRDL 3tCLK -50 3tCLK +50 ns 22 Address Valid to RD or WR Low tAVRDL 4tCLK -130 ns 23 Data Valid to WR Going Low tDVWRL tCLK -60 ns 24 Data Valid to WR High tDVWRH 7tCLK -150 7tCLK -90 ns ns 25 Data Valid after WR High tWRHDV tCLK -50 ns 26 RD Low to Address Float tRDLAZ 27 RD or WR High to ALE High tRDHALH @ 12 MHz @ 16 MHz tALLVI 4tCLK -150 4tCLK -90 3tCLK -150 3tCLK -90 tPSLVI @ 12 MHz @ 16 MHz 0 ns ns ns ns ns tCLK -20 tCLK -8 ns ns 5tCLK -150 5tCLK -90 ns ns tPSLAZ 0 ns Pulse Width tRDPW 6tCLK -100 ns Pulse Width tWRPW 6tCLK -100 ns Low to Address Float Low to Valid Data In @ 12 MHz @ 16 MHz 5tCLK -165 5tCLK -105 tRDLDV @ 12 MHz @ 16 MHz 10 of 19 0 tCLK -40 ns ns ns 0 ns tCLK +50 ns DS5000(T) EXPANDED PROGRAM MEMORY READ CYCLE EXPANDED DATA MEMORY READ CYCLE 11 of 19 DS5000(T) EXPANDED DATA MEMORY WRITE CYCLE EXTERNAL CLOCK TIMING 12 of 19 DS5000(T) AC CHARACTERISTICS (cont'd) EXTERNAL CLOCK DRIVE # PARAMETER 28 External Clock High Time 29 (tA=0°C to 70°C; VCC=5V ± 5%) SYMBOL MIN @ 12 MHz @ 16 MHz tCLKHPW 20 15 ns ns External Clock Low Time @ 12 MHz @ 16 MHz tCLKLPW 20 15 ns ns 30 External Clock Rise Time @ 12 MHz @ 16 MHz tCLKR 20 15 ns ns 31 External Clock Fall Time @ 12 MHz @ 16 MHz tCLKF 20 15 ns ns AC CHARACTERISTICS (cont'd) SERIAL PORT TIMING - MODE 0 # PARAMETER 35 MAX UNITS (tA=0°C to 70°C; VCC=5V ± 5%) SYMBOL MIN Serial Port Cycle Time tSPCLK 12tCLK µs 36 Output Data Setup to Rising Clock Edge tDOCH 10tCLK -133 ns 37 Output Data Hold after Rising Clock Edge tCHDO 2tCLK -117 ns 38 Clock Rising Edge to Input Data Valid tCHDV 39 Input Data Hold after Rising Clock Edge tCHDIV SERIAL PORT TIMING - MODE 0 13 of 19 MAX 10tCLK -133 0 UNITS ns ns DS5000(T) AC CHARACTERISTICS (cont'd) POWER CYCLING TIMING (tA=0°C to 70°C; VCC=5V ± 5%) # PARAMETER SYMBOL MIN tF 40 32 Slew Rate from VCCmin to 3.3V 33 Crystal Start-up Time tCSU (note 5) 34 Power-on Reset Delay tPOR 21504 POWER CYCLE TIMING 14 of 19 MAX UNITS µs tCLK DS5000(T) AC CHARACTERISTICS (cont'd) PARALLEL PROGRAM LOAD TIMING # PARAMETER 40 (tA=0°C to 70°C; VCC=5V ± 5%) SYMBOL MIN MAX UNITS Oscillator Frequency 1/tCLK 1.0 12.0 MHz 41 Address Setup to PROG Low tAVPRL 0 42 Address Hold after PROG High tPRHAV 0 43 Data Setup to PROG Low tDVPRL 0 44 Data Hold after PROG High tPRHDV 0 45 P2.7, 2.6, 2.5 Setup to VPP tP27HVP 0 46 VPP Setup to PROG Low tVPHPRL 0 47 VPP Hold after PROG Low tPRHVPL 0 48 PROG Width Low tPRW 2400 49 Data Output from Address Valid tAVDV 48 1800* tCLK 50 Data Output from P2.7 Low tDVP27L 48 1800* tCLK 51 Data Float after P2.7 High tP27HDZ 0 48 1800* tCLK 52 Delay to Reset/ PSEN Active after Power On tPORPV 21504 tCLK 53 Reset/ PSEN Active (or Verify Inactive) to VPP High tRAVPH 1200 tCLK 54 VPP Inactive (Between Program Cycles) tVPPPC 1200 tCLK 55 Verify Active Time tVFT 48 2400* tCLK * Second set of numbers refers to expanded memory programming up to 32k bytes. 15 of 19 tCLK DS5000(T) PARALLEL PROGRAM LOAD TIMING (test frequency=1MHz; tA=25°C) CAPACITANCE PARAMETER SYMBOL MIN TYP MAX UNITS Output Capacitance CO 10 pF Input Capacitance CI 10 pF 16 of 19 NOTES DS5000(T) DS5000(T) TYPICAL ICC VS. FREQUENCY Normal operation is measured using: 1) External crystals on XTAL1 and 2 2) All port pins disconnected 3) RST=0 volts and EA=VCC 4) Part performing endless loop writing to internal memory Idle mode operation is measured using: 1) External clock source at XTAL1; XTAL2 floating 2) All port pins disconnected 3) RST=0 volts and EA=VCC 4) Part set in IDLE mode by software 17 of 19 DS5000(T) NOTES: 1. All voltages are referenced to ground. 2. Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF = 10 ns, VIL = 0.5V; XTAL2 disconnected; EA = RST = PORT0 = VCC. 3. Idle mode ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF = 10 ns, VIL = 0.5V; XTAL2 disconnected; EA = PORT0 = VCC, RST = VSS. 4. Stop mode ICC is measured with all output pins disconnected; EA = PORT0 = VCC; XTAL2 not connected; RST = VSS. 5. Crystal start-up time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit until the first clock pulse is produced by the on-chip oscillator. The user should check with the crystal vendor for the worst case spec on this time. PACKAGE DRAWING DIM 18 of 19 INCHES MIN MAX A IN. 2.080 2.100 B IN. 0.680 0.700 C IN. 0.290 0.325 D IN. 0.090 0.110 E IN. 0.030 0.060 F IN. 0.145 0.185 G IN. 0.016 0.020 H IN. 0.590 0.610 I IN. 0.009 0.015 DS5000(T) DATA SHEET REVISION SUMMARY REVISION 072095 to 072496 112299 DESCRIPTION Corrected Figure 3 to show RST active high. Added Data Sheet Revision Summary section. Converted from Interleaf to Word. Page 1: Features Added “at Room Temperature” to “Maintains All Nonvolatile Resources Up to 10 Years in the Absence of VCC” bullet. Page 2: Ordering Information Removed 8kB parts from list; added 32kB and lead-free packages. 070706 Page 8: Development Support Updated paragraph to reflect availability of DS89C450-K00 evaluation kit, not DS5000TK. Page 9: Absolute Maximum Ratings Changed “260°C for 10 seconds” to “See IPC/JEDEC J-STD-020 Specification.” Pages 1, 4, 8: Replaced references to “User’s Guide section of Secure Microcontroller Data Book” with “Secure Microcontroller User’s Guide.” 19 of 19 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.