FREESCALE MC68HC08KL8FB

Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
HC08KL8GRS/D
REV. 2.0
68HC08KL8
General Release Specification
August 10, 1998
Personal and PC Media Division
Austin, Texas
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
General Release Specification
General Release Specification
MC68HC08KL8 — Rev. 2.0
For More regarding
Information
This Product,
was negligent
theOn
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or manufacture of the part.
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General Release Specification — MC68HC08KL8
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . 23
R E Q U I R E D
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Section 4. Read-Only Memory (ROM) . . . . . . . . . . . . . . . 51
Section 5. Mask Option Register (MOR) . . . . . . . . . . . . . 53
Section 6. Central Processor Unit (CPU) . . . . . . . . . . . . 57
Section 7. Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Section 8. System Integration Module (SIM) . . . . . . . . . 77
Section 9. Universal Serial Bus Module (USB) . . . . . . . 103
Section 10. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . 151
Section 11. Timer Interface Module (TIM) . . . . . . . . . . . 165
Section 12. Input/Output Ports (I/O) . . . . . . . . . . . . . . . 189
Section 13. Computer Operating Properly (COP) . . . . 211
Section 14. External Interrupt (IRQ) . . . . . . . . . . . . . . . 217
Section 15. Keyboard Interrupt Module (KBI). . . . . . . . 225
Section 16. Break Module (BREAK) . . . . . . . . . . . . . . . 233
Section 17. Electrical Specifications . . . . . . . . . . . . . . . 239
Section 18. Mechanical Specifications . . . . . . . . . . . . . 249
Section 19. Ordering Information . . . . . . . . . . . . . . . . . 253
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A G R E E M E N T
Section 3. Random-Access Memory (RAM) . . . . . . . . . . 49
N O N - D I S C L O S U R E
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Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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List of Sections
General Release Specification
MC68HC08KL8 — Rev. 2.0
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Section 1. General Description
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5.1
Power Supply Pins (VDDREG, VSSREG, VDD1,
VSS1, VDD2, and VSS2) . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5.2
Voltage Regulator Out (REGOUT) . . . . . . . . . . . . . . . . . . 31
1.5.3
Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . 31
1.5.4
External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.5.5
External Interrupt Pin (IRQ1). . . . . . . . . . . . . . . . . . . . . . . 32
1.5.6
USB Data Pins (D+ and D–) . . . . . . . . . . . . . . . . . . . . . . . 32
1.5.7
Port A Input/Output (I/O) Pins (PTA7–PTA0) . . . . . . . . . . 32
1.5.8
Port B (I/O) Pins (PTB7–PTB0). . . . . . . . . . . . . . . . . . . . . 32
1.5.9
Port C I/O Pins (PTC7–PTC0). . . . . . . . . . . . . . . . . . . . . . 32
1.5.10
Port D I/O Pins (PTD7/KBD7–PTD0/KBD0) . . . . . . . . . . . 33
1.5.11
Port E I/O Pins (PTE6–PTE3 and PTE2/TCH1,
PTE1/TCH0, PTE0/TCLK) . . . . . . . . . . . . . . . . . . . . . . 33
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A G R E E M E N T
Table of Contents
N O N - D I S C L O S U R E
General Release Specification — MC68HC08KL8
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
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Table of Contents
Section 2. Memory Map
2.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.3
Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.4
Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .37
2.5
Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.6
Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Section 3. Random-Access Memory (RAM)
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Section 4. Read-Only Memory (ROM)
4.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Section 5. Mask Option Register (MOR)
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
5.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
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Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
6.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
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6.4
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.4.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.4.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
6.4.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
6.4.4
Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
6.4.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .63
6.5
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .65
6.6
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
6.7
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Section 7. Oscillator
7.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7.3
Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . .74
7.4
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
7.4.1
Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . . .75
7.4.2
Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . .75
7.4.3
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . .75
7.4.4
External Clock Source (CGMXCLK) . . . . . . . . . . . . . . . . . .75
7.4.5
Oscillator Out (CGMOUT) . . . . . . . . . . . . . . . . . . . . . . . . . .76
7.5
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
7.5.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
7.5.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
7.6
Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . .76
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A G R E E M E N T
6.1
N O N - D I S C L O S U R E
Section 6. Central Processor Unit (CPU)
R E Q U I R E D
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Section 8. System Integration Module (SIM)
8.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
8.3
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . .81
8.3.1
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
8.3.2
Clock Startup from POR . . . . . . . . . . . . . . . . . . . . . . . . . . .82
8.3.3
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . .82
8.4
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . .82
8.4.1
External Pin Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
8.4.2
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . .84
8.4.2.1
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
8.4.2.2
Computer Operating Properly (COP) Reset. . . . . . . . . . .86
8.4.2.3
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
8.4.2.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
8.4.2.5
Universal Serial Bus Reset . . . . . . . . . . . . . . . . . . . . . . .87
8.5
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
8.5.1
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . .87
8.5.2
SIM Counter During Stop Mode Recovery . . . . . . . . . . . . .88
8.5.3
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . .88
8.6
Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
8.6.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
8.6.1.1
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
8.6.1.2
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
8.6.2
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . .92
8.6.2.1
Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . .93
8.6.2.2
Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . .94
8.6.3
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
8.6.4
Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
8.6.5
Status Flag Protection in Break Mode. . . . . . . . . . . . . . . . .95
8.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
8.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
8.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
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9.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
9.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
9.3
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
9.3.1
9.3.1.1
9.3.1.2
9.3.1.3
9.3.1.4
9.3.1.5
9.3.1.6
9.3.2
9.3.3
9.3.4
9.3.4.1
9.3.4.2
9.3.4.3
9.3.5
9.4
USB Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Sync Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Packet Identifier Field. . . . . . . . . . . . . . . . . . . . . . . . . . .110
Address Field (ADDR) . . . . . . . . . . . . . . . . . . . . . . . . . .110
Endpoint Field (ENDP). . . . . . . . . . . . . . . . . . . . . . . . . .110
Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . .111
End-of-Packet (EOP) . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Reset Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Resume After Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Host Initiated Resume . . . . . . . . . . . . . . . . . . . . . . . . . .115
USB Reset Signalling. . . . . . . . . . . . . . . . . . . . . . . . . . .116
Remote Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Low-Speed Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
9.5
Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
9.5.1
Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
9.5.2
Regulator Bypass Option . . . . . . . . . . . . . . . . . . . . . . . . .119
9.5.3
USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
9.5.3.1
Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . .120
9.5.3.2
Low Speed (1.5 Mbs) Driver Characteristics . . . . . . . . .120
9.5.3.3
Receiver Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
9.5.3.4
Data Source Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
9.5.3.5
Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . .123
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Section 9. Universal Serial Bus Module (USB)
N O N - D I S C L O S U R E
8.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.8.1
Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.8.2
Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
8.8.3
Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . .102
R E Q U I R E D
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9.5.4
9.5.4.1
9.5.4.2
USB Control Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Data Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . .125
Bit Stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
9.6
I/O Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
9.6.1
USB Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . .131
9.6.2
USB Interrupt Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . .132
9.6.3
USB Interrupt Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . .134
9.6.4
USB Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . .136
9.6.5
USB Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . .138
9.6.6
USB Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .140
9.6.7
USB Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
9.6.8
USB Endpoint 0 Data Registers . . . . . . . . . . . . . . . . . . . .143
9.6.9
USB Endpoint 1/Endpoint 2 Data Registers . . . . . . . . . . .144
9.7
USB Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
9.7.1
USB End-of-Transaction Interrupt . . . . . . . . . . . . . . . . . . .145
9.7.1.1
Receive Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . . .145
9.7.1.2
Transmit Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . .148
9.7.1.3
Transmit Endpoint 1 and Transmit Endpoint 2. . . . . . . .149
9.7.2
Resume Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
9.7.3
End-of-Packet Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .150
Section 10. Monitor ROM (MON)
10.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
10.4.1
Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .154
10.4.2
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
10.4.3
Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
10.4.4
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
10.4.5
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
10.5
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
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Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
11.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
Freescale Semiconductor, Inc...
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
11.4.1
TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . .170
11.4.2
Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
11.4.3
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
11.4.3.1
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .170
11.4.3.2
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .171
11.4.4
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . .172
11.4.4.1
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .173
11.4.4.2
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .174
11.4.4.3
PWM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
11.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
11.6
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
11.7
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .177
11.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
11.8.1
TIM Clock Pin (PTE0/TCLK) . . . . . . . . . . . . . . . . . . . . . . .178
11.8.2
TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1). . . . . . .178
11.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
11.9.1
TIM Status and Control Register . . . . . . . . . . . . . . . . . . . .179
11.9.2
TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .181
11.9.3
TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . .182
11.9.4
TIM Channel Status and Control Registers. . . . . . . . . . . .183
11.9.5
TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .187
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N O N - D I S C L O S U R E
Section 11. Timer Interface Module (TIM)
R E Q U I R E D
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Section 12. Input/Output Ports (I/O)
12.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
12.3.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
12.3.2
Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . .193
12.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
12.4.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
12.4.2
Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . .196
12.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
12.5.1
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
12.5.2
Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . .199
12.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
12.6.1
Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
12.6.2
Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . .202
12.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
12.7.1
Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
12.7.2
Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . .206
12.8 Port Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
12.8.1
Port Option Control Register . . . . . . . . . . . . . . . . . . . . . . .208
Section 13. Computer Operating Properly (COP)
13.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
13.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
13.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
13.4.1
CGMXCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
13.4.2
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
13.4.3
COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
13.4.4
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
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13.5
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
13.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
13.7
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
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13.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
13.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
13.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
13.9
COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .216
Section 14. External Interrupt (IRQ)
14.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
14.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
14.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
14.5
IRQ1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
14.6
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .222
14.7
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .222
Section 15. Keyboard Interrupt Module (KBI)
15.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
15.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
15.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
15.5
Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
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Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
COPD (COP Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
COPRS (COP Rate Select). . . . . . . . . . . . . . . . . . . . . . . .214
N O N - D I S C L O S U R E
13.4.5
13.4.6
13.4.7
13.4.8
R E Q U I R E D
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15.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
15.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
15.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
15.7
Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .230
15.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
15.8.1
Keyboard Status and Control Register . . . . . . . . . . . . . . .230
15.8.2
Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . .232
Section 16. Break Module (BREAK)
16.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
16.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
16.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
16.4.1
Flag Protection During Break Interrupts . . . . . . . . . . . . . .236
16.4.2
CPU During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . .236
16.4.3
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .236
16.4.4
COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . .236
16.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
16.5.1
Break Status and Control Register . . . . . . . . . . . . . . . . . .237
16.5.2
Break Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . .238
16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
16.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
16.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
Section 17. Electrical Specifications
17.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
17.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
17.3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .240
17.4
Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .241
17.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
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17.6
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .242
17.7
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
17.8
Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
17.9
USB DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .244
17.10 USB Low-Speed Source Electrical Characteristics . . . . . . . .245
17.11 USB Signaling Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
R E Q U I R E D
Table of Contents
17.13 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
Section 18. Mechanical Specifications
18.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
18.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
18.3
Quad Flat Pack (Case 848B-04). . . . . . . . . . . . . . . . . . . . . . .250
18.4
Shrink Dual In-Line Package (Case 858-01) . . . . . . . . . . . . .251
A G R E E M E N T
Freescale Semiconductor, Inc...
17.12 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . .247
19.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
19.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
19.3
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
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Section 19. Ordering Information
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Figure
Title
Page
1-1
1-2
1-3
1-4
1-5
MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52-Pin QFP Assignments (Top View). . . . . . . . . . . . . . . . .
42-Pin SDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . .
Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . .
Regulator Supply Capacitor Configuration . . . . . . . . . . . . .
2-1
2-2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Control, Status, and Data Registers. . . . . . . . . . . . . . . . . . .38
5-1
Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . .54
6-1
6-2
6-3
6-4
6-5
6-6
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Index Register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . .63
7-1
Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . .74
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
SIM Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
SIM Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Sources of Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . .84
POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Interrupt Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
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28
29
30
31
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List of Figures
N O N - D I S C L O S U R E
General Release Specification — MC68HC08KL8
R E Q U I R E D
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List of Figures
Figure
Title
Page
8-10
8-11
8-12
8-13
8-14
8-15
8-16
8-17
8-18
8-19
8-20
8-21
Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . .91
Interrupt Status Register 1 (INT1) . . . . . . . . . . . . . . . . . . . .93
Interrupt Status Register 2 (INT2) . . . . . . . . . . . . . . . . . . . .94
Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . .97
Wait Recovery from Internal Reset . . . . . . . . . . . . . . . . . . .97
Stop Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Stop Mode Recovery from Interrupt or Break. . . . . . . . . . . .98
Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . .99
Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . .101
Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . .102
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
USB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Supported Transaction Types Per Endpoint . . . . . . . . . . .107
Supported USB Packet Types . . . . . . . . . . . . . . . . . . . . . .108
Sync Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
SOP, Sync Signaling, and Voltage Levels . . . . . . . . . . . . .109
CRC Block Diagram for Token Packets . . . . . . . . . . . . . . .111
CRC Block Diagram for Data Packets . . . . . . . . . . . . . . . .112
EOP Transaction Voltage Levels . . . . . . . . . . . . . . . . . . . .113
EOP Width Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
External Low-Speed Device Configuration. . . . . . . . . . . . .117
Regulator Electrical Connections . . . . . . . . . . . . . . . . . . . .118
Regulator Bypass Option . . . . . . . . . . . . . . . . . . . . . . . . . .119
Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .121
Differential Input Sensitivity
Over Entire Common Mode Range . . . . . . . . . . . . . . . .121
Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . . . .123
NRZI Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Flow Diagram for NRZI. . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Bit Stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Flow Diagram for Bit Stuffing . . . . . . . . . . . . . . . . . . . . . . .127
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
USB Address Register (UADDR) . . . . . . . . . . . . . . . . . . . .131
9-15
9-16
9-17
9-18
9-19
9-20
9-21
9-22
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List of Figures
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9-31
9-32
9-33
9-34
Page
USB Interrupt Register 0 (UIR0). . . . . . . . . . . . . . . . . . . . .132
USB Interrupt Register 1 (UIR1). . . . . . . . . . . . . . . . . . . . .134
USB Control Register 0 (UCR0) . . . . . . . . . . . . . . . . . . . . .136
USB Control Register 1 (UCR1) . . . . . . . . . . . . . . . . . . . . .138
USB Control Register 2 (UCR2) . . . . . . . . . . . . . . . . . . . . .140
USB Status Register (USR) . . . . . . . . . . . . . . . . . . . . . . . .142
USB Endpoint 0 Data Register (UE0D0–UE0D7) . . . . . . .143
USB Endpoint 1/Endpoint 2 Data Register
(UE1D0–UE1D7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
OUT Token Data Flow for Receive Endpoint 0 . . . . . . . . .146
SETUP Token Data Flow for Receive Endpoint 0 . . . . . . .147
IN Token Data Flow for Transmit Endpoint 0 . . . . . . . . . . .148
IN Token Data Flow for Transmit
Endpoint 1/Endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . .149
10-1
10-2
10-3
10-4
10-5
10-6
10-7
Monitor Mode Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Monitor Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
Break Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Stack Pointer at Monitor Mode Entry . . . . . . . . . . . . . . . . .162
Monitor Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . .163
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
TIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
TIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . .168
PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . .172
TIM Status and Control Register (TSC) . . . . . . . . . . . . . . .179
TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . .181
TIM Counter Modulo Registers (TMODH:TMODL) . . . . . .182
TIM Channel Status and Control Registers
(TSC0:TSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
TIM Channel Registers (TCH0H/L:TCH1H/L) . . . . . . . . . .187
12-1
12-2
I/O Port Register Summary . . . . . . . . . . . . . . . . . . . . . . . .190
Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . .192
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A G R E E M E N T
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9-23
9-24
9-25
9-26
9-27
9-28
9-29
9-30
Title
N O N - D I S C L O S U R E
Figure
R E Q U I R E D
List of Figures
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
List of Figures
Figure
Title
Page
12-3
12-4
12-5
12-6
12-7
12-8
12-9
12-10
12-11
12-12
12-13
12-14
12-15
12-16
12-17
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . .193
Port A I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . .195
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . .196
Port B I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . .198
Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . .199
Port C I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . .201
Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . .202
Port D I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . .204
Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . .206
Port E I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
Port Option Control Register (POC) . . . . . . . . . . . . . . . . . .208
13-1
13-2
13-3
COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
COP I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . .212
COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . .215
14-1
14-2
14-3
IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .220
IRQ I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . .220
IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . .223
15-1
15-2
15-3
15-4
Keyboard Module Block Diagram. . . . . . . . . . . . . . . . . . . .226
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
Keyboard Status and Control Register (KBSCR) . . . . . . . .231
Keyboard Interrupt Enable Register (KBIER). . . . . . . . . . .232
16-1
16-2
16-3
16-4
Break Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . .235
Break I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . .235
Break Status and Control Register (BRKSCR) . . . . . . . . .237
Break Address Registers (BRKH and BRKL) . . . . . . . . . . .238
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Table
Title
Page
2-1
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
6-1
6-2
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
8-1
8-2
8-3
Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
9-1
Supported Packet Identifiers . . . . . . . . . . . . . . . . . . . . . . . . .110
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
Monitor Mode Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . .157
READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . .159
WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . .159
IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . .160
IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . .160
READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . .161
RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . .161
11-1 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
11-2 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . .185
12-1
12-2
12-3
12-4
12-5
Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
Port E Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
19-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
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A G R E E M E N T
List of Tables
N O N - D I S C L O S U R E
General Release Specification — MC68HC08KL8
R E Q U I R E D
Freescale Semiconductor, Inc.
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N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
List of Tables
General Release Specification
MC68HC08KL8 — Rev. 2.0
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1.1 Contents
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.4
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.5.1
Power Supply Pins (VDDREG, VSSREG, VDD1,
VSS1, VDD2, and VSS2) . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.5.2
Voltage Regulator Out (REGOUT) . . . . . . . . . . . . . . . . . . .31
1.5.3
Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . .31
1.5.4
External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.5.5
External Interrupt Pin (IRQ1). . . . . . . . . . . . . . . . . . . . . . . .32
1.5.6
USB Data Pins (D+ and D–) . . . . . . . . . . . . . . . . . . . . . . . .32
1.5.7
Port A Input/Output (I/O) Pins (PTA7–PTA0) . . . . . . . . . . .32
1.5.8
Port B (I/O) Pins (PTB7–PTB0). . . . . . . . . . . . . . . . . . . . . .32
1.5.9
Port C I/O Pins (PTC7–PTC0). . . . . . . . . . . . . . . . . . . . . . .32
1.5.10
Port D I/O Pins (PTD7/KBD7–PTD0/KBD0) . . . . . . . . . . . .33
1.5.11
Port E I/O Pins (PTE6–PTE3 and PTE2/TCH1,
PTE1/TCH0, PTE0/TCLK) . . . . . . . . . . . . . . . . . . . . . . .33
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A G R E E M E N T
Section 1. General Description
N O N - D I S C L O S U R E
General Release Specification — MC68HC08KL8
R E Q U I R E D
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N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
General Description
1.2 Introduction
The MC68HC08KL8 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the enhanced M68HC08
central processor unit (CPU08) and are available with a variety of
modules, memory sizes and types, and package types.
1.3 Features
Features of the MC68HC08KL8 include:
•
High-Performance M68HC08 Architecture
•
Fully Upward-Compatible Object Code with M6805, M146805,
and M68HC05 Families
•
1.5-MHz Internal Bus Operation
•
Eight Kbytes of On-Chip Read-Only Memory (ROM)
•
On-Chip Programming Firmware for Use with Host Personal
Computer
•
ROM Data Security1
•
368 Bytes of On-Chip Random Access Memory (RAM)
•
39 General-Purpose Input/Output (I/O) Ports, 24 with Software
Configurable Pullups
•
16-Bit, 2-Channel Timer Interface Module (TIM)
•
8-Bit Keyboard Interrupt (KBI) Port
•
Available in a 52-lead plastic quad flat pack (QFP) package:
– 39 general-purpose input/output (I/O), 24 with software
configurable pullups
– 16-bit, 2-channel timer interface module (TIM)
– Eight light-emitting diode (LED) direct drive port pins
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the EPROM/OTPROM difficult for unauthorized users.
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•
Full Compatibility with Universal Serial Bus (USB) Specification
Rev. 1.0
– Supports Non-Isochronous Data
– Bidirectional Half-Duplex Link
– 1.5 Mbps Data Rate (Low Speed)
•
On-Chip USB Transceiver
•
On-Chip 3.3-V Regulator for USB Transceiver
•
USB Data Control Logic
– Packet Decoding/Generation
– CRC Generation and Checking
– Non-Return-to-Zero Inverted (NRZI) Encoding/Decoding
and Bit-Stuffing
•
Two 8-Byte Transmit Buffers
– One Dedicated for Endpoint 0
– One Shared by Endpoint 1 and Endpoint 2
•
One 8-Byte Receive Buffer
– Dedicated for Control Endpoint 0
•
USB Suspend/Resume Operation
•
System Protection Features
– Optional Computer Operating Properly (COP) Reset
– Illegal Opcode Detection with Optional Reset
– Illegal Address Detection with Optional Reset
•
Low-Power Design, Fully Static with Stop Mode and Wait Mode
•
Master Reset Pin with Internal Pullup and Power-On Reset
•
External Asynchronous Interrupt Pin with Internal Pullup (IRQ1)
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R E Q U I R E D
Available in a 42-lead shrink dual in-line plastic (SDIP) package:
– 29 general-purpose input/output (I/O), 21 with software
configurable pullups
– Five light-emitting diode (LED) direct drive port pins
A G R E E M E N T
•
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
General Description
Features
Freescale Semiconductor, Inc.
Features of the CPU08 include:
•
Enhanced HC05 Programming Model
•
Extensive Loop Control Functions
•
16 Addressing Modes (Eight More Than the HC05)
•
16-Bit Index Register and Stack Pointer
•
Memory-to-Memory Data Transfers
•
Fast 8 × 8 Multiply Instruction
•
Fast 16/8 Divide Instruction
•
Binary-Coded Decimal (BCD) Instructions
•
Optimization for Controller Applications
•
Third Party C Language Support
1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC08KL8.
N O N - D I S C L O S U R E
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R E Q U I R E D
General Description
General Release Specification
MC68HC08KL8 — Rev. 2.0
General Description
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ARITHMETIC/LOGIC
UNIT (ALU)
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USB ENDPOINT 0, 1, 2
(2-Tx/1-Rx BUFFER)
USB
MODULE
PTE6**
PTE5**
PTE4**
PTE3**
PTE2/TCH1**
PTE1/TCH0**
PTE0/TCLK**
D+
D-
PTC7–PTC5 † ‡**
PTC4–PTC0 † ‡
PTD7/KBD7–
PTD0/KBD0
PTB7–PTB0 †
PTA7–PTA0 †
A G R E E M E N T
R E Q U I R E D
† Ports are software configurable with pullup device if input port.
‡ Software configurable LED direct drive 3 mA source /10 mA sink or standard drive
* Pin contains integrated pullup device
** Available in 52-lead QFP only
POWER-ON RESET
MODULE
TIMER INTERFACE
MODULE**
COMPUTER OPERATING PROPERLY
MODULE
BREAK
MODULE
INTERNAL BUS
Figure 1-1. MCU Block Diagram
N O N - D I S C L O S U R E
VSSREG
USB REGULATOR
POWER
VDD1
VSS1
VDD2
VSS2
REGOUT
3.3 V
VDDREG
IRQ
MODULE
SYSTEM INTEGRATION
MODULE
* RST
* IRQ1/VPP
OSCILLATOR
OSC1
OSC2
USER EPROM VECTOR SPACE — 16 BYTES
MONITOR ROM — 240 BYTES
USER RAM — 368 BYTES
USER EPROM — 8,192 BYTES
CONTROL AND STATUS REGISTERS — 64 BYTES
CPU
REGISTERS
M68HC08 CPU
DDRE
DDRA
DDRB
DDRC
DDRD
PTA
PTB
PTC
PTD
PTE
LS USB
TRANSCEIVER
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General Description
MCU Block Diagram
Freescale Semiconductor, Inc.
1.5 Pin Assignments
IRQ1
RST
OSC1
OSC2
VSS2
VDD2
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
51
50
49
48
47
46
45
44
43
42
41
40
1
PTE0/TCLK
PTE1/TCH0
52
Figure 1-2 shows the 52-pin QFP assignments and Figure 1-3 shows
the 42-pin SDIP assignments.
39
PTA1
8
32
PTB2
REGOUT
9
31
PTB1
VSSREG
10
30
PTB0
VDDREG
11
29
VDD1
PTD0/KBD0
12
28
VSS1
PTD1/KBD1
13
27
PTC7
26
D-
PTC6
PTB3
25
33
PTC5
7
24
D+
PTC4
PTB4
23
34
PTC3
6
22
PTE6
PTC2
PTB5
21
35
PTC1
5
20
PTE5
PTC0
PTB6
19
36
PTD7/KBD7
4
18
PTE4
PTD6/KBD6
PTB7
17
37
PTD5/KBD5
3
16
PTE3
PTD4/KBD4
PTA0
15
38
PTD3/KBD3
2
14
PTE2/TCH1
PTD2/KBD2
N O N - D I S C L O S U R E
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A G R E E M E N T
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General Description
Figure 1-2. 52-Pin QFP Assignments (Top View)
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1
42
PTA6
VDD2
2
41
PTA5
VSS2
3
40
PTA4
OSC2
4
39
PTA3
OSC1
5
38
PTA2
RST
6
37
PTA1
IRQ1
7
36
PTA0
D+
8
35
PTB7
D–
9
34
PTB6
REGOUT
10
33
PTB5
VSSREG
11
32
PTB4
VDDREG
12
31
PTB3
PTD0/KBD0
13
30
PTB2
PTD1/KBD1
14
29
PTB1
PTD2/KBD2
15
28
PTB0
PTD3/KBD3
16
27
VDD1
PTD4/KBD4
17
26
VSS1
PTD5/KBD5
18
25
PTC4
PTD6/KBD6
19
24
PTC3
PTD7/KBD7
20
23
PTC2
PTC0
21
22
PTC1
R E Q U I R E D
PTA7
A G R E E M E N T
Freescale Semiconductor, Inc...
General Description
Pin Assignments
N O N - D I S C L O S U R E
Figure 1-3. 42-Pin SDIP Pin Assignments
MC68HC08KL8 — Rev. 2.0
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1.5.1 Power Supply Pins (VDDREG, VSSREG, VDD1, VSS1, VDD2, and VSS2)
VDDREG and VSSREG are the power supply and ground pins used by the
on-board regulator. In regulator bypass, these become the supply pins
for the USB transceiver.
VDD1, VSS1, VDD2, and VSS2 are the power supply and ground pins. The
MCU operates from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as Figure 1-4
shows. Place the bypass capacitors as close to the MCU power pins as
possible. Use high-frequency-response ceramic capacitors for CBypass.
CBulk are optional bulk current bypass capacitors for use in applications
that require the port pins to source high current levels.
MCU
VDDREG, VDD1, VDD2
VSSREG,VSS1, VSS2
CBypass
0.1 µF
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
General Description
+
CBulk
VDD
NOTE: Component values shown represent typical applications.
Figure 1-4. Power Supply Bypassing
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MCU
REGOUT
VSSREG
CRegbypass
0.1 µF
+
CRegbulk
> 1 µF
VREGOUT
Figure 1-5. Regulator Supply Capacitor Configuration
1.5.3 Oscillator Pins (OSC1 and OSC2)
The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit. (See Section 7. Oscillator.)
1.5.4 External Reset Pin (RST)
A logic 0 on the RST pin forces the MCU to a known startup state. RST
is bidirectional, allowing a reset of the entire system. It is driven low when
any internal reset source is asserted. The RST pin contains an internal
pullup device. (See Section 8. System Integration Module (SIM).)
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REGOUT is the 3.3-V output of the on-chip voltage regulator. It is used
to supply the voltage for the external pullup resistor required on the
USB’s D– line. REGOUT also is used internally for the USB data driver.
The REGOUT pin requires an external bulk capacitor 1 µF or larger and
a 0.1-µF ceramic bypass capacitor as Figure 1-5 shows. Place the
bypass capacitors as close to the REGOUT pin as possible. (See
Section 9. Universal Serial Bus Module (USB).)
A G R E E M E N T
1.5.2 Voltage Regulator Out (REGOUT)
R E Q U I R E D
General Description
Pin Assignments
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A G R E E M E N T
R E Q U I R E D
General Description
1.5.5 External Interrupt Pin (IRQ1)
IRQ1 is an asynchronous external interrupt pin. The IRQ1 pin contains
an internal pullup device. (See Section 14. External Interrupt (IRQ).)
1.5.6 USB Data Pins (D+ and D–)
D+ and D– are the differential data lines used by the USB module. (See
Section 9. Universal Serial Bus Module (USB).)
1.5.7 Port A Input/Output (I/O) Pins (PTA7–PTA0)
PTA7–PTA0 are general-purpose bidirectional I/O port pins. (See
Section 12. Input/Output Ports (I/O).) Each pin contains a software
configurable pullup device when the pin is configured as an input. (See
12.8 Port Options.)
1.5.8 Port B (I/O) Pins (PTB7–PTB0)
PTB7–PTB0 are general-purpose bidirectional I/O port pins. (See
Section 12. Input/Output Ports (I/O).) Each pin contains a software
configurable pullup device when the pin is configured as an input. (See
12.8 Port Options.)
1.5.9 Port C I/O Pins (PTC7–PTC0)
PTC7–PTC0 are general-purpose bidirectional I/O port pins. (See
Section 12. Input/Output Ports (I/O).) Port C pins are software
configurable to be LED direct drive ports. Each pin contains a software
configurable pullup device when the pin is configured as an input. (See
12.8 Port Options.)
NOTE:
On the 42-lead SDIP package the PTC7–PTC5 pads are not bonded
out. Set these ports to output to avoid floating inputs.
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PTD7/KBD7–PTD0/KBD0 are general-purpose bidirectional I/O port
pins. (See Section 12. Input/Output Ports (I/O).) Any or all of the port
D pins can be programmed to serve as external interrupt pins. (See
Section 15. Keyboard Interrupt Module (KBI).)
Port E is a 7-bit special function port that shares three of its pins with the
timer interface module. (Section 11. Timer Interface Module (TIM) and
Section 12. Input/Output Ports (I/O).)
NOTE:
On the 42-lead SDIP package the port E pads are not bonded out. Set
these ports to output to avoid floating inputs.
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1.5.11 Port E I/O Pins (PTE6–PTE3 and PTE2/TCH1, PTE1/TCH0, PTE0/TCLK)
A G R E E M E N T
1.5.10 Port D I/O Pins (PTD7/KBD7–PTD0/KBD0)
R E Q U I R E D
General Description
Pin Assignments
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A G R E E M E N T
R E Q U I R E D
General Description
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2.1 Contents
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.3
Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.4
Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .37
2.5
Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.6
Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
2.2 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory
map, shown in Figure 2-1, includes:
•
Eight Kbytes of read-only memory (ROM)
•
368 bytes of RAM
•
16 bytes of user-defined vectors
•
240 bytes of monitor ROM
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A G R E E M E N T
Section 2. Memory Map
N O N - D I S C L O S U R E
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R E Q U I R E D
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Freescale Semiconductor, Inc.
R E Q U I R E D
Memory Map
N O N - D I S C L O S U R E
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A G R E E M E N T
$0000
↓
$003F
$0040
↓
$01AF
$01B0
↓
$DDFF
$DE00
↓
$FDFF
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
↓
$FE0B
$FE0C
$FE0D
$FE0E
$FE0F
$FE10
↓
$FEFF
$FF00
↓
$FFEF
$FFF0
↓
$FFFF
I/O REGISTERS, 64 BYTES
RAM, 368 BYTES
UNIMPLEMENTED 56,400 BYTES
ROM, 8,192 BYTES
BREAK STATUS REGISTER (BSR)
RESET STATUS REGISTER (RSR)
RESERVED
BREAK FLAG CONTROL REGISTER (BFCR)
INTERRUPT STATUS REGISTER 1 (INT1)
INTERRUPT STATUS REGISTER 2 (INT2)
RESERVED
RESERVED, 4 BYTES
BREAK ADDRESS HIGH REGISTER (BRKH)
BREAK ADDRESS LOW REGISTER (BRKL)
BREAK STATUS AND CONTROL REGISTER (BSCR)
RESERVED
MONITOR ROM, 240 BYTES
UNIMPLEMENTED, 240 BYTES
VECTORS, 16 BYTES
Figure 2-1. Memory Map
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•
$FE00 (break status register, BSR)
•
$FE01 (reset status register, RSR)
•
$FE03 (break flag control register, BFCR)
•
$FE04 (interrupt status register 1, INT1)
•
$FE05 (interrupt status register 2, INT2)
•
$FE0C and $FE0D (break address registers, BRKH and BRKL)
•
$FE0E (break status and control register, BSCR)
•
$FFFF (COP control register, COPCTL)
2.4 Unimplemented Memory Locations
Some addresses are unimplemented. Accessing an unimplemented
address can cause an illegal address reset if illegal address resets are
enabled. In the memory map and in the I/O register summary,
unimplemented addresses are shaded.
Some I/O bits are read-only: the write function is unimplemented. Writing
to a read-only I/O bit has no effect on MCU operation. In register figures,
the write function of read-only bits is shaded.
2.5 Reserved Memory Locations
Some addresses are reserved. Writing to a reserved address can have
unpredictable effects on MCU operation. In the memory map and in the
I/O register summary, reserved addresses are marked with the word
Reserved.
Some I/O bits are reserved. Writing to a reserved bit can have
unpredictable effects on MCU operation. In register figures, reserved
bits are marked with the letter R.
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Addresses $0000–$003F contain most of the control, status, and data
registers. Additional I/O registers have these addresses:
N O N - D I S C L O S U R E
2.3 Input/Output (I/O) Section
R E Q U I R E D
Memory Map
Input/Output (I/O) Section
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A G R E E M E N T
R E Q U I R E D
Memory Map
Addr.
Name
$0000
Read:
Port A Data Register
Write:
(PTA)
Reset:
$0001
$0002
$0003
$0004
$0005
$0006
$0007
Read:
Port B Data Register
Write:
(PTB)
Reset:
Read:
Port C Data Register
Write:
(PTC)
Reset:
Read:
Port D Data Register
Write:
(PTD)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTB2
PTB1
PTB0
PTC2
PTC1
PTC0
PTD2
PTD1
PTD0
Unaffected by Reset
PTB7
PTB6
PTB5
PTB4
PTB3
Unaffected by Reset
PTC7
PTC6
PTC5
PTC4
PTC3
Unaffected by Reset
PTD7
Read:
DDRA7
Data Direction Register A
Write:
(DDRA)
Reset:
0
Read:
DDRB7
Data Direction Register B
Write:
(DDRB)
Reset:
0
PTD6
PTD5
PTD4
PTD3
Unaffected by Reset
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
0
0
0
0
0
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
0
0
0
0
0
DDRC5
DDRC4
DDRC3
DDRC2
0
0
0
0
DDRD5
DDRD4
DDRD3
DDRD2
0
0
0
0
R
= Reserved
Read:
DDRC7 DDRC6
Data Direction Register C
Write:
(DDRC)
Reset:
0
0
Read:
DDRD7 DDRD6
Data Direction Register D
Write:
(DDRD)
Reset:
0
0
= Unimplemented
DDRA1 DDRA0
0
0
DDRB1 DDRB0
0
0
DDRC1 DDRC0
0
0
DDRD1 DDRD0
0
0
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 9)
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Name
Bit 7
$0008
Read:
Port E Data Register
Write:
(PTE)
Reset:
Unimplemented
$000A
Unimplemented
$000B
Unimplemented
$000C
$000D
$000E
$000F
$0010
$0011
4
3
2
1
Bit 0
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
Unaffected by Reset
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Data Direction Register E
Write:
(DDRE)
Reset:
Read:
Keyboard Status and Control
Write:
Register (KBSCR)
Reset:
0
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
0
0
0
0
0
0
0
0
0
0
KEYF
0
ACKK
0
Read:
KBIE7
Keyboard Interrupt Enable
Write:
Register (KBIER)
Reset:
0
Read:
Port Option Control Register
Write:
(POC)
Reset:
Read:
TIM Status and Control Register
Write:
(TSC)
Reset:
Unimplemented
5
IMASKK MODEK
0
0
0
0
0
KBIE6
KBIE5
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
0
0
0
0
0
PCP
PBP
PAP
0
0
0
0
0
0
0
PS2
PS1
PS0
0
0
0
0
0
1
TOIE
TSTOP
0
1
0
0
0
0
0
0
0
0
TOF
DDRE1 DDRE0
LDD
TRST
0
0
R
= Reserved
Read:
Write:
= Unimplemented
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 9)
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A G R E E M E N T
$0009
0
6
R E Q U I R E D
Addr.
N O N - D I S C L O S U R E
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Memory Map
Reserved Memory Locations
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A G R E E M E N T
R E Q U I R E D
Memory Map
Addr.
$0012
$0013
Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TIM Counter Register High
Write:
(TCNTH)
Reset:
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Read:
TIM Counter Register Low
Write:
(TCNTL)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Read:
TIM Counter Modulo Register High
$0014
Write:
(TMODH)
Reset:
Read:
TIM Counter Modulo Register Low
$0015
Write:
(TMODL)
Reset:
Read: CH0F
TIM Channel 0 Status and Control
$0016
Write:
0
Register (TSC0)
Reset:
0
$0017
$0018
Read:
TIM Channel 0 Register High
Write:
(TCH0H)
Reset:
Read:
TIM Channel 0 Register Low
Write:
(TCH0L)
Reset:
Bit 15
Indeterminate after Reset
Bit 7
$001A
5
4
3
Indeterminate after Reset
Read: CH1F
TIM Channel 1 Status and Control
$0019
Write:
0
Register (TSC1)
Reset:
0
Read:
TIM Channel 1 Register High
Write:
(TCH1H)
Reset:
6
Bit 15
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
14
13
12
11
10
9
Bit 8
Indeterminate after Reset
= Unimplemented
R
= Reserved
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 9)
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Read:
TIM Channel 1 Register Low
Write:
(TCH1L)
Reset:
$001C
Unimplemented
$001D
Unimplemented
$001E
$001F
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Indeterminate after Reset
Read:
Write:
Read:
Write:
Read:
IRQ Status and Control Register
Write:
(ISCR)
Reset:
Read:
Mask Option Register
Write:
(MOR)
Reset:
0
0
0
0
IRQF1
0
ACK1
IMASK1 MODE1
0
0
0
0
0
0
0
0
R
REGBP
R
ROMSEC
SSREC
COPRS
STOP
COPD
Unaffected by Reset
$0020
Read: UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
USB Endpoint 0 Data Register 0
Write: UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
(UE0D0)
Reset:
Indeterminate after Reset
$0021
Read: UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
USB Endpoint 0 Data Register 1
Write: UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
(UE0D1)
Reset:
Indeterminate after Reset
$0022
Read: UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
USB Endpoint 0 Data Register 2
Write: UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
(UE0D2)
Reset:
Indeterminate after Reset
$0023
Read: UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
USB Endpoint 0 Data Register 3
Write: UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
(UE0D3)
Reset:
Indeterminate after Reset
= Unimplemented
R
= Reserved
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 9)
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$001B
Name
N O N - D I S C L O S U R E
Addr.
R E Q U I R E D
Memory Map
Reserved Memory Locations
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A G R E E M E N T
R E Q U I R E D
Memory Map
Addr.
Name
Bit 7
6
5
4
3
2
1
Bit 0
$0024
Read: UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
USB Endpoint 0 Data Register 4
Write: UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
(UE0D4)
Reset:
Indeterminate after Reset
$0025
Read: UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
USB Endpoint 0 Data Register 5
Write: UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
(UE0D5)
Reset:
Indeterminate after Reset
$0026
Read: UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
USB Endpoint 0 Data Register 6
Write: UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
(UE0D6)
Reset:
Indeterminate after Reset
$0027
Read: UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
USB Endpoint 0 Data Register 7
Write: UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
(UE0D7)
Reset:
Indeterminate after Reset
Read:
USB Endpoint 1/2 Data Register 0
$0028
Write: UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
(UE1D0)
Reset:
Indeterminate after Reset
Read:
USB Endpoint 1/2 Data Register 1
$0029
Write: UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
(UE1D1)
Reset:
Indeterminate after Reset
Read:
USB Endpoint 1/2 Data Register 2
$002A
Write: UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
(UE1D2)
Reset:
Indeterminate after Reset
Read:
USB Endpoint 1/2 Data Register 3
$002B
Write: UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
(UE1D3)
Reset:
Indeterminate after Reset
Read:
USB Endpoint 1/2 Data Register 4
$002C
Write: UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
(UE1D4)
Reset:
Indeterminate after Reset
= Unimplemented
R
= Reserved
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 9)
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Bit 7
6
5
4
3
2
1
Bit 0
Read:
USB Endpoint 1/2 Data Register 5
$002D
Write: UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
(UE1D5)
Reset:
Indeterminate after Reset
Freescale Semiconductor, Inc...
Read:
USB Endpoint 1/2 Data Register 6
$002E
Write: UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
(UE1D6)
Reset:
Indeterminate after Reset
Read:
USB Endpoint 1/2 Data Register 7
$002F
Write: UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
(UE1D7)
Reset:
Indeterminate after Reset
$0030
Unimplemented
↓
Unimplemented
$0036
Unimplemented
$0037
$0038
$0039
$003A
Read:
Write:
Read:
Write:
Read:
Write:
Read:
0
0
USB Control Register 2
Write: RSTFR TX1STR
(UCR2)
Reset:
0
0
TX1ST
0
0
0
0
0
UADD6
UADD5
UADD4
UADD3
UADD2
0
0
0
0
0
Read: TXD0F
USB Interrupt Register 0
Write:
(UIR0)
Reset:
0
RXD0F
RSTF
SUSPND
TXD0IE
RXD0IE
0
0
0
0
0
Read: TXD1F
USB Interrupt Register 1
Write:
(UIR1)
Reset:
0
EOPF
RESUMF
0
TXD1IE
EOPIE
0
0
0
R
= Reserved
Read:
USBEN
USB Address Register
Write:
(UADDR)
Reset:
0
RESUMFR
0
0
= Unimplemented
ENABLE2 ENABLE1 STALL2 STALL1
0
0
UADD1 UADD0
0
0
0
0
TXD0FR RXD0FR
0
0
0
0
TXD1FR EOPFR
0
0
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 9)
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A G R E E M E N T
Name
N O N - D I S C L O S U R E
Addr.
R E Q U I R E D
Memory Map
Reserved Memory Locations
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Memory Map
Addr.
$003B
$003C
$003D
Name
Bit 7
Read:
T0SEQ
USB Control Register 0
Write:
(UCR0)
Reset:
0
Read: RSEQ
USB Status Register
Write:
(USR)
Reset:
X
$003F
Unimplemented
$FE00
Read:
Break Status Register
Write:
(BSR)
Reset:
$FE03
4
STALL0
TX0E
RX0E
0
0
0
0
2
1
Bit 0
TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0
0
0
0
0
FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0
0
0
0
0
0
SETUP
RPSIZ3
RPSIZ2
X
X
X
X
X
R
R
SBSW
R
RPSIZ1 RPSIZ0
Write:
Read:
Write:
Read:
Reset Status Register
Write:
(RSR)
POR:
Reserved
TX1E
3
Read:
Unimplemented
$FE02
5
Read:
T1SEQ ENDADD
USB Control Register 1
Write:
(UCR1)
Reset:
0
0
$003E
$FE01
6
Read:
Write:
R
R
R
R
0
POR
PIN
COP
ILOP
ILAD
USB
0
0
1
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
= Reserved
Read:
BCFE
Break Flag Control Register
Write:
(BFCR)
Reset:
0
= Unimplemented
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 9)
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$FE05
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Interrupt Status Register 1
Write:
(INT1)
Reset:
IF6
IF5
IF4
IF3
IF2
IF1
0
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Read:
Interrupt Status Register 2
Write:
(INT2)
Reset:
IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
R
= Reserved
$FE06
Reserved
$FE07
Unimplemented
$FE08
Unimplemented
$FE09
Unimplemented
$FE0A
Unimplemented
$FE0B
Unimplemented
$FE0C
$FE0D
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
A G R E E M E N T
$FE04
Name
Read:
Write:
Read:
Write:
Read:
Break Address Register High
Write:
(BRKH)
Reset:
Read:
Break Address Register Low
Write:
(BRKL)
Reset:
= Unimplemented
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 9)
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R E Q U I R E D
Memory Map
Reserved Memory Locations
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Addr.
Name
Bit 7
Read:
BRKE
Break Status and Control Register
$FE0E
Write:
(BRKSCR)
Reset:
0
$FFFF
Read:
COP Control Register
Write:
(COPCTL)
Reset:
6
BRKA
0
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
Low Byte of Reset Vector
Writing Clears COP Counter (Any Value)
Unaffected by Reset
= Unimplemented
R
= Reserved
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 9)
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Priority
High
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Low
Address
Vector
$FFF0
Keyboard Vector (High)
$FFF1
Keyboard Vector (Low)
$FFF2
TIM Overflow Vector (High)
$FFF3
TIM Overflow Vector (Low)
$FFF4
TIM Channel 1 Vector (High)
$FFF5
TIM Channel 1 Vector (Low)
$FFF6
TIM Channel 0 Vector (High)
$FFF7
TIM Channel 0 Vector (Low)
$FFF8
USB Vector (High)
$FFF9
USB Vector (Low)
$FFFA
IRQ1 Vector (High)
$FFFB
IRQ1 Vector (Low)
$FFFC
SWI Vector (High)
$FFFD
SWI Vector (Low)
$FFFE
Reset Vector (High)
$FFFF
Reset Vector (Low)
2.6 Monitor ROM
The 240 bytes at addresses $FE10–$FEFF are reserved ROM
addresses that contain the instructions for the monitor functions. (See
Section 10. Monitor ROM (MON).)
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A G R E E M E N T
Table 2-1. Vector Addresses
N O N - D I S C L O S U R E
Table 2-1 is a list of vector locations.
R E Q U I R E D
Memory Map
Monitor ROM
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R E Q U I R E D
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3.1 Contents
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.2 Introduction
This section describes the 368 bytes of random-access memory (RAM).
3.3 Functional Description
Addresses $0040–$01AF are RAM locations. The location of the stack
RAM is programmable. The 16-bit stack pointer allows the stack to be
anywhere in the 64-Kbyte memory space.
NOTE:
For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 192 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF, direct addressing mode instructions can
access efficiently all page zero RAM locations. Page zero RAM,
therefore, provides ideal locations for frequently accessed global
variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
NOTE:
For M6805 Family compatibility, the H register is not stacked.
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Section 3. Random-Access Memory (RAM)
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During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
NOTE:
Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking
operation.
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A G R E E M E N T
R E Q U I R E D
Random-Access Memory (RAM)
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4.1 Contents
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.2 Introduction
This section describes the 8 KBytes of read-only memory (ROM) and 16
bytes of user vectors.
4.3 Functional Description
An unprogrammed or erased location reads as $00. These addresses
are user ROM locations:
NOTE:
•
$DE00–$FDFF
•
$FFF0–$FFFF (These locations are reserved for user-defined
interrupt and reset vectors.)
A security feature prevents viewing of the ROM contents.1
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the ROM contents difficult for unauthorized users.
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A G R E E M E N T
Section 4. Read-Only Memory (ROM)
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Read-Only Memory (ROM)
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5.1 Contents
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
5.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
5.2 Introduction
This section describes the mask options and the mask option register
(MOR). The mask options are hard-wired connections specified at the
same time as the ROM code, which allow the user to customize the
MCU. The MOR controls the enable or disable of the following functions:
•
USB regulator bypass
•
ROM security1
•
Stop mode recovery time (32 or 4096 CGMXCLK cycles)
•
COP timeout period (218 – 24 or 213 – 24 CGMXCLK cycles)
•
STOP instruction
•
Operation of the computer operating properly module (COP)
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the ROM difficult for unauthorized users.
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A G R E E M E N T
Section 5. Mask Option Register (MOR)
N O N - D I S C L O S U R E
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R E Q U I R E D
Mask Option Register (MOR)
5.3 Functional Description
Address:
Read:
$001F
Bit 7
6
5
4
3
2
1
Bit 0
R
REGBP
R
ROMSEC
SSREC
COPRS
STOP
COPD
Write:
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A G R E E M E N T
Reset:
Unaffected by Reset
= Unimplemented
Figure 5-1. Mask Option Register (MOR)
NOTE:
Writing to a reserved address can have unpredictable effects on MCU
operation.
REGBP — Regulator Bypass Bit
The REGBP causes the on-chip regulator to pass VDDREG to the
REGOUT pin.
1 = VDDREG voltage applied to the REGOUT pin.
0 = Regulator output drives 3.3 volts on REGOUT pin.
NOTE:
The bypass mode is reserved for transceiver testing and should not be
used in normal operation.
ROMSEC — ROM Security Bit
ROMSEC enables the ROM security feature. Setting the ROMSEC bit
prevents reading of the ROM contents. Access to the ROM is denied
to unauthorized users of customer specified software.
1 = ROM security enabled
0 = ROM security disabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
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NOTE:
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS. (See
Section 13. Computer Operating Properly (COP).)
1 = COP timeout period = 213 – 24 CGMXCLK cycles
0 = COP timeout period = 218 – 24 CGMXCLK cycles
R E Q U I R E D
Mask Option Register (MOR)
Functional Description
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
N O N - D I S C L O S U R E
COPD disables the COP module. (See Section 13. Computer
Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
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STOP — STOP Instruction Enable Bit
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A G R E E M E N T
R E Q U I R E D
Mask Option Register (MOR)
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6.1 Contents
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
6.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
6.4
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.4.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.4.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
6.4.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
6.4.4
Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
6.4.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .63
6.5
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .65
6.6
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
6.7
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.2 Introduction
This section describes the central processor unit (CPU). The M68HC08
CPU is an enhanced and fully object-code-compatible version of the
M68HC05 CPU. The CPU08 Reference Manual (Motorola document
number CPU08RM/AD) contains a description of the CPU instruction
set, addressing modes, and architecture.
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A G R E E M E N T
Section 6. Central Processor Unit (CPU)
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6.3 Features
Features of the CPU include:
•
Fully Upward, Object-Code Compatibility with M68HC05 Family
•
16-Bit Stack Pointer with Stack Manipulation Instructions
•
16-Bit Index Register with X-Register Manipulation Instructions
•
8-MHz CPU Internal Bus Frequency
•
64-Kbyte Program/Data Memory Space
•
16 Addressing Modes
•
Memory-to-Memory Data Moves Without Using Accumulator
•
Fast 8-Bit by 8-Bit Multiply and 16-Bit by 8-Bit Divide Instructions
•
Enhanced Binary-Coded Decimal (BCD) Data Handling
•
Modular Architecture with Expandable Internal Bus Definition
for Extension of Addressing Range Beyond 64 Kbytes
•
Low-Power Stop Mode and Wait Mode
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6.4 CPU Registers
Figure 6-1 shows the five CPU registers. CPU registers are not part of
the memory map.
7
0
ACCUMULATOR (A)
15
0
H
X
INDEX REGISTER (H:X)
0
A G R E E M E N T
STACK POINTER (SP)
0
15
PROGRAM COUNTER (PC)
7
0
V 1 1 H I N Z C
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU Registers
6.4.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by Reset
Figure 6-2. Accumulator (A)
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15
Bit 7
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CPU Registers
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6.4.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
The index register can serve also as a temporary data storage
location.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
Read:
Write:
Reset:
X = Indeterminate
Figure 6-3. Index Register (H:X)
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In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
Figure 6-4. Stack Pointer (SP)
NOTE:
The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct
address (page zero) space. For correct operation, the stack pointer must
point only to RAM locations.
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The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction also sets the least
significant byte (LSB) to $FF but does not affect the most significant byte
(MSB). The stack pointer decrements as data is pushed onto the stack
and increments as data is pulled from the stack.
N O N - D I S C L O S U R E
6.4.3 Stack Pointer
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6.4.4 Program Counter
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
Read:
Write:
Reset:
Loaded with Vector from $FFFE and $FFFF
Figure 6-5. Program Counter (PC)
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6.4.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
Bit 7
6
5
4
3
2
1
Bit 0
V
1
1
H
I
N
Z
C
X
1
1
X
1
X
X
X
Read:
R E Q U I R E D
Central Processor Unit (CPU)
CPU Registers
Reset:
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
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Write:
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an ADD or ADC operation. The halfcarry flag is required for binary-coded decimal (BCD) arithmetic
operations. The DAA instruction uses the states of the H and C flags
to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
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H — Half-Carry Flag
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A G R E E M E N T
R E Q U I R E D
Central Processor Unit (CPU)
NOTE:
To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can only be cleared by the clear
interrupt (CLI) mask software instruction.
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting
bit 7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
General Release Specification
MC68HC08KL8 — Rev. 2.0
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
The ALU performs the arithmetic and logic operations defined by the
instruction set.
6.6 Instruction Set Summary
Table 6-1 provides a summary of the M68HC08 instruction set.
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
Description
V H I N Z C
A ← (A) + (M) + (C)
Add with Carry
IMM
DIR
EXT
↕ ↕ – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
A9
B9
C9
D9
E9
F9
9EE9
9ED9
ii
dd
hh ll
ee ff
ff
IMM
DIR
EXT
↕ ↕ – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
AB
BB
CB
DB
EB
FB
9EEB
9EDB
ii
dd
hh ll
ee ff
ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
Add without Carry
AIS #opr
Add Immediate Value (Signed) to SP
SP ← (SP) + (16 « M)
– – – – – – IMM
AIX #opr
Add Immediate Value (Signed) to H:X
H:X ← (H:X) + (16 « M)
A ← (A) & (M)
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
A ← (A) + (M)
Logical AND
Arithmetic Shift Left
(Same as LSL)
C
0
b7
b0
ff
ee ff
Cycles
Operation
Effect on
CCR
Opcode
Source
Form
Operand
Table 6-1. Instruction Set Summary
Address
Mode
Freescale Semiconductor, Inc...
Refer to the CPU08 Reference Manual (Motorola document number
CPU08RM/AD) for a description of the instructions and addressing
modes and more details about the CPU’s architecture.
2
3
4
4
3
2
4
5
ff
ee ff
2
3
4
4
3
2
4
5
A7
ii
2
– – – – – – IMM
AF
ii
2
IMM
DIR
EXT
0 – – ↕ ↕ – IX2
IX1
IX
SP1
SP2
A4
B4
C4
D4
E4
F4
9EE4
9ED4
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
DIR
INH
↕ – – ↕ ↕ ↕ INH
IX1
IX
SP1
38 dd
48
58
68 ff
78
9E68 ff
MC68HC08KL8 — Rev. 2.0
ff
ee ff
4
1
1
4
3
5
General Release Specification
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
N O N - D I S C L O S U R E
6.5 Arithmetic/Logic Unit (ALU)
A G R E E M E N T
R E Q U I R E D
Central Processor Unit (CPU)
Arithmetic/Logic Unit (ALU)
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
Description
V H I N Z C
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
Arithmetic Shift Right
BCC rel
Branch if Carry Bit Clear
C
b7
b0
PC ← (PC) + 2 + rel ? (C) = 0
Mn ← 0
DIR
INH
↕ – – ↕ ↕ ↕ INH
IX1
IX
SP1
37 dd
47
57
67 ff
77
9E67 ff
Cycles
Operation
Effect on
CCR
Opcode
Source
Form
Operand
Table 6-1. Instruction Set Summary (Continued)
Address
Mode
R E Q U I R E D
Central Processor Unit (CPU)
4
1
1
4
3
5
– – – – – – REL
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
(b3)
– – – – – – DIR
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BCLR n, opr
Clear Bit n in M
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC ← (PC) + 2 + rel ? (C) = 1
– – – – – – REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? (Z) = 1
– – – – – – REL
27
rr
3
BGE opr
Branch if Greater Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) = 0
– – – – – – REL
90
rr
3
BGT opr
Branch if Greater Than (Signed
Operands)
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0 – – – – – – REL
92
rr
3
BHCC rel
Branch if Half Carry Bit Clear
3
BHCS rel
Branch if Half Carry Bit Set
BHI rel
Branch if Higher
BHS rel
PC ← (PC) + 2 + rel ? (H) = 0
– – – – – – REL
28
rr
PC ← (PC) + 2 + rel ? (H) = 1
– – – – – – REL
29
rr
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
– – – – – – REL
22
rr
3
Branch if Higher or Same
(Same as BCC)
PC ← (PC) + 2 + rel ? (C) = 0
– – – – – – REL
24
rr
3
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
– – – – – – REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
– – – – – – REL
2E
rr
3
(A) & (M)
IMM
DIR
EXT
0 – – ↕ ↕ – IX2
IX1
IX
SP1
SP2
A5
B5
C5
D5
E5
F5
9EE5
9ED5
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
93
rr
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
Bit Test
BLE opr
Branch if Less Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1 – – – – – – REL
3
BLO rel
Branch if Lower (Same as BCS)
PC ← (PC) + 2 + rel ? (C) = 1
– – – – – – REL
25
rr
3
BLS rel
Branch if Lower or Same
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
– – – – – – REL
23
rr
3
BLT opr
Branch if Less Than (Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) =1
– – – – – – REL
91
rr
3
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? (I) = 0
– – – – – – REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? (N) = 1
– – – – – – REL
2B
rr
3
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? (I) = 1
– – – – – – REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? (Z) = 0
– – – – – – REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? (N) = 0
– – – – – – REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel
– – – – – – REL
20
rr
3
General Release Specification
MC68HC08KL8 — Rev. 2.0
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
– – – – – – REL
21
rr
3
PC ← (PC) + 3 + rel ? (Mn) = 1
DIR (b0)
DIR (b1)
DIR (b2)
(b3)
– – – – – ↕ DIR
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
(b3)
– – – – – – DIR
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
– – – – – – REL
AD
rr
4
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
DIR
IMM
– – – – – – IMM
IX1+
IX+
SP1
31
41
51
61
71
9E61
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
4
6
PC ← (PC) + 2
Branch Never
BRSET n,opr,rel Branch if Bit n in M Set
BSET n,opr
Set Bit n in M
BSR rel
Branch to Subroutine
PC ← (PC) + 3 + rel ? (Mn) = 0
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel Compare and Branch if Equal
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
CLC
Clear Carry Bit
C←0
– – – – – 0 INH
98
1
CLI
Clear Interrupt Mask
I←0
– – 0 – – – INH
9A
2
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
INH
0 – – 0 1 – INH
IX1
IX
SP1
3F dd
4F
5F
8C
6F ff
7F
9E6F ff
3
1
1
1
3
2
4
(A) – (M)
IMM
DIR
EXT
↕ – – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
A1
B1
C1
D1
E1
F1
9EE1
9ED1
2
3
4
4
3
2
4
5
DIR
INH
0 – – ↕ ↕ 1 INH
IX1
IX
SP1
33 dd
43
53
63 ff
73
9E63 ff
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
Clear
Compare A with M
Complement (One’s Complement)
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
MC68HC08KL8 — Rev. 2.0
ii
dd
hh ll
ee ff
ff
ff
ee ff
4
1
1
4
3
5
General Release Specification
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
01
03
05
07
09
0B
0D
0F
N O N - D I S C L O S U R E
Cycles
Freescale Semiconductor, Inc...
DIR (b0)
DIR (b1)
DIR (b2)
(b3)
– – – – – ↕ DIR
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
Description
V H I N Z C
BRCLR n,opr,rel Branch if Bit n in M Clear
BRN rel
Operand
Operation
Effect on
CCR
Address
Mode
Source
Form
Opcode
Table 6-1. Instruction Set Summary (Continued)
R E Q U I R E D
Central Processor Unit (CPU)
Instruction Set Summary
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Compare H:X with M
Compare X with M
DAA
Decimal Adjust A
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
Decrement
DIV
Divide
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
↕ – – ↕ ↕ ↕ IMM
DIR
65
75
ii ii+1
dd
3
4
(X) – (M)
IMM
DIR
EXT
↕ – – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
A3
B3
C3
D3
E3
F3
9EE3
9ED3
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
U – – ↕ ↕ ↕ INH
72
(A)10
DBNZ opr,rel
DBNZA rel
DBNZX rel
Decrement and Branch if Not Zero
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
(H:X) – (M:M + 1)
Description
V H I N Z C
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
Cycles
CPHX #opr
CPHX opr
Operation
Effect on
CCR
Exclusive OR M with A
Increment
Jump
Jump to Subroutine
Load A from M
Address
Mode
Source
Form
Operand
Table 6-1. Instruction Set Summary (Continued)
Opcode
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Central Processor Unit (CPU)
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0
DIR
PC ← (PC) + 2 + rel ? (result) ≠ 0
INH
PC ← (PC) + 2 + rel ? (result) ≠ 0
– – – – – – INH
PC ← (PC) + 3 + rel ? (result) ≠ 0
IX1
PC ← (PC) + 2 + rel ? (result) ≠ 0
IX
PC ← (PC) + 4 + rel ? (result) ≠ 0
SP1
3B
4B
5B
6B
7B
9E6B
ff
ee ff
2
dd rr
rr
rr
ff rr
rr
ff rr
5
3
3
5
4
6
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
↕ – – ↕ ↕ – INH
IX1
IX
SP1
A ← (H:A)/(X)
H ← Remainder
– – – – ↕ ↕ INH
52
A ← (A ⊕ M)
IMM
DIR
EXT
0 – – ↕ ↕ – IX2
IX1
IX
SP1
SP2
A8
B8
C8
D8
E8
F8
9EE8
9ED8
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
↕ – – ↕ ↕ – INH
IX1
IX
SP1
3C dd
4C
5C
6C ff
7C
9E6C ff
PC ← Jump Address
DIR
EXT
– – – – – – IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
2
3
4
3
2
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
DIR
EXT
– – – – – – IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
4
5
6
5
4
A ← (M)
IMM
DIR
EXT
0 – – ↕ ↕ – IX2
IX1
IX
SP1
SP2
A6
B6
C6
D6
E6
F6
9EE6
9ED6
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
General Release Specification
3A dd
4A
5A
6A ff
7A
9E6A ff
4
1
1
4
3
5
7
ii
dd
hh ll
ee ff
ff
ff
ee ff
ff
ee ff
2
3
4
4
3
2
4
5
4
1
1
4
3
5
MC68HC08KL8 — Rev. 2.0
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
Load H:X from M
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
Logical Shift Right
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
Move
MUL
Unsigned multiply
Cycles
H:X ← (M:M + 1)
0 – – ↕ ↕ – IMM
DIR
45
55
X ← (M)
IMM
DIR
EXT
0 – – ↕ ↕ – IX2
IX1
IX
SP1
SP2
AE
BE
CE
DE
EE
FE
9EEE
9EDE
0
DIR
INH
↕ – – ↕ ↕ ↕ INH
IX1
IX
SP1
38 dd
48
58
68 ff
78
9E68 ff
4
1
1
4
3
5
C
DIR
INH
↕ – – 0 ↕ ↕ INH
IX1
IX
SP1
34 dd
44
54
64 ff
74
9E64 ff
4
1
1
4
3
5
Load X from M
Logical Shift Left
(Same as ASL)
Operand
V H I N Z C
C
b7
b0
0
b7
b0
H:X ← (H:X) + 1 (IX+D, DIX+)
DD
0 – – ↕ ↕ – DIX+
IMD
IX+D
4E
5E
6E
7E
X:A ← (X) × (A)
– 0 – – – 0 INH
42
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
↕ – – ↕ ↕ ↕ INH
IX1
IX
SP1
(M)Destination ← (M)Source
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
Negate (Two’s Complement)
NOP
No Operation
None
– – – – – – INH
NSA
Nibble Swap A
A ← (A[3:0]:A[7:4])
– – – – – – INH
62
A ← (A) | (M)
IMM
DIR
EXT
0 – – ↕ ↕ – IX2
IX1
IX
SP1
SP2
AA
BA
CA
DA
EA
FA
9EEA
9EDA
– – – – – – INH
87
ii jj
dd
3
4
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
ff
ee ff
dd dd
dd
ii dd
dd
5
4
4
4
5
30 dd
40
50
60 ff
70
9E60 ff
9D
4
1
1
4
3
5
1
3
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
Inclusive OR A and M
PSHA
Push A onto Stack
Push (A); SP ← (SP) – 1
PSHH
Push H onto Stack
Push (H); SP ← (SP) – 1
– – – – – – INH
8B
2
PSHX
Push X onto Stack
Push (X); SP ← (SP) – 1
– – – – – – INH
89
2
PULA
Pull A from Stack
SP ← (SP + 1); Pull (A)
– – – – – – INH
86
2
PULH
Pull H from Stack
SP ← (SP + 1); Pull (H)
– – – – – – INH
8A
2
PULX
Pull X from Stack
SP ← (SP + 1); Pull (X)
– – – – – – INH
88
2
C
DIR
INH
↕ – – ↕ ↕ ↕ INH
IX1
IX
SP1
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
Rotate Left through Carry
b7
b0
MC68HC08KL8 — Rev. 2.0
ii
dd
hh ll
ee ff
ff
ff
ee ff
39 dd
49
59
69 ff
79
9E69 ff
2
3
4
4
3
2
4
5
2
4
1
1
4
3
5
General Release Specification
Central Processor Unit (CPU)
For More Information On This Product,
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A G R E E M E N T
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
Description
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
LDHX #opr
LDHX opr
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary (Continued)
R E Q U I R E D
Central Processor Unit (CPU)
Instruction Set Summary
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
Description
V H I N Z C
Cycles
Operation
Effect on
CCR
Operand
Source
Form
Opcode
Table 6-1. Instruction Set Summary (Continued)
Address
Mode
R E Q U I R E D
Central Processor Unit (CPU)
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
Rotate Right through Carry
RSP
Reset Stack Pointer
SP ← $FF
– – – – – – INH
9C
1
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕ ↕ ↕ ↕ ↕ ↕ INH
80
7
RTS
Return from Subroutine
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
– – – – – – INH
81
4
A ← (A) – (M) – (C)
IMM
DIR
EXT
↕ – – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
A2
B2
C2
D2
E2
F2
9EE2
9ED2
C
b7
b0
DIR
INH
↕ – – ↕ ↕ ↕ INH
IX1
IX
SP1
36 dd
46
56
66 ff
76
9E66 ff
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
Subtract with Carry
SEC
Set Carry Bit
C←1
– – – – – 1 INH
99
SEI
Set Interrupt Mask
I←1
– – 1 – – – INH
9B
M ← (A)
DIR
EXT
IX2
0 – – ↕ ↕ – IX1
IX
SP1
SP2
B7
C7
D7
E7
F7
9EE7
9ED7
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
STHX opr
Store H:X in M
STOP
Enable IRQ Pin; Stop Oscillator
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
Store X in M
Subtract
ii
dd
hh ll
ee ff
ff
ff
ee ff
4
1
1
4
3
5
2
3
4
4
3
2
4
5
1
2
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
(M:M + 1) ← (H:X)
0 – – ↕ ↕ – DIR
35
I ← 0; Stop Oscillator
– – 0 – – – INH
8E
M ← (X)
DIR
EXT
IX2
0 – – ↕ ↕ – IX1
IX
SP1
SP2
BF
CF
DF
EF
FF
9EEF
9EDF
dd
hh ll
ee ff
ff
IMM
DIR
EXT
↕ – – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
A0
B0
C0
D0
E0
F0
9EE0
9ED0
ii
dd
hh ll
ee ff
ff
– – 1 – – – INH
83
9
↕ ↕ ↕ ↕ ↕ ↕ INH
84
2
A ← (A) – (M)
SWI
Software Interrupt
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
Transfer A to CCR
CCR ← (A)
General Release Specification
dd
4
1
ff
ee ff
ff
ee ff
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
MC68HC08KL8 — Rev. 2.0
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
TPA
Transfer CCR to A
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
Test for Negative or Zero
TSX
Transfer SP to H:X
TXA
Transfer X to A
TXS
Transfer H:X to SP
Cycles
X ← (A)
– – – – – – INH
A ← (CCR)
– – – – – – INH
(A) – $00 or (X) – $00 or (M) – $00
DIR
INH
0 – – ↕ ↕ – INH
IX1
IX
SP1
H:X ← (SP) + 1
– – – – – – INH
95
A ← (X)
– – – – – – INH
9F
1
(SP) ← (H:X) – 1
– – – – – – INH
94
2
Accumulator
Carry/borrow bit
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct to direct addressing mode
Direct addressing mode
Direct to indexed with post increment addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate source to direct destination addressing mode
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
Indexed with post increment to direct addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
n
opr
PC
PCH
PCL
REL
rel
rr
SP1
SP2
SP
U
V
X
Z
&
|
⊕
()
–( )
#
«
←
?
:
↕
—
97
1
85
1
3D dd
4D
5D
6D ff
7D
9E6D ff
3
1
1
3
2
4
2
Any bit
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer, 8-bit offset addressing mode
Stack pointer 16-bit offset addressing mode
Stack pointer
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Immediate value
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
6.7 Opcode Map
See Table 6-2.
MC68HC08KL8 — Rev. 2.0
General Release Specification
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
Transfer A to X
Operand
V H I N Z C
TAX
A
C
CCR
dd
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
H
H
hh ll
I
ii
IMD
IMM
INH
IX
IX+
IX+D
IX1
IX1+
IX2
M
N
Description
Opcode
Operation
Effect on
CCR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary (Continued)
R E Q U I R E D
Central Processor Unit (CPU)
Opcode Map
General Release Specification
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
5
BRSET0
3 DIR
5
BRCLR0
3 DIR
5
BRSET1
3 DIR
5
BRCLR1
3 DIR
5
BRSET2
3 DIR
5
BRCLR2
3 DIR
5
BRSET3
3 DIR
5
BRCLR3
3 DIR
5
BRSET4
3 DIR
5
BRCLR4
3 DIR
5
BRSET5
3 DIR
5
BRCLR5
3 DIR
5
BRSET6
3 DIR
5
BRCLR6
3 DIR
5
BRSET7
3 DIR
5
BRCLR7
3 DIR
0
4
BSET0
2 DIR
4
BCLR0
2 DIR
4
BSET1
2 DIR
4
BCLR1
2 DIR
4
BSET2
2 DIR
4
BCLR2
2 DIR
4
BSET3
2 DIR
4
BCLR3
2 DIR
4
BSET4
2 DIR
4
BCLR4
2 DIR
4
BSET5
2 DIR
4
BCLR5
2 DIR
4
BSET6
2 DIR
4
BCLR6
2 DIR
4
BSET7
2 DIR
4
BCLR7
2 DIR
1
3
BRA
REL
3
BRN
2 REL
3
BHI
2 REL
3
BLS
2 REL
3
BCC
2 REL
3
BCS
2 REL
3
BNE
2 REL
3
BEQ
2 REL
3
BHCC
2 REL
3
BHCS
2 REL
3
BPL
2 REL
3
BMI
2 REL
3
BMC
2 REL
3
BMS
2 REL
3
BIL
2 REL
3
BIH
2 REL
2
2
Branch
REL
4
INH
1
NEGX
1 INH
4
CBEQX
3 IMM
7
DIV
1 INH
1
COMX
1 INH
1
LSRX
1 INH
4
LDHX
2 DIR
1
RORX
1 INH
1
ASRX
1 INH
1
LSLX
1 INH
1
ROLX
1 INH
1
DECX
1 INH
3
DBNZX
2 INH
1
INCX
1 INH
1
TSTX
1 INH
4
MOV
2 DIX+
1
CLRX
1 INH
5
4
NEG
IX1
5
CBEQ
3 IX1+
3
NSA
1 INH
4
COM
2 IX1
4
LSR
2 IX1
3
CPHX
3 IMM
4
ROR
2 IX1
4
ASR
2 IX1
4
LSL
2 IX1
4
ROL
2 IX1
4
DEC
2 IX1
5
DBNZ
3 IX1
4
INC
2 IX1
3
TST
2 IX1
4
MOV
3 IMD
3
CLR
2 IX1
2
6
Read-Modify-Write
INH
IX1
7
IX
9
3
7
BGE
RTI
INH 2 REL
3
4
BLT
RTS
1 INH 2 REL
3
BGT
2 REL
3
9
BLE
SWI
1 INH 2 REL
2
2
TXS
TAP
1 INH 1 INH
2
1
TSX
TPA
1 INH 1 INH
2
PULA
1 INH
2
1
PSHA
TAX
1 INH 1 INH
2
1
CLC
PULX
1 INH 1 INH
1
2
SEC
PSHX
1 INH 1 INH
2
2
CLI
PULH
1 INH 1 INH
2
2
PSHH
SEI
1 INH 1 INH
1
1
CLRH
RSP
1 INH 1 INH
1
NOP
1 INH
1
STOP
*
1 INH
1
1
WAIT
TXA
1 INH 1 INH
1
8
Control
INH
INH
2
B
DIR
MSB
0
LSB
3
SUB
DIR
3
CMP
2 DIR
3
SBC
2 DIR
3
CPX
2 DIR
3
AND
2 DIR
3
BIT
2 DIR
3
LDA
2 DIR
3
STA
2 DIR
3
EOR
2 DIR
3
ADC
2 DIR
3
ORA
2 DIR
3
ADD
2 DIR
2
JMP
2 DIR
4
4
JSR
BSR
2 REL 2 DIR
3
2
LDX
LDX
2 IMM 2 DIR
2
3
AIX
STX
2 IMM 2 DIR
2
SUB
IMM
2
CMP
2 IMM
2
SBC
2 IMM
2
CPX
2 IMM
2
AND
2 IMM
2
BIT
2 IMM
2
LDA
2 IMM
2
AIS
2 IMM
2
EOR
2 IMM
2
ADC
2 IMM
2
ORA
2 IMM
2
ADD
2 IMM
2
A
IMM
Low Byte of Opcode in Hexadecimal
3
5
NEG
NEG
SP1 1 IX
4
6
CBEQ
CBEQ
4 SP1 2 IX+
2
DAA
1 INH
3
5
COM
COM
3 SP1 1 IX
3
5
LSR
LSR
3 SP1 1 IX
4
CPHX
2 DIR
3
5
ROR
ROR
3 SP1 1 IX
5
3
ASR
ASR
3 SP1 1 IX
5
3
LSL
LSL
3 SP1 1 IX
3
5
ROL
ROL
3 SP1 1 IX
3
5
DEC
DEC
3 SP1 1 IX
6
4
DBNZ
DBNZ
4 SP1 2 IX
5
3
INC
INC
3 SP1 1 IX
2
4
TST
TST
3 SP1 1 IX
4
MOV
2 IX+D
4
2
CLR
CLR
3 SP1 1 IX
3
9E6
SP1
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
1
4
NEGA
NEG
DIR 1 INH
4
5
CBEQ CBEQA
3 DIR 3 IMM
5
MUL
1 INH
1
4
COMA
COM
2 DIR 1 INH
1
4
LSRA
LSR
2 DIR 1 INH
3
4
LDHX
STHX
2 DIR 3 IMM
1
4
RORA
ROR
2 DIR 1 INH
1
4
ASRA
ASR
2 DIR 1 INH
4
1
LSL
LSLA
2 DIR 1 INH
1
4
ROLA
ROL
2 DIR 1 INH
1
4
DECA
DEC
2 DIR 1 INH
5
3
DBNZ DBNZA
3 DIR 2 INH
4
1
INC
INCA
2 DIR 1 INH
1
3
TSTA
TST
2 DIR 1 INH
5
MOV
3 DD
1
3
CLRA
CLR
2 DIR 1 INH
2
3
DIR
INH Inherent
REL Relative
IMM Immediate
IX
Indexed, No Offset
DIR Direct
IX1 Indexed, 8-Bit Offset
EXT Extended
IX2 Indexed, 16-Bit Offset
DD Direct-Direct
IMD Immediate-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*Pre-byte for stack pointer indexed instructions
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
LSB
MSB
Bit Manipulation
DIR
DIR
Table 6-2. Opcode Map
2
E
1
F
IX
2
SUB
IX
2
CMP
1 IX
2
SBC
1 IX
2
CPX
1 IX
2
AND
1 IX
2
BIT
1 IX
2
LDA
1 IX
2
STA
1 IX
2
EOR
1 IX
2
ADC
1 IX
2
ORA
1 IX
2
ADD
1 IX
2
JMP
1 IX
4
JSR
1 IX
4
2
LDX
LDX
3 SP1 1 IX
4
2
STX
STX
3 SP1 1 IX
4
SUB
SP1
4
CMP
3 SP1
4
SBC
3 SP1
4
CPX
3 SP1
4
AND
3 SP1
4
BIT
3 SP1
4
LDA
3 SP1
4
STA
3 SP1
4
EOR
3 SP1
4
ADC
3 SP1
4
ORA
3 SP1
4
ADD
3 SP1
3
9EE
SP1
High Byte of Opcode in Hexadecimal
3
SUB
IX1
3
CMP
2 IX1
3
SBC
2 IX1
3
CPX
2 IX1
3
AND
2 IX1
3
BIT
2 IX1
3
LDA
2 IX1
3
STA
2 IX1
3
EOR
2 IX1
3
ADC
2 IX1
3
ORA
2 IX1
3
ADD
2 IX1
3
JMP
2 IX1
5
JSR
2 IX1
5
3
LDX
LDX
4 SP2 2 IX1
5
3
STX
STX
4 SP2 2 IX1
5
SUB
SP2
5
CMP
4 SP2
5
SBC
4 SP2
5
CPX
4 SP2
5
AND
4 SP2
5
BIT
4 SP2
5
LDA
4 SP2
5
STA
4 SP2
5
EOR
4 SP2
5
ADC
4 SP2
5
ORA
4 SP2
5
ADD
4 SP2
4
9ED
IX1
Cycles
5
BRSET0 Opcode Mnemonic
3 DIR Number of Bytes / Addressing Mode
0
4
SUB
IX2
4
CMP
3 IX2
4
SBC
3 IX2
4
CPX
3 IX2
4
AND
3 IX2
4
BIT
3 IX2
4
LDA
3 IX2
4
STA
3 IX2
4
EOR
3 IX2
4
ADC
3 IX2
4
ORA
3 IX2
4
ADD
3 IX2
4
JMP
3 IX2
6
JSR
3 IX2
4
LDX
3 IX2
4
STX
3 IX2
3
D
Register/Memory
SP2
IX2
R E Q U I R E D
4
SUB
EXT
4
CMP
3 EXT
4
SBC
3 EXT
4
CPX
3 EXT
4
AND
3 EXT
4
BIT
3 EXT
4
LDA
3 EXT
4
STA
3 EXT
4
EOR
3 EXT
4
ADC
3 EXT
4
ORA
3 EXT
4
ADD
3 EXT
3
JMP
3 EXT
5
JSR
3 EXT
4
LDX
3 EXT
4
STX
3 EXT
3
C
EXT
Freescale Semiconductor,
nc...
A G R E E M E IN
T
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
MC68HC08KL8 — Rev. 2.0
Freescale Semiconductor, Inc...
7.1 Contents
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7.3
Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . .74
7.4
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
7.4.1
Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . . .75
7.4.2
Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . .75
7.4.3
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . .75
7.4.4
External Clock Source (CGMXCLK) . . . . . . . . . . . . . . . . . .75
7.4.5
Oscillator Out (CGMOUT) . . . . . . . . . . . . . . . . . . . . . . . . . .76
7.5
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
7.5.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
7.5.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
7.6
Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . .76
7.2 Introduction
The oscillator circuit is designed for use with crystals or ceramic
resonators. The oscillator circuit generates the crystal clock signal,
CGMXCLK, at the frequency of the crystal. This signal is divided by two
before being passed on to the system integration module (SIM) for bus
clock generation.
Figure 7-1 shows the structure of the oscillator. The oscillator requires
various external components.
MC68HC08KL8 — Rev. 2.0
General Release Specification
Oscillator
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
Section 7. Oscillator
N O N - D I S C L O S U R E
General Release Specification — MC68HC08KL8
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Oscillator
7.3 Oscillator External Connections
In its typical configuration, the oscillator requires five external
components. The crystal oscillator is normally connected in a Pierce
oscillator configuration, as shown in Figure 7-1. This figure shows only
the logical representation of the internal components and may not
represent actual circuitry. The oscillator configuration uses five
components:
•
Crystal, X1
•
Fixed capacitor, C1
•
Tuning capacitor, C2 (can also be a fixed capacitor)
•
Feedback resistor, RB
•
Series resistor, RS (optional)
TO SIM
AND USB
FROM
SIM
CGMXCLK
TO SIM
÷2
CGMOUT
SIMOSCEN
MCU
OSC1
OSC2
RB
RS*
X1
C1
C2
* RS can be 0 (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data.
Figure 7-1. Oscillator External Connections
General Release Specification
MC68HC08KL8 — Rev. 2.0
Oscillator
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
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The following paragraphs describe the oscillator input/output (I/O)
signals.
7.4.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
7.4.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
7.4.3 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM)
and enables the oscillator.
7.4.4 External Clock Source (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal (fXCLK) and comes directly from the crystal oscillator circuit.
Figure 7-1 shows only the logical relation of CGMXCLK to OSC1 and
OSC2 and may not represent the actual circuitry. The duty cycle of
CGMXCLK is unknown and may depend on the crystal and other
external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
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7.4 I/O Signals
N O N - D I S C L O S U R E
The series resistor (RS) is included in the diagram to follow strict Pierce
oscillator guidelines and may not be required for all ranges of operation,
especially with high-frequency crystals. Refer to the crystal
manufacturer’s data for more information.
R E Q U I R E D
Oscillator
I/O Signals
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R E Q U I R E D
Oscillator
7.4.5 Oscillator Out (CGMOUT)
The clock driven to the SIM is the crystal frequency divided by two. This
signal is driven to the SIM for generation of the bus clocks used by the
CPU and other modules on the MCU. CGMOUT will be divided again in
the SIM and results in the internal bus frequency being one fourth of the
CGMXCLK frequency.
7.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby
modes.
7.5.1 Wait Mode
The WAIT instruction has no effect on the oscillator logic. CGMXCLK
continues to drive to the SIM module.
7.5.2 Stop Mode
The STOP instruction disables the CGMXCLK output.
7.6 Oscillator During Break Mode
The oscillator continues to drive CGMXCLK when the chip enters the
break state.
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Section 8. System Integration Module (SIM)
8.1 Contents
8.3
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . .81
8.3.1
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
8.3.2
Clock Startup from POR . . . . . . . . . . . . . . . . . . . . . . . . . . .82
8.3.3
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . .82
8.4
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . .82
8.4.1
External Pin Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
8.4.2
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . .84
8.4.2.1
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
8.4.2.2
Computer Operating Properly (COP) Reset. . . . . . . . . . .86
8.4.2.3
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
8.4.2.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
8.4.2.5
Universal Serial Bus Reset . . . . . . . . . . . . . . . . . . . . . . .87
8.5
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
8.5.1
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . .87
8.5.2
SIM Counter During Stop Mode Recovery . . . . . . . . . . . . .88
8.5.3
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . .88
8.6
Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
8.6.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
8.6.1.1
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
8.6.1.2
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
8.6.2
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . .92
8.6.2.1
Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . .93
8.6.2.2
Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . .94
8.6.3
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
8.6.4
Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
8.6.5
Status Flag Protection in Break Mode. . . . . . . . . . . . . . . . .95
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A G R E E M E N T
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
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8.2
R E Q U I R E D
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8.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
8.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
8.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
8.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.8.1
Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.8.2
Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
8.8.3
Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . .102
8.2 Introduction
This section describes the system integration module (SIM), which
supports up to 16 external and/or internal interrupts. Together with the
CPU, the SIM controls all MCU activities. The SIM is a system state
controller that coordinates CPU and exception timing. A block diagram
of the SIM is shown in Figure 8-1. Figure 8-2 is a summary of the SIM
I/O registers.
The SIM is responsible for:
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System Integration Module (SIM)
•
Bus clock generation and control for CPU and peripherals
– Stop/wait/reset/break entry and recovery
– Internal clock control
•
Master reset control, including power-on reset (POR) and
computer operating properly (COP) timeout
•
Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
•
CPU enable/disable timing
•
Modular architecture expandable to 128 interrupt sources
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CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
SIM
COUNTER
COP CLOCK
CGMXCLK (FROM OSCILLATOR)
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CGMOUT (FROM OSCILLATOR)
÷2
CLOCK
CONTROL
RESET
PIN LOGIC
CLOCK GENERATORS
POR CONTROL
MASTER
RESET
CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
INTERNAL CLOCKS
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
USB RESET (FROM USB MODULE)
RESET
INTERRUPT CONTROL
AND PRIORITY DECODE
INTERRUPT SOURCES
CPU INTERFACE
Figure 8-1. SIM Block Diagram
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A G R E E M E N T
MODULE WAIT
STOP/WAIT
CONTROL
N O N - D I S C L O S U R E
MODULE STOP
R E Q U I R E D
System Integration Module (SIM)
Introduction
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System Integration Module (SIM)
Addr.
Register Name
Bit 7
6
5
4
3
2
$FE00
Break Status Register Read:
(BSR) Write:
R
R
R
R
R
R
Reset Status Register Read:
(RSR) Write:
POR:
$FE03
$FE04
Interrupt Status Register 1 Read:
(INT1) Write:
Reset:
$FE05
Interrupt Status Register 2 Read:
(INT2) Write:
Reset:
Note 1. Writing a logic 0 clears SBSW.
R
Note 1
0
POR
PIN
COP
ILOP
ILAD
USB
0
0
1
0
0
0
0
0
0
0
R
R
R
R
R
R
R
IF6
IF5
IF4
IF3
IF2
IF1
0
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Break Flag Control Register Read:
BCFE
(BFCR) Write:
Reset:
0
SBSW
Reset:
$FE01
1
0
= Unimplemented
R
= Reserved
Figure 8-2. SIM Register Summary
NOTE:
Writing to a reserved address can have unpredictable effects on MCU
operation.
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Signal Name
Description
CGMXCLK
Buffered OSC1 from the oscillator
CGMOUT
The CGMXCLK frequency divided by two. This signal is again
divided by two in the SIM to generate the internal bus clocks.
(Bus clock = CGMXCLK divided by four)
IAB
Internal address bus
IDB
Internal data bus
PORRST
Signal from the power-on reset module to the SIM
IRST
Internal reset signal
R/W
Read/write signal
8.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 8-3.
FROM
OSCILLATOR
CGMXCLK
FROM
OSCILLATOR
CGMOUT
SIM COUNTER
BUS CLOCK
GENERATORS
÷2
SIM
Figure 8-3. SIM Clock Signals
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Table 8-1. Signal Name Conventions
N O N - D I S C L O S U R E
Table 8-1 shows the internal signal names used in this section.
R E Q U I R E D
System Integration Module (SIM)
SIM Bus Clock Control and Generation
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R E Q U I R E D
System Integration Module (SIM)
8.3.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency
(CGMXCLK) divided by four.
8.3.2 Clock Startup from POR
When the power-on reset (POR) module generates a reset, the clocks
to the CPU and peripherals are inactive and held in an inactive phase
until after the 4096 CGMXCLK cycle POR timeout has completed. The
RST pin is driven low by the SIM during this entire period. The IBUS
clocks start upon completion of the timeout.
8.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 32 CGMXCLK cycles. (See 8.7.2 Stop Mode.)
In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
8.4 Reset and System Initialization
The MCU has these reset sources:
•
Power-on reset module (POR)
•
External reset pin (RST)
•
Computer operating properly module (COP)
•
Illegal opcode
•
Illegal address
•
Universal serial bus module (USB)
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8.4.1 External Pin Reset
The RST pin circuits include an internal pullup device. Pulling the
asynchronous RST pin low halts all processing. The PIN bit of the reset
status register (RSR) is set as long as RST is held low for a minimum of
67 CGMXCLK cycles, assuming that the POR was not the source of the
reset. See Table 8-2 for details. Figure 8-4 shows the relative timing.
Table 8-2. PIN Bit Set Timing
Reset Type
Number of Cycles Required to Set PIN
POR
4163 (4096 + 64 + 3)
All Others
67 (64 + 3)
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An internal reset clears the SIM counter (see 8.5 SIM Counter), but an
external reset does not. Each of the resets sets a corresponding bit in
the reset status register (RSR). (See 8.8 SIM Registers.)
CGMOUT
RST
IAB
PC
VECT H
VECT L
Figure 8-4. External Reset Timing
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All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
R E Q U I R E D
System Integration Module (SIM)
Reset and System Initialization
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System Integration Module (SIM)
8.4.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles. (See Figure
8-5.) An internal reset can be caused by an illegal address, illegal
opcode, COP timeout, the USB module, or POR. (See Figure 8-6.) Note
that for POR resets, the SIM cycles through 4096 CGMXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal
then follows the sequence from the falling edge of RST shown in Figure
8-5.
IRST
RST
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
CGMXCLK
IAB
VECTOR HIGH
Figure 8-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
USB
INTERNAL RESET
Figure 8-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
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8.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. Sixty-four CGMXCLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to
occur.
R E Q U I R E D
System Integration Module (SIM)
Reset and System Initialization
A POR pulse is generated.
•
The internal reset signal is asserted.
•
The SIM enables the oscillator to drive CGMXCLK.
•
Internal clocks to the CPU and modules are held inactive for 4096
CGMXCLK cycles to allow stabilization of the oscillator.
•
The RST pin is driven low during the oscillator stabilization time.
•
The POR bit of the reset status register (RSR) is set and all other
bits in the register are cleared.
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
CGMXCLK
CGMOUT
RST
IAB
$FFFE
$FFFF
Figure 8-7. POR Recovery
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•
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At power-on, these events occur:
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R E Q U I R E D
System Integration Module (SIM)
8.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
reset status register (RSR). The SIM actively pulls down the RST pin for
all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and stages 12 through
5 of the SIM counter. The SIM counter output, which occurs at least
every 212 – 24 CGMXCLK cycles, drives the COP counter. The COP
should be serviced as soon as possible out of reset to guarantee the
maximum amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ1 pin is held at
VTST while the MCU is in monitor mode. The COP module can be
disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ1 pin. This prevents the COP from
becoming disabled as a result of external noise. During a break state,
VTST on the RST pin disables the COP module.
8.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the reset status register (RSR) and
causes a reset.
If the stop enable bit, STOP, in the mask option register is logic 0, the
SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
8.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the reset status register (RSR) and resetting
the MCU. A data fetch from an unmapped address does not generate a
reset. The SIM actively pulls down the RST pin for all internal reset
sources.
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Reset can wake a device from the suspended mode. A device may take
up to 10 ms to wake up from the suspended state.
8.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescalar for the computer operating properly module (COP). The SIM
counter uses 12 stages for counting, followed by a 13th stage that
triggers a reset of SIM counters and supplies the clock for the COP
module. The SIM counter is clocked by the falling edge of CGMXCLK.
8.5.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the oscillator to drive the bus clock state machine.
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The USB module will detect a reset signaled on the bus by the presence
of an extended SE0 at the USB data pins of a device. The reset signaling
is specified to be present for a minimum of 10 ms. An active device
(powered and not in the suspend state) seeing a single-ended 0 on its
USB data inputs for more than 2.5 µs may treat that signal as a reset,
but must have interpreted the signaling as a reset within 5.5 µs. For a
low-speed device, an SE0 condition between 4 and 8 low-speed bit
times represents a valid USB reset. After the reset is removed, the
device will be in the attached, but not yet addressed or configured, state
(refer to Section 9.1 USB Devices of the Universal Serial Bus
Specification Rev. 1.0). The device must be able to accept the device
address via a SET_ADDRESS command (refer to Section 9.4 of the
Universal Serial Bus Specification Rev. 1.0) no later than 10 ms after the
reset is removed.
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8.4.2.5 Universal Serial Bus Reset
R E Q U I R E D
System Integration Module (SIM)
SIM Counter
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System Integration Module (SIM)
8.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic 1, then the stop recovery is
reduced from the normal delay of 4096 CGMXCLK cycles down to 32
CGMXCLK cycles. This is ideal for applications using canned oscillators
that do not require long startup times from stop mode. External crystal
applications should use the full stop recovery time by having SSREC
cleared in the mask option register.
8.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 8.7.2 Stop Mode
for details.) The SIM counter is free-running after all reset states. (See
8.4.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.)
8.6 Exception Control
Normal, sequential program execution can be changed in three different
ways:
•
Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
•
Reset
•
Break interrupts
8.6.1 Interrupts
An interrupt temporarily changes the sequence of program execution to
respond to a particular event. The flowchart in Figure 8-8 shows the
handling of system interrupts.
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BREAK
INTERRUPT
?
NO
YES
YES
BITSET?
SET?
IIBIT
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NO
IRQ1
INTERRUPT
?
NO
YES
USB
INTERRUPT
?
NO
YES
OTHER
INTERRUPTS
?
NO
YES
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION
?
YES
NO
RTI
INSTRUCTION
?
YES
UNSTACK CPU REGISTERS
NO
EXECUTE INSTRUCTION
Figure 8-8. Interrupt Processing
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N O N - D I S C L O S U R E
FROM RESET
A G R E E M E N T
R E Q U I R E D
System Integration Module (SIM)
Exception Control
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System Integration Module (SIM)
Interrupts are latched and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced or the I bit is cleared.
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 8-9 shows interrupt entry timing. Figure
8-10 shows interrupt recovery timing.
MODULE
INTERRUPT
I BIT
IAB
IDB
DUMMY
SP
DUMMY
SP – 1
PC – 1[7:0]
SP – 2
PC–1[15:8]
SP – 3
SP – 4
A
X
VECT H
CCR
VECT L
V DATA H
START ADDR
V DATA L
OPCODE
R/W
Figure 8-9. Interrupt Entry
MODULE
INTERRUPT
I BIT
IAB
IDB
SP – 4
SP – 3
CCR
SP – 2
A
SP – 1
X
SP
PC
PC – 1 [7:0] PC–1[15:8]
PC + 1
OPCODE
OPERAND
R/W
Figure 8-10. Interrupt Recovery
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A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register) and if the corresponding interrupt enable bit is
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
Freescale Semiconductor, Inc...
If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first. Figure 8-11
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service routine,
the pending interrupt is serviced before the LDA instruction is executed.
CLI
BACKGROUND
ROUTINE
LDA #$FF
INT1
PSHH
A G R E E M E N T
8.6.1.1 Hardware Interrupts
R E Q U I R E D
System Integration Module (SIM)
Exception Control
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 8-11. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
NOTE:
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
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N O N - D I S C L O S U R E
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
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N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
System Integration Module (SIM)
8.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
NOTE:
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC–1, as a hardware interrupt does.
8.6.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt
sources. Table 8-3 summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 8-3. Interrupt Sources
Flags
Mask(1)
INT Register Flag
Priority(2)
Vector Address
—
—
—
0
$FFFC–$FFFD
IRQ1 Pin
IRQF1
IMASK1
IF1
1
$FFFA–$FFFB
USB Endpoint 0 Transmit
TXD0F
TXD0IE
USB Endpoint 0 Receive
RXD0F
RXD0IE
USB Endpoint 1/
Endpoint 2 Transmit
TXD1F
TXD1IE
IF2
2
$FFF8–$FFF9
USB End of Packet
EOPF
EOPIE
RESUMF
—
TIM Channel 0
CH0F
CH0IE
IF3
3
$FFF6–$FFF7
TIM Channel 1
CH1F
CH1IE
IF4
4
$FFF4–$FFF5
TIM Overflow
TOF
TOIE
IF5
5
$FFF2–$FFF3
Keyboard Pins
KEYF
IMASKK
IF6
6
$FFF0–$FFF1
Source
SWI Instruction
USB Resume Interrupt
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction.
2. 0 = highest priority
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8.6.2.1 Interrupt Status Register 1
$FE04
Bit 7
6
5
4
3
2
1
Bit 0
Read:
IF6
IF5
IF4
IF3
IF2
IF1
0
0
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
= Reserved
Figure 8-12. Interrupt Status Register 1 (INT1)
NOTE:
Writing to a reserved address can have unpredictable effects on MCU
operation.
IF6–IF1 — Interrupt Flags 1–6
These flags indicate the presence of interrupt requests from
the sources shown in Table 8-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0 and Bit 1 — Always read 0
N O N - D I S C L O S U R E
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R
A G R E E M E N T
Address:
R E Q U I R E D
System Integration Module (SIM)
Exception Control
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R E Q U I R E D
System Integration Module (SIM)
8.6.2.2 Interrupt Status Register 2
Address:
$FE05
Bit 7
6
5
4
3
2
1
Bit 0
Read:
IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
= Reserved
Figure 8-13. Interrupt Status Register 2 (INT2)
NOTE:
Writing to a reserved address can have unpredictable effects on MCU
operation.
IF14–IF7 — Interrupt Flags 14–7
Since the MC68HC08KL8 does not use these interrupt flags,
these bits will always read 0.
N O N - D I S C L O S U R E
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A G R E E M E N T
R
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8.6.4 Break Interrupts
The break module can stop normal program flow at a softwareprogrammable break point by asserting its break interrupt output. (See
Section 16. Break Module (BREAK).) The SIM puts the CPU into the
break state by forcing it to the SWI vector location. Refer to the break
interrupt subsection of each module to see how each module is affected
by the break state.
8.6.5 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can
be cleared during break mode. The user can select whether flags are
protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the break flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a 2-step clearing mechanism — for example, a read of
one register followed by the read or write of another — are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the
flag as normal.
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A G R E E M E N T
All reset sources always have equal and highest priority and cannot be
arbitrated.
N O N - D I S C L O S U R E
8.6.3 Reset
R E Q U I R E D
System Integration Module (SIM)
Exception Control
Freescale Semiconductor, Inc.
R E Q U I R E D
System Integration Module (SIM)
8.7 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low-power
mode for standby situations. The SIM holds the CPU in a non-clocked
state. The operation of each of these modes is described here. Both
STOP and WAIT clear the interrupt mask (I) in the condition code
register, allowing interrupts to occur.
N O N - D I S C L O S U R E
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A G R E E M E N T
8.7.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks
continue to run. Figure 8-14 shows the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred. In
wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode. Some modules can be programmed to be active in wait
mode.
Wait mode can also be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the break
status register (BSR). If the COP disable bit, COPD, in the mask option
register is logic 0, then the computer operating properly module (COP)
is enabled and remains active in wait mode.
IAB
IDB
WAIT ADDR
WAIT ADDR + 1
PREVIOUS DATA
SAME
NEXT OPCODE
SAME
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
Figure 8-14. Wait Mode Entry Timing
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IDB
$6E0B
$A6
$6E0C
$A6
$A6
$00FF
$01
$0B
$00FE
$00FD
$00FC
$6E
EXITSTOPWAIT
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NOTE: EXITSTOPWAIT = RST pin or CPU interrupt or break interrupt
Figure 8-15. Wait Recovery from Interrupt or Break
32
CYCLES
$6E0B
IAB
IDB
32
CYCLES
$A6
$A6
RSTVCTH
RSTVCTL
$A6
RST
CGMXCLK
Figure 8-16. Wait Recovery from Internal Reset
8.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (CGMOUT and CGMXCLK) in
stop mode, stopping the CPU and peripherals. Stop recovery time is
selectable using the SSREC bit in the mask option register. If SSREC is
set, stop recovery is reduced from the normal delay of 4096 CGMXCLK
cycles down to 32. This is ideal for applications using canned oscillators
that do not require long startup times from stop mode.
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A G R E E M E N T
IAB
N O N - D I S C L O S U R E
Figure 8-15 and Figure 8-16 show the timing for WAIT recovery.
R E Q U I R E D
System Integration Module (SIM)
Low-Power Modes
Freescale Semiconductor, Inc.
R E Q U I R E D
System Integration Module (SIM)
NOTE:
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the break status register (BSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period. Figure 8-17 shows stop mode entry timing.
NOTE:
A G R E E M E N T
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N O N - D I S C L O S U R E
External crystal applications should use the full stop recovery time by not
selecting the SSREC option.
To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
CPUSTOP
IAB
IDB
STOP ADDR
STOP ADDR + 1
PREVIOUS DATA
SAME
NEXT OPCODE
SAME
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 8-17. Stop Mode Entry Timing
STOP RECOVERY PERIOD
CGMXCLK
INT/BREAK
IAB
STOP +1
STOP + 2
STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 8-18. Stop Mode Recovery from Interrupt or Break
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8.8.1 Break Status Register
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The break status register contains a flag to indicate that a break caused
an exit from stop mode or wait mode.
Address:
$FE00
Bit 7
6
5
4
3
2
R
R
R
R
R
R
Read:
1
Bit 0
SBSW
R
Write:
Note 1
Reset:
0
Note 1. Writing a logic 0 clears SBSW.
R
= Reserved
Figure 8-19. Break Status Register (BSR)
NOTE:
Writing to a reserved address can have unpredictable effects on MCU
operation.
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait
mode or stop mode after exiting from a break interrupt. Clear
SBSW by writing a logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode exited by break interrupt
0 = Stop mode or wait mode not exited by break interrupt
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A G R E E M E N T
The SIM has two break registers and one reset register.
N O N - D I S C L O S U R E
8.8 SIM Registers
R E Q U I R E D
System Integration Module (SIM)
SIM Registers
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A G R E E M E N T
R E Q U I R E D
System Integration Module (SIM)
SBSW can be read within the break state SWI routine. The
user can modify the return address on the stack by subtracting
one from it.
The following code is an example of this. Writing 0 to the
SBSW bit clears it.
This code works if the H register has been pushed onto the stack in the break service
routine software. This code should be executed at the end of the break service routine
software.
HIBYTE
EQU
5
LOBYTE
EQU
6
;
If not SBSW, do RTI
BRCLR
SBSW,BSR, RETURN
; See if wait mode or stop mode was exited
; by break.
TST
LOBYTE,SP
; If RETURNLO is not zero,
BNE
DOLO
; then just decrement low byte.
DEC
HIBYTE,SP
; Else deal with high byte, too.
DOLO
DEC
LOBYTE,SP
; Point to WAIT/STOP opcode.
RETURN
PULH
RTI
; Restore H register.
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Address:
Read:
$FE01
Bit 7
6
5
4
3
2
1
Bit 0
POR
PIN
COP
ILOP
ILAD
USB
0
0
1
0
0
0
0
0
0
0
Write:
POR:
= Unimplemented
Figure 8-20. Reset Status Register (RSR)
POR — Power-On Reset Bit
1 = A POR has occurred.
0 = Read of RSR
PIN — External Reset Bit
1 = An external reset has occurred since the last read of the
RSR.
0 = Read of RSR
COP — Computer Operating Properly Reset Bit
1 = A COP reset has occurred since the last read of the
RSR.
0 = POR or read of RSR
ILOP — Illegal Opcode Reset Bit
1 = An illegal opcode reset has occurred since the last read
of the RSR.
0 = POR or read of RSR
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A G R E E M E N T
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This register contains six flags that show the source of the last reset. All
flag bits are cleared automatically following a read of the register. The
register is initialized on power-up as shown with the POR bit set and all
other bits cleared. However, during a POR or any other internal reset,
the RST pin is pulled low. After the pin is released, it will be sampled 32
CGMXCLK cycles later. If the pin is not above a VIH at that time, then the
PIN bit in the RSR may be set in addition to whatever other bits are
set.
N O N - D I S C L O S U R E
8.8.2 Reset Status Register
R E Q U I R E D
System Integration Module (SIM)
SIM Registers
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N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
System Integration Module (SIM)
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = An illegal address reset has occurred since the last read
of the RSR.
0 = POR or read of RSR
USB — Universal Serial Bus Reset Bit
1 = Last reset caused by an USB module
0 = POR or read of RSR
8.8.3 Break Flag Control Register
The break control register contains a bit that enables software to clear
status bits while the MCU is in a break state.
Address:
$FE03
Bit 7
6
5
4
3
2
1
Bit 0
BCFE
R
R
R
R
R
R
R
Read:
Write:
POR:
0
R
= Reserved
Figure 8-21. Break Flag Control Register (BFCR)
NOTE:
Writing to a reserved address can have unpredictable effects on MCU
operation.
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by
accessing status registers while the MCU is in a break state.
To clear status bits during the break state, the BCFE bit must
be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
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Section 9. Universal Serial Bus Module (USB)
9.1 Contents
9.3
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
9.3.1
USB Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
9.3.1.1
Sync Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
9.3.1.2
Packet Identifier Field. . . . . . . . . . . . . . . . . . . . . . . . . . .110
9.3.1.3
Address Field (ADDR) . . . . . . . . . . . . . . . . . . . . . . . . . .110
9.3.1.4
Endpoint Field (ENDP). . . . . . . . . . . . . . . . . . . . . . . . . .110
9.3.1.5
Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . .111
9.3.1.6
End-of-Packet (EOP) . . . . . . . . . . . . . . . . . . . . . . . . . . .113
9.3.2
Reset Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
9.3.3
Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9.3.4
Resume After Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9.3.4.1
Host Initiated Resume . . . . . . . . . . . . . . . . . . . . . . . . . .115
9.3.4.2
USB Reset Signalling. . . . . . . . . . . . . . . . . . . . . . . . . . .116
9.3.4.3
Remote Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
9.3.5
Low-Speed Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
9.4
Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
9.5
Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
9.5.1
Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
9.5.2
Regulator Bypass Option . . . . . . . . . . . . . . . . . . . . . . . . .119
9.5.3
USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
9.5.3.1
Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . .120
9.5.3.2
Low Speed (1.5 Mbs) Driver Characteristics . . . . . . . . .120
9.5.3.3
Receiver Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
9.5.3.4
Data Source Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
9.5.3.5
Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . .123
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A G R E E M E N T
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
N O N - D I S C L O S U R E
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9.2
R E Q U I R E D
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9.5.4
9.5.4.1
9.5.4.2
USB Control Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Data Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . .125
Bit Stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
9.6
I/O Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
9.6.1
USB Address Register
. . . . . . . . . . . . . . . . . . . . . . . .131
9.6.2
USB Interrupt Register 0
. . . . . . . . . . . . . . . . . . . . . . .132
9.6.3
USB Interrupt Register 1 . . . . . . . . . . . . . . . . . . . . . . . .134
9.6.4
USB Control Register 0
. . . . . . . . . . . . . . . . . . . . . . . .136
9.6.5
USB Control Register 1
. . . . . . . . . . . . . . . . . . . . . . .138
9.6.6
USB Control Register 2
. . . . . . . . . . . . . . . . . . . . . . . .140
9.6.7
USB Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . .142
9.6.8
USB Endpoint 0 Data Registers . . . . . . . . . . . . . . . . . . . .143
9.6.9
USB Endpoint 1/Endpoint 2 Data Registers . . . . . . . . . . .144
9.7
USB Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
9.7.1
USB End-of-Transaction Interrupt . . . . . . . . . . . . . . . . . . .145
9.7.1.1
Receive Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . . .145
9.7.1.2
Transmit Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . .148
9.7.1.3
Transmit Endpoint 1 and Transmit Endpoint 2. . . . . . . .149
9.7.2
Resume Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
9.7.3
End-of-Packet Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .150
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Universal Serial Bus Module (USB)
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Universal Serial Bus Module (USB)
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•
Integrated 3.3-Volt Regulator with 3.3-Volt Output Pin
•
Integrated USB Transceiver Supporting Low-Speed Functions
•
USB Data Control Logic
– Packet Decoding/Generation
– CRC (Cyclic Redundancy Check) Generation and Checking
– NRZI (Non-Return-to Zero Inserted) Encoding/Decoding
– Bit-Stuffing
•
USB Reset Support
•
Control Endpoint 0 and Interrupt Endpoints 1 and 2
•
Two 8-Byte Transmit Buffers
•
One 8-Byte Receive Buffer
•
Suspend and Resume Operations
– Remote Wakeup Support
•
USB-Generated Interrupts
– Transaction Interrupt Driven
– Resume Interrupt
– End-of-Packet Interrupt
•
Stall, Nak, and Ack Handshake Generation
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Features of the USB (universal serial bus) module include:
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9.2 Features
R E Q U I R E D
Universal Serial Bus Module (USB)
Features
Freescale Semiconductor, Inc.
9.3 Overview
This section provides an overview of the universal serial bus (USB)
module developed for the MC68HC08KL8. This USB module is
designed to serve as a low-speed (LS) USB device per the Universal
Serial Bus Specification Rev 1.0. Three types of USB data transfers are
supported: control, interrupt, and bulk (transmit only). Endpoint 0
functions as a receive/transmit control endpoint. Endpoints 1 and 2 can
function as interrupt or bulk, but only in the transmit direction.
A block diagram of the USB module is shown in Figure 9-1. The USB
module manages communications between the host and the USB
function. The module is partitioned into four functional blocks. These
blocks consist of a 3.3-volt regulator, a dual-function transceiver, the
USB control logic, and the endpoint registers. The blocks are further
detailed later in this section (see 9.5 Hardware Description).
CPU BUS
USB REGISTERS
D+
VPIN
TRANSCEIVER
USB CONTROL LOGIC
RCV
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A G R E E M E N T
R E Q U I R E D
Universal Serial Bus Module (USB)
VMIN
VPOUT
D–
USB
UPSTREAM
PORT
VMOUT
REGULATOR
REGOUT
3.3 V OUT
Figure 9-1. USB Block Diagram
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MC68HC08KL8 — Rev. 2.0
Universal Serial Bus Module (USB)
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ENDPOINT 0 TRANSACTIONS:
CONTROL WRITE
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SETUP
DATA0
ACK
OUT
DATA0
OUT
ACK
DATA1
ACK
OUT
DATA0/1
IN
ACK
ACK
DATA1
CONTROL READ
ACK
DATA0
SETUP
IN
IN
DATA0
ACK
DATA1
ACK
IN
DATA0/1
OUT
DATA1
ACK
ACK
NO-DATA CONTROL
SETUP
ACK
DATA0
IN
DATA1
ACK
ENDPOINTS 1 AND 2 TRANSACTIONS:
KEY:
INTERRUPT
DATA0/1
IN
ACK
UNRELATED BUS
TRAFFIC
HOST
GENERATED
BULK TRANSMIT
DATA0/1
IN
ACK
DEVICE
GENERATED
Figure 9-2. Supported Transaction Types Per Endpoint
MC68HC08KL8 — Rev. 2.0
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Universal Serial Bus Module (USB)
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A G R E E M E N T
Figure 9-2 shows the various transaction types supported by the
MC68HC08KL8 USB module. The transactions are portrayed as error
free. The effect of errors in the data flow are discussed later.
N O N - D I S C L O S U R E
9.3.1 USB Protocol
R E Q U I R E D
Universal Serial Bus Module (USB)
Overview
Freescale Semiconductor, Inc.
R E Q U I R E D
Universal Serial Bus Module (USB)
Each USB transaction is comprised of a series of packets. The
MC68HC08KL8 USB module supports the packet types shown in Figure
9-3. Token packets are generated by the USB host and decoded by the
USB device. Data and handshake packets are both decoded and
generated by the USB device, depending on the type of transaction.
Token Packet:
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A G R E E M E N T
IN
OUT
SYNC
PID
PID
SYNC
PID
PID
ADDR
ENDP
CRC5
EOP
CRC16
EOP
SETUP
Data Packet:
DATA0
DATA1
DATA
0 – 8 Bytes
Handshake Packet:
ACK
NAK
SYNC
PID
PID
EOP
STALL
Figure 9-3. Supported USB Packet Types
The following subsections detail each segment used to form a complete
USB transaction.
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Universal Serial Bus Module (USB)
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SYNC PATTERN
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NRZI DATA
ENCODING
PID0
BUS IDLE
PID1
Figure 9-4. Sync Pattern
The start of a packet (SOP) is signaled by the originating port by driving
the D+ and D– lines from the idle state (also referred to as the J state) to
the opposite logic level (also referred to as the K state). This switch in
levels represents the first bit of the sync field. Figure 9-5 shows the data
signaling and voltage levels for the start-of-packet and the sync pattern.
VOH (MIN)
VSE (MAX)
VSE (MIN)
VOL (MAX)
VSS
FIRST BIT OF PACKET
BUS IDLE
SOP
END OF SYNC
Figure 9-5. SOP, Sync Signaling, and Voltage Levels
MC68HC08KL8 — Rev. 2.0
General Release Specification
Universal Serial Bus Module (USB)
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A G R E E M E N T
The NRZI (see 9.5.4.1 Data Encoding/Decoding) bit pattern shown in
Figure 9-4 is used as a synchronization pattern and is prefixed to each
packet. This pattern is equivalent to a data pattern of seven 0s followed
by a 1 ($80).
N O N - D I S C L O S U R E
9.3.1.1 Sync Pattern
R E Q U I R E D
Universal Serial Bus Module (USB)
Overview
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R E Q U I R E D
Universal Serial Bus Module (USB)
9.3.1.2 Packet Identifier Field
The packet identifier field is an 8-bit number comprised of the 4-bit
packet identification and its complement. The field follows the sync
pattern and determines the direction and type of transaction on the bus.
Table 9-1 shows the packet identifier values for the supported packet
types.
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A G R E E M E N T
Table 9-1. Supported Packet Identifiers
Packet Identifier Value
Packet Identifier Type
%1001
IN Token
%0001
OUT Token
%1101
SETUP Token
%0011
DATA0 Packet
%1011
DATA1 Packet
%0010
ACK Handshake
%1010
NAK Handshake
%1110
STALL Handshake
9.3.1.3 Address Field (ADDR)
The address field is a 7-bit number that is used to select a particular USB
device. This field is compared to the lower seven bits of the UADDR
register to determine if a given transaction is targeting the
MC68HC08KL8 USB device.
9.3.1.4 Endpoint Field (ENDP)
The endpoint field is a 4-bit number that is used to select a particular
endpoint within a USB device. For the MC68HC08KL8, this will be a
binary number between 0 and 2 inclusive. Any other value will cause the
transaction to be ignored.
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MC68HC08KL8 — Rev. 2.0
Universal Serial Bus Module (USB)
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9.3.1.5 Cyclic Redundancy Check (CRC)
A G R E E M E N T
– UPDATE EVERY BIT TIME
– PRESET TO ONES AT SOP
GENERATOR POLYNOMIAL
0
0
1
0
1
5
DATA STREAM
NEXT BIT
0
5
0
MUX
1
5
EXPECTED RESIDUAL
0
5
1
1
0
0
5
GOOD CRC
BAD CRC
EQUAL?
N
Y
Figure 9-6. CRC Block Diagram for Token Packets
MC68HC08KL8 — Rev. 2.0
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Universal Serial Bus Module (USB)
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Cyclic redundancy checks are used to verify the address and data
stream of a USB transaction. This field is five bits wide for token packets
and 16 bits wide for data packets. CRCs are generated in the transmitter
and sent on the USB data lines after both the endpoint field and the data
field. Figure 9-6 shows how the 5-bit CRC value is calculated from the
data stream and verified for the address and endpoint fields of a token
packet. Figure 9-7 shows how the 16-bit CRC value is calculated and
either transmitted or verified for the data packet of a given transaction.
R E Q U I R E D
Universal Serial Bus Module (USB)
Overview
Freescale Semiconductor, Inc.
R E Q U I R E D
Universal Serial Bus Module (USB)
– UPDATE EVERY BIT TIME
– RESET TO ONES AT SOP
GENERATOR POLYNOMIAL
1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
INPUT/OUTPUT
DATA STREAM
16
NEXT BIT
0
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A G R E E M E N T
16
0
OUTPUT
DATA STREAM
TRANSMIT
MUX
1
16
16
CRC16 IS TRANSMITTED
MSB FIRST AFTER FINAL
DATA BYTE.
EXPECTED RESIDUAL:
RECEIVE
1 0 0 0 0 0 0 0 0 0 00 0 1 1 0 1
16
GOOD CRC
Y
EQUAL?
BAD CRC
N
Figure 9-7. CRC Block Diagram for Data Packets
General Release Specification
MC68HC08KL8 — Rev. 2.0
Universal Serial Bus Module (USB)
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The single-ended 0 (SE0) state is used to signal an end-of-packet
(EOP). The single-ended 0 state is indicated by both D+ and D– being
below 0.8 V. EOP will be signaled by driving D+ and D– to the singleended 0 state for two bit times followed by driving the lines to the idle
state for one bit time. The transition from the single-ended 0 to the idle
state defines the end of the packet. The idle state is asserted for one bit
time and then both the D+ and D– output drivers are placed in their highimpedance state. The bus termination resistors hold the bus in the idle
state. Figure 9-8 shows the data signaling and voltage levels for an endof-packet transaction.
LAST BIT OF
PACKET
BUS DRIVEN TO
IDLE STATE
EOP
STROBE
BUS FLOATS
BUS IDLE
VOH (MIN)
VSE (MAX)
VSE (MIN)
VOL (MAX)
A G R E E M E N T
9.3.1.6 End-of-Packet (EOP)
R E Q U I R E D
Universal Serial Bus Module (USB)
Overview
Figure 9-8. EOP Transaction Voltage Levels
The width of the SE0 in the EOP is about two bit times. The EOP width
is measured with the same capacitive load used for maximum rise and
fall times and is measured at the same level as the differential signal
crossover points of the data lines.
tPeriod
DIFFERENTIAL
DATA LINES
DATA
CROSSOVER
LEVEL
EOP
WIDTH
Figure 9-9. EOP Width Timing
MC68HC08KL8 — Rev. 2.0
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Universal Serial Bus Module (USB)
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VSS
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A G R E E M E N T
R E Q U I R E D
Universal Serial Bus Module (USB)
9.3.2 Reset Signaling
A reset is signaled on the bus by the presence of an extended SE0 at
the USB data pins of a device. The reset signaling is specified to be
present for a minimum of 10 ms. An active device (powered and not in
the suspend state) seeing a single-ended 0 on its USB data inputs for
more than 2.5 µs may treat that signal as a reset, but must have
interpreted the signaling as a reset within 5.5 µs. For a low-speed
device, an SE0 condition between four and eight low-speed bit times
represents a valid USB reset.
A USB sourced reset will hold the 68HC6808KL8 in reset for the duration
of the reset on the USB bus. The USB bit in the reset status register
(RSR) will be set after the internal reset is removed. Refer to 8.8.2 Reset
Status Register for more detail. The MCU’s reset recovery sequence is
detailed in Section 8. System Integration Module (SIM).
The reset flag bit (RSTF) in the USB interrupt register 0 (UIR0) also will
be set after the internal reset is removed. Refer to 9.6.2 USB Interrupt
Register 0 for more detail.
After a reset is removed, the device will be in the attached, but not yet
addressed or configured state (refer to Section 9.1 USB Device States
of the Universal Serial Bus Specification Rev. 1.0). The device must be
able to accept a device address via a SET_ADDRESS command (refer
to Section 9.4 Standard Device Request in the Universal Serial Bus
Specification Rev. 1.0) no later than 10 ms after the reset is removed.
Reset can wake a device from the suspended mode. A device may take
up to 10 ms to wake up from the suspended state.
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Universal Serial Bus Module (USB)
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Firmware should monitor the EOPF flag and enter suspend mode by
setting the SUSPND bit if an EOP is not detected for 3 ms.
Per the USB specification, the MC68HC08KL8 is required to draw less
than 500 µA from the VDD supply when it is in the suspend state. This
includes the current supplied by the voltage regulator to the 15 kΩ to
ground termination resistors placed at the host end of the USB bus. This
low-current requirement means that firmware is responsible for entering
stop mode once the USB module has been placed in the suspend state.
9.3.4 Resume After Suspend
The MC68HC08KL8 can be activated from the suspend state by normal
bus activity, a USB reset signal, or by a forced resume driven from the
MC68HC08KL8.
9.3.4.1 Host Initiated Resume
The host signals resume by initiating resume signalling (K state) for at
least 20 ms followed by a standard low-speed EOP signal. This 20 ms
ensures that all devices in the USB network are awakened.
After resuming the bus, the host must begin sending bus traffic within 3
ms to prevent the device from re-entering suspend mode.
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Universal Serial Bus Module (USB)
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The MC68HC08KL8 supports suspend mode for low power. Suspend
mode should be entered when the USB data lines are in the idle state for
more than 3.0 ms. Entry into suspend mode is controlled by the
SUSPND bit in the USB interrupt register. Any low-speed bus activity
should keep the device out of the suspend state. Low-speed devices are
kept awake by periodic low-speed EOP signals from the host. This is
referred to as low speed keep alive (refer to Section 11.2.5.1 of the
Universal Serial Bus Specification Rev. 1.0).
A G R E E M E N T
9.3.3 Suspend
R E Q U I R E D
Universal Serial Bus Module (USB)
Overview
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R E Q U I R E D
Universal Serial Bus Module (USB)
9.3.4.2 USB Reset Signalling
Reset can wake a device from the suspended mode. A device may take
up to 10 ms to wake up from the suspended state.
9.3.4.3 Remote Wakeup
The MC68HC08KL8 also supports the remote wakeup feature. The
firmware has the ability to exit suspend mode by signaling a resume
state to the upstream host or hub. A non-idle state (K state) on the USB
data lines is accomplished by asserting the FRESUM bit in the UCR1
register.
When using the remote wakeup capability, the firmware must wait for at
least 5 ms after the bus is in the idle state before sending the remote
wakeup resume signaling. This allows the upstream devices to get into
their suspend state and prepare for propagating resume signaling. The
FRESUM bit should be asserted to cause the resume state on the USB
data lines for at least 10 ms, but not more than 15 ms. Note that the
resume signalling is controlled by the FRESUM bit and meeting the
timing specifications is dependent on the firmware. When FRESUM is
cleared by firmware, the data lines will return to their high-impedance
state. Refer to the register definitions (see 9.6.5 USB Control Register
1) for more information about how the force resume (FRESUM) bit can
be used to initiate the remote wakeup feature.
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MC68HC08KL8 — Rev. 2.0
Universal Serial Bus Module (USB)
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9.3.5 Low-Speed Device
Externally, low-speed devices are configured by the position of a pullup
resistor on the USB D– pin of the MC68HC08KL8. Low-speed devices
are terminated as shown in Figure 9-10 with the pullup on the D– line.
3.3-V REGULATOR OUT
1.5 kΩ
.
USB LOW-SPEED CABLE
D–
Figure 9-10. External Low-Speed Device Configuration
For low-speed transmissions, the transmitter’s EOP width must be
between 1.25 µs and 1.50 µs. These ranges include timing variations
due to differential buffer delay and rise/fall time mismatches and to noise
and other random effects. A low-speed receiver must accept a 670-ns
SE0 followed by a J transition as a valid EOP. An SE0 shorter than 330
ns or an SE0 not followed by a J transition must be rejected as an EOP.
An EOP between 330 ns and 670 ns may be rejected or accepted as
discussed. Any SE0 that is 2.5 µs or longer is automatically a reset.
9.4 Clock Requirements
The low-speed data rate is nominally 1.5 Mbs. The CGMXCLK signal
driven by the oscillator circuits is the clock source for the USB module
and requires that a 6-MHz oscillator circuit be connected to the OSC1
and OSC2 pins. The permitted frequency tolerance for low-speed
functions is approximately ±1.5% (15,000 ppm). This tolerance includes
inaccuracies from all sources: initial frequency accuracy, crystal
capacitive loading, supply voltage on the oscillator, temperature, and
aging. The jitter in the low-speed data rate must be less than 10 ns. This
tolerance allows the use of resonators in low-cost, low-speed devices.
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Universal Serial Bus Module (USB)
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D+
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MC68HC08KL8
R E Q U I R E D
Universal Serial Bus Module (USB)
Clock Requirements
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R E Q U I R E D
Universal Serial Bus Module (USB)
9.5 Hardware Description
The USB module as previously shown in Figure 9-1 contains four
functional blocks: a 3.3-volt regulator, a low-speed USB transceiver, the
USB control logic, and the USB registers. The following subsections
detail the function of the regulator, transceiver, and control logic. See 9.6
I/O Register Description for the register discussion.
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A G R E E M E N T
9.5.1 Voltage Regulator
The USB data lines are required by the USB specification to have a
maximum output voltage between 2.8 V and 3.6 V. The data lines also
are required to have an external 1.5-kΩ pullup resistor connected
between data lines and a voltage source between 3.0 V and 3.6 V. Since
the power provided by the USB cable is specified to be between 4.4 V
and 5.0 V, an on-chip regulator is used to drop the voltage to the
appropriate level for sourcing the USB transceiver and external pullup
resistor. An output pin driven by the regulator voltage is provided to
source the 1.5-kΩ external resistor. The REGOUT pin requires an
external bulk capacitor 1 µF or larger and a 0.1-µF ceramic bypass
capacitor. Figure 9-11 shows the worst case electrical connection for
the voltage regulator.
4.4 V
2 CAPACITORS
— BULK CAPACITOR > 1 µF
— BYPASS CAPACITOR 0.1 µF
VDDREG
REGOUT
3.3-V
REGULATOR
USB DATA LINES
R1
D–
LOW-SPEED
TRANSCEIVER
VSSREG
HOST
OR
HUB
USB CABLE
D+
R2
R2
MC68HC08KL8
R1 = 1.5 kΩ ± 5%
R2 = 15 kΩ ± 5%
Figure 9-11. Regulator Electrical Connections
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Universal Serial Bus Module (USB)
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Under normal user operation, the REGOUT voltage is sourced from the
3.3-volt regulator. The transceiver is powered by the regulator and the
VDDREG input. For testability of the transceiver, the 3.3-volt regulator has
a bypass option that allows the REGOUT and USB transceiver power to
be sourced from the VDDREG input.
The bypass mode is to be used for transceiver testing and should not be
used in normal operation.
See Section 5. Mask Option Register (MOR) for setting the bypass
option. Figure 9-12 illustrates operation of the REGBP bit in the mask
option register.
VDDREG
REGULATOR
OFF REGBP
ON
FEEDBACK
REGOUT
TRANSCEIVER
Figure 9-12. Regulator Bypass Option
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Universal Serial Bus Module (USB)
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NOTE:
A G R E E M E N T
9.5.2 Regulator Bypass Option
R E Q U I R E D
Universal Serial Bus Module (USB)
Hardware Description
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R E Q U I R E D
Universal Serial Bus Module (USB)
9.5.3 USB Transceiver
The USB transceiver provides the physical interface to the USB D+ and
D– data lines. The transceiver is composed of two parts: an output drive
circuit and a receiver.
9.5.3.1 Output Driver Characteristics
The USB transceiver uses a differential output driver to drive the USB
data signal onto the USB cable. The static output swing of the driver in
its low state is below the VOL of 0.3 V with a 1.5-kΩ load to 3.6 V and in
its high state is above the VOH of 2.8 V with a 15-kΩ load to ground. The
output swings between the differential high and low state are well
balanced to minimize signal skew. Slew rate control on the driver is used
to minimize the radiated noise and cross talk. The driver’s outputs
support 3-state operation to achieve bidirectional half duplex operation.
The driver can tolerate a voltage on the signal pins of –0.5 V to 3.8 V with
respect to local ground reference without damage.
9.5.3.2 Low Speed (1.5 Mbs) Driver Characteristics
The rise and fall time of the signals on this cable are greater than 75 ns
to keep RFI (radio frequency interference) emissions under FCC
(Federal Communications Commission) class B limits and less than
300 ns to limit timing delays, signaling skews, and distortions. The driver
reaches the specified static signal levels with smooth rise and fall times
and minimal reflections and ringing when driving the cable. This driver is
used only on network segments between low-speed devices and the
ports to which they are connected.
USB data transmission is done with differential signals. A differential
input receiver is used to accept the USB data signal. A differential 1 on
the bus is represented by D+ being at least 200 mV more positive than
D– as seen at the receiver, and a differential 0 is represented by D–
being at least 200 mV more positive than D+ as seen at the receiver. The
signal crossover point must be between 1.3 V and 2.0 V.
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SIGNAL PINS
PASS OUTPUT SPEC
LEVELS WITH MINIMAL
REFLECTIONS AND RINGING
VSE (MAX)
VSE (MIN)
VSS
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Figure 9-13. Receiver Characteristics
MINIMUM DIFFERENTIAL SENSITIVITY (VOLTS)
The receiver features an input sensitivity of 200 mV when both
differential data inputs are in the range of 0.8 V to 2.5 V with respect to
the local ground reference. This is called the common mode input
voltage range. Proper data reception also is achieved when the
differential data lines are outside the common mode range, as shown in
Figure 9-14. The receiver can tolerate static input voltages between
–0.5 V to 3.8 V with respect to its local ground reference without
damage. In addition to the differential receiver, there is a single-ended
receiver (Schmitt trigger) for each of the two data lines.
1.0
0.8
0.6
0.4
0.2
0.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
COMMON MODE INPUT VOLTAGE (VOLTS)
Figure 9-14. Differential Input Sensitivity
Over Entire Common Mode Range
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ONE BIT
TIME
(1.5 Mb/s)
A G R E E M E N T
R E Q U I R E D
Universal Serial Bus Module (USB)
Hardware Description
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R E Q U I R E D
Universal Serial Bus Module (USB)
9.5.3.3 Receiver Data Jitter
The data receivers for all types of devices must be able to properly
decode the differential data in the presence of jitter. The more of the bit
time that any data edge can occupy and still be decoded, the more
reliable the data transfer will be. Data receivers are required to decode
differential data transitions that occur in a window plus and minus a
nominal quarter bit time from the nominal (centered) data edge position.
Jitter will be caused by the delay mismatches and by mismatches in the
source and destination data rates (frequencies). The receive data jitter
budget for low speed is given in Section 17. Electrical Specifications.
The specification includes the consecutive (next) and paired transition
values for each source of jitter.
9.5.3.4 Data Source Jitter
The source of data can have some variation (jitter) in the timing of edges
of the data transmitted. The time between any set of data transitions is
N * tPeriod ± jitter time, where N is the number of bits between the
transitions and tPeriod is defined as the actual period of the data rate. The
data jitter is measured with the same capacitive load used for maximum
rise and fall times and is measured at the crossover points of the data
lines as shown in Figure 9-15.
tPeriod
CROSSOVER
POINTS
DIFFERENTIAL
DATA LINES
CONSECUTIVE
TRANSITIONS
PAIRED
TRANSITIONS
Figure 9-15. Data Jitter
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The output rise time and fall time are measured between 10% and 90%
of the signal. Edge transition time for the rising and falling edges of lowspeed signals is 75 ns (minimum) into a capacitive load (CL) of 50 pF and
300 ns (maximum) into a capacitive load of 350 pF. The rising and falling
edges should be transitioning (monotonic) smoothly when driving the
cable to avoid excessive EMI (electro-magnetic interference).
FALL TIME
RISE TIME
CL
90%
90%
DIFFERENTIAL
DATA LINES
10%
10%
CL
tR
tF
LOW SPEED: 75 ns at CL = 50 pF, 300 ns at CL = 350 pF
Figure 9-16. Data Signal Rise and Fall Time
MC68HC08KL8 — Rev. 2.0
General Release Specification
Universal Serial Bus Module (USB)
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A G R E E M E N T
9.5.3.5 Data Signal Rise and Fall Time
N O N - D I S C L O S U R E
For low-speed transmissions, the jitter time for any consecutive
differential data transitions must be within ±25 ns and within ±10 ns for
any set of paired differential data transitions. These jitter numbers
include timing variations due to differential buffer delay, rise/fall time
mismatches, internal clock source jitter, noise and other random effects.
R E Q U I R E D
Universal Serial Bus Module (USB)
Hardware Description
Freescale Semiconductor, Inc.
9.5.4 USB Control Logic
The USB control logic manages data movement between the CPU and
the transceiver. The control logic handles both transmit and receive
operations on the USB. It contains the logic used to manipulate the
transceiver and the endpoint registers.
The byte count buffer is loaded with the active transmit endpoints byte
count value during transmit operations. This same buffer is used for
receive transactions to count the number of bytes received and, upon
the end of the transaction, transfer that number to the receive endpoints
byte count register.
When transmitting, the control logic handles parallel-to-serial
conversion, CRC generation, NRZI encoding, and bit stuffing.
When receiving, the control logic handles sync detection, packet
identification, end-of-packet detection, bit (un)stuffing, NRZI decoding,
CRC validation, and serial-to-parallel conversion. Errors detected by the
control logic include bad CRC, timeout while waiting for EOP, and bit
stuffing violations.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Universal Serial Bus Module (USB)
General Release Specification
MC68HC08KL8 — Rev. 2.0
Universal Serial Bus Module (USB)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
The USB employs NRZI data encoding when transmitting packets. In
NRZI encoding, a 1 is represented by no change in level and a 0 is
represented by a change in level. Figure 9-17 shows a data stream and
the NRZI equivalent and Figure 9-18 is a flow diagram for NRZI. The
high level represents the J state on the data lines in this and subsequent
figures showing NRZI encoding. A string of 0s causes the NRZI data to
toggle each bit time. A string of 1s causes long periods with no
transitions in the data.
0 1 10
DATA
IDLE
NRZI
IDLE
1
0
1
0
0
0
1
0
0
1
1
0
Figure 9-17. NRZI Data Encoding
POWER-UP
NO PACKET
TRANSMISSION
A G R E E M E N T
9.5.4.1 Data Encoding/Decoding
R E Q U I R E D
Universal Serial Bus Module (USB)
Hardware Description
BEGIN PACKET
TRANSMISSION
FETCH THE
DATA BIT
NO
IS DATA
BIT = 0?
NO DATA
TRANSITION
NO
YES
TRANSITION
DATA
IS PACKAGE
TRANSFER
DONE?
YES
Figure 9-18. Flow Diagram for NRZI
MC68HC08KL8 — Rev. 2.0
General Release Specification
Universal Serial Bus Module (USB)
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N O N - D I S C L O S U R E
IDLE
Freescale Semiconductor, Inc.
9.5.4.2 Bit Stuffing
To ensure adequate signal transitions, bit stuffing is employed by the
transmitting device when sending a packet on the USB (see Figure 919 and Figure 9-20). A 0 is inserted after every six consecutive 1s in the
data stream before the data is NRZI encoded to force a transition in the
NRZI data stream. This gives the receiver logic a data transition at least
once every seven bit times to guarantee the data and clock lock. The
receiver must decode the NRZI data, recognize the stuffed bits, and
discard them. Bit stuffing is enabled beginning with the sync pattern and
throughout the entire transmission. The data 1 that ends the sync pattern
is counted as the first 1 in a sequence. Bit stuffing is always enforced,
without exception. If required by the bit stuffing rules, a 0 bit will be
inserted even if it is the last bit before the end-of-packet (EOP) signal.
RAW
DATA
SYNC PATTERN
PACKET DATA
STUFFED BIT
BIT
STUFFED
DATA
NRZI
ENCODED
DATA
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Universal Serial Bus Module (USB)
PACKET DATA
SYNC PATTERN
SIX ONES
IDLE
SYNC PATTERN
PACKET DATA
Figure 9-19. Bit Stuffing
General Release Specification
MC68HC08KL8 — Rev. 2.0
Universal Serial Bus Module (USB)
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Freescale Semiconductor, Inc.
IDLE
BEGIN PACKET
TRANSMISSION
RESET BIT
COUNTER TO 0
Freescale Semiconductor, Inc...
GET NEXT
BIT
=0
=1
BIT VALUE?
INCREMENT
THE COUNTER
NO
COUNTER = 6?
YES
INSERT A
ZERO BIT
RESET THE BIT
COUNTER TO 0
NO
IS PACKAGE
TRANSFER
DONE?
YES
Figure 9-20. Flow Diagram for Bit Stuffing
9.6 I/O Register Description
The USB endpoint registers are comprised of a set of control/status
registers and 24 data registers that provide storage for the buffering of
data between USB and the CPU. See Figure 9-21.
MC68HC08KL8 — Rev. 2.0
General Release Specification
Universal Serial Bus Module (USB)
For More Information On This Product,
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A G R E E M E N T
NO PACKET
TRANSMISSION
N O N - D I S C L O S U R E
POWER-UP
R E Q U I R E D
Universal Serial Bus Module (USB)
I/O Register Description
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Universal Serial Bus Module (USB)
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$0020
Read: UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
USB Endpoint 0 Data Register 0
Write: UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
(UE0D0)
Reset:
Indeterminate after Reset
$0021
Read: UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
USB Endpoint 0 Data Register 1
Write: UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
(UE0D1)
Reset:
Indeterminate after Reset
$0022
Read: UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
USB Endpoint 0 Data Register 2
Write: UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
(UE0D2)
Reset:
Indeterminate after Reset
Read: UE0RD7 UE0RD6 UE0RD5
$0023
UE0RD3 UE0RD2 UE0RD1 UE0RD0
USB Endpoint 0 Data Register 3
Write: UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
(UE0D3)
Reset:
Indeterminate after Reset
Read: UE0RD7 UE0RD6 UE0RD5
$0024
UE0RD4
UE0RD4
UE0RD3 UE0RD2 UE0RD1 UE0RD0
USB Endpoint 0 Data Register 4
Write: UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
(UE0D4)
Reset:
Indeterminate after Reset
$0025
Read: UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
USB Endpoint 0 Data Register 5
Write: UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
(UE0D5)
Reset:
Indeterminate after Reset
$0026
Read: UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
USB Endpoint 0 Data Register 6
Write: UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
(UE0D6)
Reset:
Indeterminate after Reset
$0027
Read: UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
USB Endpoint 0 Data Register 7
Write: UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
(UE0D7)
Reset:
Indeterminate after Reset
= Unimplemented
X = Indeterminate
Figure 9-21. Register Summary (Sheet 1 of 3)
General Release Specification
MC68HC08KL8 — Rev. 2.0
Universal Serial Bus Module (USB)
For More Information On This Product,
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Freescale Semiconductor, Inc.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
USB Endpoint 1/2 Data Register 0
$0028
Write: UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
(UE1D0)
Reset:
Indeterminate after Reset
Freescale Semiconductor, Inc...
Read:
USB Endpoint 1/2 Data Register 1
$0029
Write: UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
(UE1D1)
Reset:
Indeterminate after Reset
Read:
USB Endpoint 1/2 Data Register 2
$002A
Write: UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
(UE1D2)
Reset:
Indeterminate after Reset
Read:
$002B
USB Endpoint 1/2 Data Register 3
Write: UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
(UE1D3)
Reset:
Indeterminate after Reset
Read:
$002C
USB Endpoint 1/2 Data Register 4
Write: UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
(UE1D4)
Reset:
Indeterminate after Reset
Read:
USB Endpoint 1/2 Data Register 5
$002D
Write: UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
(UE1D5)
Reset:
Indeterminate after Reset
Read:
USB Endpoint 1/2 Data Register 6
$002E
Write: UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
(UE1D6)
Reset:
Indeterminate after Reset
Read:
USB Endpoint 1/2 Data Register 7
$002F
Write: UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
(UE1D7)
Reset:
Indeterminate after Reset
= Unimplemented
X = Indeterminate
Figure 9-21. Register Summary (Sheet 2 of 3)
MC68HC08KL8 — Rev. 2.0
General Release Specification
Universal Serial Bus Module (USB)
For More Information On This Product,
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A G R E E M E N T
Register Name
N O N - D I S C L O S U R E
Addr.
R E Q U I R E D
Universal Serial Bus Module (USB)
I/O Register Description
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Universal Serial Bus Module (USB)
Addr.
$0037
$0038
$0039
$003A
Register Name
Bit 7
6
Read:
0
0
USB Control Register 2
Write: RSTFR TX1STR
(UCR2)
Reset:
0
0
5
4
TX1ST
0
3
2
0
0
0
UADD6
UADD5
UADD4
UADD3
UADD2
0
0
0
0
0
Read: TXD0F
USB Interrupt Register 0
Write:
(UIR0)
Reset:
0
RXD0F
RSTF
SUSPND
TXD0IE
RXD0IE
0
0
0
Read: TXD1F
EOPF
RESUMF
0
USB Interrupt Register 1
Write:
(UIR1)
Reset:
0
0
UADD1 UADD0
0
0
0
0
TXD0FR RXD0FR
0
0
TXD1IE
EOPIE
RESUMFR
0
Bit 0
ENABLE2 ENABLE1 STALL2 STALL1
0
Read:
USBEN
USB Address Register
Write:
(UADDR)
Reset:
0
1
0
0
0
STALL0
TX0E
RX0E
0
0
0
0
0
0
0
TXD1FR EOPFR
0
0
0
0
Read:
$003B
$003C
$003D
T0SEQ
USB Control Register 0
Write:
(UCR0)
Reset:
0
Read:
T1SEQ ENDADD
USB Control Register 1
Write:
(UCR1)
Reset:
0
0
Read: RSEQ
USB Status Register
Write:
(USR)
Reset:
X
TX1E
0
TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0
0
0
0
FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0
0
0
SETUP
RPSIZ3
RPSIZ2
X
X
X
= Unimplemented
0
0
0
0
RPSIZ1 RPSIZ0
X
X
X = Indeterminate
Figure 9-21. Register Summary (Sheet 3 of 3)
General Release Specification
MC68HC08KL8 — Rev. 2.0
Universal Serial Bus Module (USB)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
9.6.1 USB Address Register
Address:
$0038
Bit 7
6
5
4
3
2
1
Bit 0
USBEN
UADD6
UADD5
UADD4
UADD3
UADD2
UADD1
UADD0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
R E Q U I R E D
Universal Serial Bus Module (USB)
I/O Register Description
This read/write bit enables and disables the USB module and the
USB pins. When USBEN is clear, the USB module will not respond to
any traffic. Reset clears this bit.
1 = USB function enabled
0 = USB function disabled
NOTE:
The user must set this bit before the USB module will recognize USB
reset signalling.
UADD6–UADD0 — USB Function Address
These bits specify the USB address of the device. Reset clears these
bits.
MC68HC08KL8 — Rev. 2.0
General Release Specification
Universal Serial Bus Module (USB)
For More Information On This Product,
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A G R E E M E N T
USBEN — USB Module Enable
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
Figure 9-22. USB Address Register (UADDR)
Freescale Semiconductor, Inc.
R E Q U I R E D
Universal Serial Bus Module (USB)
9.6.2 USB Interrupt Register 0
Address: $0039
Read:
Bit 7
6
5
TXD0F
RXD0F
RSTF
4
3
2
SUSPND
TXD0IE
RXD0IE
Write:
Reset:
0
0
0
0
0
1
Bit 0
0
0
TXD0FR
RXD0FR
0
0
0
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
= Unimplemented
Figure 9-23. USB Interrupt Register 0 (UIR0)
TXD0F — Endpoint 0 Data Transmit Flag
This read-only bit is set after the data stored in endpoint 0 transmit
buffers has been sent and an ACK handshake packet from the host is
received. Once the next set of data is ready in the transmit buffers,
software must clear this flag by writing a logic 1 to the TXD0FR bit. To
enable the next data packet transmission, TX0E also must be set. If
the TXD0F bit is not cleared, a NAK handshake will be returned in the
next IN transaction.
Reset clears this bit. Writing to TXD0F has no effect.
1 = Transmit on endpoint 0 has occurred.
0 = Transmit on endpoint 0 has not occurred.
RXD0F — Endpoint 0 Data Receive Flag
This read-only bit is set after the USB module has received a data
packet and responded with an ACK handshake packet. Software
must clear this flag by writing a logic 1 to the RXD0FR bit after all of
the received data has been read. Software also must set the RX0E bit
to 1 to enable the next data packet reception. If the RXD0F bit is not
cleared, a NAK handshake will be returned in the next OUT
transaction.
Reset clears this bit. Writing to RXD0F has no effect.
1 = Receive on endpoint 0 has occurred.
0 = Receive on endpoint 0 has not occurred.
General Release Specification
MC68HC08KL8 — Rev. 2.0
Universal Serial Bus Module (USB)
For More Information On This Product,
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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
NOTE:
The RSTF bit is included to maintain backward compatibility with the
68HC705JB2 USB implementation. The USB bit in the RSR register
(see 8.8.2 Reset Status Register) is also a USB reset indicator.
SUSPND — USB Suspend Flag
To save power, this read/write bit should be set by the software if a
3-ms constant idle state is detected on the USB bus. Setting this bit
puts the transceiver and regulator into a power-saving mode. This bit
is automatically cleared by hardware when the resume flag
(RESUMF) is set.
TXD0IE — Endpoint 0 Transmit Interrupt Enable
This read/write bit enables the transmit endpoint 0 to generate CPU
interrupt requests when the TXD0F bit becomes set. Reset clears the
TXD0IE bit.
1 = Transmit endpoint 0 can generate a CPU interrupt request.
0 = Transmit endpoint 0 cannot generate a CPU interrupt request.
RXD0IE — Endpoint 0 Receive Interrupt Enable
This read/write bit enables the receive endpoint 0 to generate CPU
interrupt requests when the RXD0F bit becomes set. Reset clears the
RXD0IE bit.
1 = Receive endpoint 0 can generate a CPU interrupt request.
0 = Receive endpoint 0 cannot generate a CPU interrupt request.
TXD0FR — Endpoint 0 Transmit Flag Reset
Writing a logic 1 to this write-only bit will clear the TXD0F bit if it is set.
Writing a logic 0 to TXD0FR has no effect. Reset clears this bit.
RXD0FR — Endpoint 0 Receive Flag Reset
Writing a logic 1 to this write-only bit will clear the RXD0F bit if it is set.
Writing a logic 0 to RXD0FR has no effect. Reset clears this bit.
MC68HC08KL8 — Rev. 2.0
General Release Specification
Universal Serial Bus Module (USB)
For More Information On This Product,
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A G R E E M E N T
This read-only bit is set when a valid reset signal state is detected on
the D+ and D– lines. This reset detection will also generate an internal
reset signal to reset the CPU and other peripherals including the USB
module. This bit is cleared by writing a logic 1 to the RSTFR bit in the
UCR2 register. This bit also is cleared by a POR reset.
N O N - D I S C L O S U R E
RSTF — USB Reset Flag
R E Q U I R E D
Universal Serial Bus Module (USB)
I/O Register Description
Freescale Semiconductor, Inc.
R E Q U I R E D
Universal Serial Bus Module (USB)
9.6.3 USB Interrupt Register 1
Address:
Read:
$003A
Bit 7
6
5
4
TXD1F
EOPF
RESUMF
0
Write:
Reset:
3
2
TXD1IE
EOPIE
RESUMFR
0
0
0
0
0
1
Bit 0
0
0
TXD1FR
EOPFR
0
0
0
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
= Unimplemented
Figure 9-24. USB Interrupt Register 1 (UIR1)
TXD1F — Endpoint 1/Endpoint 2 Data Transmit Flag
This read-only bit is shared by endpoint 1 and endpoint 2. It is set after
the data stored in the shared endpoint 1/endpoint 2 transmit buffer
has been sent and an ACK handshake packet from the host is
received. Once the next set of data is ready in the transmit buffers,
software must clear this flag by writing a logic 1 to the TXD1FR bit. To
enable the next data packet transmission, TX1E also must be set. If
the TXD1F bit is not cleared, a NAK handshake will be returned in the
next IN transaction.
Reset clears this bit. Writing to TXD1F has no effect.
1 = Transmit on endpoint 1 or endpoint 2 has occurred.
0 = Transmit on endpoint 1 or endpoint 2 has not occurred.
EOPF — End-of-Packet Detect Flag
This read-only bit is set when a valid end-of-packet sequence is
detected on the D+ and D– lines. Software must clear this flag by
writing a logic 1 to the EOPFR bit.
Reset clears this bit. Writing to EOPF has no effect.
1 = End-of-packet sequence has been detected.
0 = End-of-packet sequence has not been detected.
General Release Specification
MC68HC08KL8 — Rev. 2.0
Universal Serial Bus Module (USB)
For More Information On This Product,
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Freescale Semiconductor, Inc.
RESUMF — Resume Flag
This read-only bit is set when USB bus activity is detected while the
SUSPND bit is set. Software must clear this flag by writing a logic 1 to
the RESUMFR bit.
Reset clears this bit. Writing a logic 0 to RESUMF has no effect.
1 = USB bus activity has been detected.
0 = No USB bus activity has been detected.
R E Q U I R E D
Universal Serial Bus Module (USB)
I/O Register Description
Freescale Semiconductor, Inc...
Writing a logic 1 to this write-only bit will clear the RESUMF bit if it is
set. Writing to RESUMFR has no effect. Reset clears this bit.
TXD1IE — Endpoint 1/Endpoint 2 Transmit Interrupt Enable
This read/write bit enables the USB to generate CPU interrupt
requests when the shared transmit endpoint 1/endpoint 2 interrupt
flag (TXD1F) bit becomes set. Reset clears the TXD1IE bit.
1 = Transmit endpoints 1 and 2 can generate a CPU interrupt
request.
0 = Transmit endpoints 1 and 2 cannot generate a CPU interrupt
request.
A G R E E M E N T
RESUMFR — Resume Flag Reset
This read/write bit enables the USB to generate CPU interrupt
requests when the EOPF bit becomes set. Reset clears the EOPIE
bit.
1 = End-of-packet sequence detection can generate a CPU
interrupt request.
0 = End-of-packet sequence detection cannot generate a CPU
interrupt request.
TXD1FR — Endpoint 1/Endpoint 2 Transmit Flag Reset
Writing a logic 1 to this write-only bit will clear the TXD1F bit if it is set.
Writing a logic 0 to TXD1FR has no effect. Reset clears this bit.
EOPFR — End-of-Packet Flag Reset
Writing a logic 1 to this write-only bit will clear the EOPF bit if it is set.
Writing a logic 0 to the EOPFR has no effect. Reset clears this bit.
MC68HC08KL8 — Rev. 2.0
General Release Specification
Universal Serial Bus Module (USB)
For More Information On This Product,
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N O N - D I S C L O S U R E
EOPIE — End-of-Packet Detect Interrupt Enable
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Universal Serial Bus Module (USB)
9.6.4 USB Control Register 0
Address:
$003B
Bit 7
6
5
4
3
2
1
Bit 0
T0SEQ
STALL0
TX0E
RX0E
TP0SIZ3
TP0SIZ2
TP0SIZ1
TP0SIZ0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 9-25. USB Control Register 0 (UCR0)
T0SEQ — Endpoint 0 Transmit Sequence Bit
This read/write bit determines which type of data packet (DATA0 or
DATA1) will be sent during the next IN transaction directed at
endpoint 0. Toggling of this bit must be controlled by software. Reset
clears this bit.
1 = DATA1 token active for next endpoint 0 transmit
0 = DATA0 token active for next endpoint 0 transmit
STALL0 — Endpoint 0 Force Stall Bit
This read/write bit causes endpoint 0 to return a STALL handshake
when polled by either an IN or OUT token by the USB host controller.
The USB hardware clears this bit when a SETUP token is received.
Reset clears this bit.
1 = Send STALL handshake.
0 = Default
TX0E — Endpoint 0 Transmit Enable
This read/write bit enables a transmit to occur when the USB host
controller sends an IN token to endpoint 0. Software should set this
bit when data is ready to be transmitted. It must be cleared by
software when no more endpoint 0 data needs to be transmitted.
If this bit is 0 or the TXD0F is set, the USB will respond with a NAK
handshake to any endpoint 0 IN tokens. Reset clears this bit.
1 = Data is ready to be sent.
0 = Data is not ready. Respond with NAK.
General Release Specification
MC68HC08KL8 — Rev. 2.0
Universal Serial Bus Module (USB)
For More Information On This Product,
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Freescale Semiconductor, Inc.
This read/write bit enables a receive to occur when the USB host
controller sends an OUT token to endpoint 0. Software should set this
bit when data is ready to be received. It must be cleared by software
when data cannot be received.
Freescale Semiconductor, Inc...
If this bit is 0 or the RXD0F is set, the USB will respond with a NAK
handshake to any endpoint 0 OUT tokens. Reset clears this bit.
1 = Data is ready to be received.
0 = Not ready for data. Respond with NAK.
TP0SIZ3–TP0SIZ0 — Endpoint 0 Transmit Data Packet Size
N O N - D I S C L O S U R E
These read/write bits store the number of transmit data bytes for the
next IN token request for endpoint 0. These bits are cleared by reset.
A G R E E M E N T
RX0E — Endpoint 0 Receive Enable
R E Q U I R E D
Universal Serial Bus Module (USB)
I/O Register Description
MC68HC08KL8 — Rev. 2.0
General Release Specification
Universal Serial Bus Module (USB)
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9.6.5 USB Control Register 1
Address:
$003C
Bit 7
6
5
T1SEQ
ENDADD
TX1E
0
0
0
4
3
2
1
Bit 0
TP1SIZ2
TP1SIZ1
TP1SIZ0
0
0
0
Read:
FRESUM TP1SIZ3
Write:
Reset:
0
0
Figure 9-26. USB Control Register 1 (UCR1)
T1SEQ — Endpoint1/Endpoint 2 Transmit Sequence Bit
This read/write bit determines which type of data packet (DATA0 or
DATA1) will be sent during the next IN transaction directed to
endpoint 1 or endpoint 2. Toggling of this bit must be controlled by
software. Reset clears this bit.
1 = DATA1 token active for next endpoint 1/endpoint 2 transmit
0 = DATA0 token active for next endpoint 1/endpoint 2 transmit
ENDADD — Endpoint Address Select
This read/write bit specifies whether the data inside the registers
UE1D0–UE1D7 are used for endpoint 1 or endpoint 2.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Universal Serial Bus Module (USB)
If all the conditions for a successful endpoint 2 USB response to a
host IN token are satisfied (TXD1F = 0, TX1E = 1, STALL2 = 0, and
ENABLE2 = 1) except that the ENDADD bit is configured for endpoint
1, the USB responds with a NAK handshake packet.
1 = Data buffers used for endpoint 2
0 = Data buffers used for endpoint 1
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MC68HC08KL8 — Rev. 2.0
Universal Serial Bus Module (USB)
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This read/write bit enables a transmit to occur when the USB host
controller sends an IN token to endpoint 1 or endpoint 2. The
appropriate endpoint enable bit, ENABLE1 or ENABLE2 bit in the
UCR2 register, also should be set. Software should set the TX1E bit
when data is ready to be transmitted. It must be cleared by software
when no more data needs to be transmitted.
Freescale Semiconductor, Inc...
If this bit is 0 or the TXD1F is set, the USB will respond with a NAK
handshake to any endpoint 1 or endpoint 2 directed IN tokens. Reset
clears this bit.
1 = Data is ready to be sent.
0 = Data is not ready. Respond with NAK.
FRESUM — Force Resume
This read/write bit forces a resume state (K or non-idle state) onto the
USB data lines to initiate a remote wakeup. Software should control
the timing of the forced resume to be between 10 and 15 ms. Setting
this bit will not cause the RESUMF bit to be set.
1 = Force data lines to K state
0 = Default
A G R E E M E N T
TX1E — Endpoint 1/Endpoint 2 Transmit Enable
R E Q U I R E D
Universal Serial Bus Module (USB)
I/O Register Description
These read/write bits store the number of transmit data bytes for the
next IN token request for endpoint 1 or endpoint 2. These bits are
cleared by reset.
MC68HC08KL8 — Rev. 2.0
General Release Specification
Universal Serial Bus Module (USB)
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N O N - D I S C L O S U R E
TP1SIZ3–TP1SIZ0 — Endpoint 1/Endpoint 2 Transmit Data Packet Size
Freescale Semiconductor, Inc.
R E Q U I R E D
Universal Serial Bus Module (USB)
9.6.6 USB Control Register 2
Address:
$0037
Bit 7
6
5
4
Read:
0
0
TX1ST
0
Write:
RSTFR
TX1STR
Reset:
0
0
3
2
ENABLE2 ENABLE1
0
0
0
1
Bit 0
STALL2
STALL1
0
0
0
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
= Unimplemented
Figure 9-27. USB Control Register 2 (UCR2)
RSTFR — Clear Reset Indicator Bit
Writing a logic 1 to this write-only bit will clear the RSTF bit in the UIR0
register if it is set. Writing a logic 0 to the RSTFR has no effect. Reset
clears this bit.
TX1STR — Clear Transmit First Flag
Writing a logic 1 to this write-only bit will clear the TX1ST bit if it is set.
Writing a logic 0 to the TX1STR has no effect. Reset clears this bit.
TX1ST — Transmit First Flag
This read-only bit is set if the endpoint 0 data transmit flag (TXD0F) is
set when the USB control logic is setting the endpoint 0 data receive
flag (RXD0F). In other words, if an unserviced endpoint 0 transmit flag
is still set at the end of an endpoint 0 reception, then this bit will be set.
This bit lets the firmware know that the endpoint 0 transmission
happened before the endpoint 0 reception.
Reset clears this bit.
1 = IN transaction occurred before SETUP/OUT.
0 = IN transaction occurred after SETUP/OUT.
ENABLE2 — Endpoint 2 Enable
This read/write bit enables endpoint 2 and allows the USB to respond
to IN packets addressed to endpoint 2. Reset clears this bit.
1 = Endpoint 2 is enabled and can respond to an IN token.
0 = Endpoint 2 is disabled.
General Release Specification
MC68HC08KL8 — Rev. 2.0
Universal Serial Bus Module (USB)
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This read/write bit enables endpoint 1 and allows the USB to respond
to IN packets addressed to endpoint 1. Reset clears this bit.
1 = Endpoint 1 is enabled and can respond to an IN token.
0 = Endpoint 1 is disabled.
STALL2 — Endpoint 2 Force Stall Bit
Freescale Semiconductor, Inc...
This read/write bit causes endpoint 2 to return a STALL handshake
when polled by either an IN or OUT token by the USB host controller.
Reset clears this bit.
1 = Send STALL handshake.
0 = Default
STALL1 — Endpoint 1 Force Stall Bit
N O N - D I S C L O S U R E
This read/write bit causes endpoint 1 to return a STALL handshake
when polled by either an IN or OUT token by the USB host controller.
Reset clears this bit.
1 = Send STALL handshake.
0 = Default
A G R E E M E N T
ENABLE1 — Endpoint 1 Enable
R E Q U I R E D
Universal Serial Bus Module (USB)
I/O Register Description
MC68HC08KL8 — Rev. 2.0
General Release Specification
Universal Serial Bus Module (USB)
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R E Q U I R E D
Universal Serial Bus Module (USB)
9.6.7 USB Status Register
Address:
Read:
$003D
Bit 7
6
RSEQ
X
5
4
3
2
1
Bit 0
SETUP
RPSIZ3
RPSIZ2
RPSIZ1
RPSIZ0
X
X
X
X
X
Write:
Reset:
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
= Unimplemented
X = Indeterminate
Figure 9-28. USB Status Register (USR)
RSEQ — Endpoint 0 Receive Sequence Bit
This read-only bit indicates the type of data packet last received for
endpoint 0 (DATA0 or DATA1).
1 = DATA1 token received in last endpoint 0 receive.
0 = DATA0 token received in last endpoint 0 receive.
SETUP — SETUP Token Detect Bit
This read-only bit indicates that a valid SETUP token has been
received.
1 = Last token received for endpoint 0 was a SETUP token.
0 = Last token received for endpoint 0 was not a SETUP token.
RPSIZ3–RPSIZ0 — Endpoint 0 Receive Data Packet Size
These read-only bits store the number of data bytes received for the
last OUT or SETUP transaction for endpoint 0. These bits are not
affected by reset.
General Release Specification
MC68HC08KL8 — Rev. 2.0
Universal Serial Bus Module (USB)
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9.6.8 USB Endpoint 0 Data Registers
UE0D0
Address: $0020
Bit 7
6
5
4
3
2
1
Bit 0
Read: UE0RD7
UE0RD6
UE0RD5
UE0RD4
UE0RD3
UE0RD2
UE0RD1
UE0RD0
Write: UE0TD7
UE0TD6
UE0TD5
UE0TD4
UE0TD3
UE0TD2
UE0TD1
UE0TD0
X
X
X
X
X
X
X
X
↓
UE0D7
Address: $0027
Read: UE0RD7
UE0RD6
UE0RD5
UE0RD4
UE0RD3
UE0RD2
UE0RD1
UE0RD0
Write: UE0TD7
UE0TD6
UE0TD5
UE0TD4
UE0TD3
UE0TD2
UE0TD1
UE0TD0
X
X
X
X
X
X
X
Reset:
X
X = Indeterminate
Figure 9-29. USB Endpoint 0 Data Register (UE0D0–UE0D7)
UE0RD7–UE0RD0 — Endpoint 0 Receive Data Buffer
These read-only bits are serially loaded with OUT token or SETUP
token data directed at endpoint 0. The data is received over the USB’s
D+ and D– pins.
UE0TD7–UE0TD0 — Endpoint 0 Transmit Data Buffer
These write-only buffers are loaded by software with data to be sent
on the USB bus on the next IN token directed at endpoint 0.
MC68HC08KL8 — Rev. 2.0
General Release Specification
Universal Serial Bus Module (USB)
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A G R E E M E N T
↓
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
Reset:
R E Q U I R E D
Universal Serial Bus Module (USB)
I/O Register Description
Freescale Semiconductor, Inc.
9.6.9 USB Endpoint 1/Endpoint 2 Data Registers
UE1D0
Address: $0028
Bit 7
6
5
4
3
2
1
Bit 0
UE1TD6
UE1TD5
UE1TD4
UE1TD3
UE1TD2
UE1TD1
UE1TD0
X
X
X
X
X
X
X
Read:
Write: UE1TD7
Reset:
X
↓
↓
UE1D7
Address: $002F
Bit 7
6
5
4
3
2
1
Bit 0
UE1TD6
UE1TD5
UE1TD4
UE1TD3
UE1TD2
UE1TD1
UE1TD0
X
X
X
X
X
X
X
Read:
Write: UE1TD7
Reset:
X
= Unimplemented
X = Indeterminate
Figure 9-30. USB Endpoint 1/Endpoint 2 Data Register
(UE1D0–UE1D7)
UE1TD7–UE1TD0 — Endpoint 1/ Endpoint 2 Transmit Data Buffer
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Universal Serial Bus Module (USB)
These write-only buffers are loaded by software with data to be sent
on the USB bus on the next IN token directed at endpoint 1 or
endpoint 2. These buffers are shared by endpoints 1 and 2 and
depend on proper configuration of the ENDADD bit.
General Release Specification
MC68HC08KL8 — Rev. 2.0
Universal Serial Bus Module (USB)
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•
End-of-transaction interrupts — signify either a completed receive
or transmit transaction
•
Resume interrupts — signify that the USB bus is reactivated after
having been suspended
•
End-of-packet interrupts — signify that a low-speed end-of-packet
signal was detected
All USB interrupts share the same interrupt vector. Firmware is
responsible for determining which interrupt is active.
9.7.1 USB End-of-Transaction Interrupt
There are three possible end-of-transaction interrupts:
•
Endpoint 0 receive
•
Endpoint 0 transmit
•
Shared endpoint 1 or endpoint 2 transmit
End-of-transaction interrupts occur as detailed in the following sections.
9.7.1.1 Receive Control Endpoint 0
For a control OUT transaction directed at endpoint 0, the USB module
will generate an interrupt by setting the RXD0F flag in the UIR0 register.
The conditions necessary for the interrupt to occur are shown in the
flowchart in Figure 9-31.
SETUP transactions cannot be stalled by the USB function. A SETUP
received by a control endpoint will clear the STALL0 bit if it is set. The
conditions for receiving a SETUP interrupt are shown in Figure 9-32.
MC68HC08KL8 — Rev. 2.0
General Release Specification
Universal Serial Bus Module (USB)
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A G R E E M E N T
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The USB module is capable of generating interrupts and causing the
CPU to execute the USB interrupt service routine. The three types of
USB interrupts are:
N O N - D I S C L O S U R E
9.7 USB Interrupts
R E Q U I R E D
Universal Serial Bus Module (USB)
USB Interrupts
Freescale Semiconductor, Inc.
R E Q U I R E D
Universal Serial Bus Module (USB)
VALID OUT TOKEN
RECEIVED FOR ENDPOINT 0
VALID DATA TOKEN
RECEIVED FOR ENDPOINT 0?
N
TIMEOUT
NO RESPONSE
FROM USB FUNCTION
Y
N
NO RESPONSE
FROM USB FUNCTION
N
SEND STALL
HANDSHAKE
ENDPOINT 0 RECEIVE READY TO RECEIVE? N
(RX0E = 1) AND (RXD0F = 0)
SEND NAK
HANDSHAKE
USB MODULE ENABLED?
(USBEN = 1)
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
Y
ENDPOINT 0 RECEIVE NOT STALLED?
(STALL0 = 0)
Y
Y
ACCEPT DATA
SET/CLEAR RSEQ BIT
ERROR FREE DATA PACKET?
N
IGNORE TRANSACTION
NO RESPONSE FROM
USB FUNCTION
Y
SET RXD0F TO 1
RECEIVE CONTROL ENDPOINT
INTERRUPT ENABLED?
(RXD0IE = 1)
N
Y
VALID TRANSACTION
INTERRUPT GENERATED
NO INTERRUPT
Figure 9-31. OUT Token Data Flow for Receive Endpoint 0
General Release Specification
MC68HC08KL8 — Rev. 2.0
Universal Serial Bus Module (USB)
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R E Q U I R E D
Universal Serial Bus Module (USB)
USB Interrupts
VALID SETUP TOKEN
RECEIVED FOR ENDPOINT 0
Y
USB MODULE ENABLED?
(USBEN = 1)
N
NO RESPONSE
FROM USB FUNCTION
N
NO RESPONSE
FROM USB FUNCTION
Y
N
STALL0 = 0?
A G R E E M E N T
Y
CLEAR STALL0 BIT
Y
ACCEPT DATA
SET/CLEAR RSEQ BIT
SET SETUP TO 1
ERROR FREE DATA PACKET?
N
IGNORE TRANSACTION
NO RESPONSE FROM
USB FUNCTION
Y
SET RXD0F TO 1
RECEIVE CONTROL ENDPOINT
INTERRUPT ENABLED?
(RXD0IE = 1)
N
Y
VALID TRANSACTION
INTERRUPT GENERATED
NO INTERRUPT
Figure 9-32. SETUP Token Data Flow for Receive Endpoint 0
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Universal Serial Bus Module (USB)
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N O N - D I S C L O S U R E
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ENDPOINT 0 RECEIVE READY TO RECEIVE?
(RX0E = 1) AND (RXD0F = 0)
Freescale Semiconductor, Inc.
9.7.1.2 Transmit Control Endpoint 0
For a control IN transaction directed at endpoint 0, the USB module will
generate an interrupt by setting the TXD0F flag in the UIR0 register. The
conditions necessary for the interrupt to occur are shown in the flowchart
in Figure 9-33.
VALID IN TOKEN
RECEIVED FOR ENDPOINT 0
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Universal Serial Bus Module (USB)
N ENABLED?
USB MODULE
(USBEN = 1)
NO RESPONSE
FROM USB FUNCTION
Y
TRANSMIT ENDPOINT NOT STALLED
BY FIRMWARE?
(STALL0 = 0)
N
SEND STALL
HANDSHAKE
N
SEND NAK
HANDSHAKE
Y
TRANSMIT ENDPOINT READY TO TRANSFER?
(TX0E = 1) AND (TXD0F = 0)
Y
N O N - D I S C L O S U R E
SEND DATA
DATA PID SET BY T0SEQ
ACK RECEIVED AND NO
TIMEOUT CONDITION OCCUR?
N
NO RESPONSE
FROM USB FUNCTION
Y
SET TXD0F TO 1
TRANSMIT ENDPOINT
INTERRUPT ENABLED?
(TXD0IE = 1)
N
Y
NO INTERRUPT
VALID TRANSACTION
INTERRUPT GENERATED
Figure 9-33. IN Token Data Flow for Transmit Endpoint 0
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MC68HC08KL8 — Rev. 2.0
Universal Serial Bus Module (USB)
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9.7.1.3 Transmit Endpoint 1 and Transmit Endpoint 2
Transmit endpoints 1 and 2 share their interrupt flag. For an IN
transaction directed at endpoint 1 or 2, the USB module will generate an
interrupt by setting the TXD1F flag in the UIR1 register. The conditions
necessary for the interrupt to occur are shown in Figure 9-34.
NOTES:
ENDP1 is endpoint 1 directed traffic.
ENDP2 is endpoint 2 directed traffic.
VALID IN TOKEN
RECEIVED FOR ENDPOINTS 1 OR 2
R E Q U I R E D
Universal Serial Bus Module (USB)
USB Interrupts
USB MODULE ENABLED?
(USBEN = 1)
N
NO RESPONSE
FROM USB FUNCTION
N
SEND STALL
HANDSHAKE
N
SEND NAK
HANDSHAKE
N
NO RESPONSE
FROM USB FUNCTION
N
NO RESPONSE
FROM USB FUNCTION
Y
TRANSMIT ENDPOINT NOT STALLED BY FIRMWARE?
(STALL1 AND ENDP1) + (STALL2 AND ENDP2)
Y
TRANSMIT ENDPOINT READY TO TRANSFER?
(TX1E = 1) AND (TXD1F = 0) AND
((ENDP2 AND ENDADD) + (ENDP1 AND ENDADD))
Y
TRANSMIT ENDPOINT ENABLED?
((ENABLE1 AND ENDP1) + (ENABLE2 AND ENDP2))
A G R E E M E N T
Freescale Semiconductor, Inc...
Y
SEND DATA
DATA PID SET BY T1SEQ
ACK RECEIVED AND NO
TIMEOUT CONDITION OCCURS?
Y
SET TXD1F TO 1
TRANSMIT ENDPOINT INTERRUPT ENABLED
(TXD1IE = 1)
NO INTERRUPT
VALID TRANSACTION
INTERRUPT GENERATED
Figure 9-34. IN Token Data Flow for Transmit Endpoint 1/Endpoint 2
MC68HC08KL8 — Rev. 2.0
General Release Specification
Universal Serial Bus Module (USB)
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N O N - D I S C L O S U R E
Y
Freescale Semiconductor, Inc.
9.7.2 Resume Interrupt
The USB module will generate a CPU interrupt if low-speed bus activity
is detected after entering the suspend state. A transition of the USB data
lines to the non-idle state (K state) while in the suspend mode will set the
RESUMF flag in the UIR1 register. There is no interrupt enable bit for this
interrupt source and an interrupt will be executed if the I bit in the CCR
is cleared. A resume interrupt can only occur while the MC68HC08KL8
is in the suspend mode.
9.7.3 End-of-Packet Interrupt
The USB module can generate a USB interrupt upon detection of an
end-of-packet signal for low-speed devices. Upon detection of an endof-packet signal, the USB module sets the EOPF bit and will generate a
CPU interrupt if the EOPIE bit in the UIR1 register is set.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Universal Serial Bus Module (USB)
General Release Specification
MC68HC08KL8 — Rev. 2.0
Universal Serial Bus Module (USB)
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Section 10. Monitor ROM (MON)
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
10.4.1
Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .154
10.4.2
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
10.4.3
Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
10.4.4
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
10.4.5
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
10.5
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
10.2 Introduction
This section describes the monitor ROM. The monitor ROM allows
complete testing of the MCU through a single-wire interface with a host
computer.
MC68HC08KL8 — Rev. 2.0
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Monitor ROM (MON)
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N O N - D I S C L O S U R E
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10.1 Contents
A G R E E M E N T
General Release Specification — MC68HC08KL8
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Monitor ROM (MON)
10.3 Features
Features of the monitor ROM include:
•
Normal User-Mode Pin Functionality
•
One Pin Dedicated to Serial Communication between Monitor
ROM and Host Computer
•
Standard Mark/Space Non-Return-to-Zero (NRZ) Communication
with Host Computer
•
Execution of Code in RAM or ROM
•
ROM Security
10.4 Functional Description
The monitor ROM receives and executes commands from a host
computer. Figure 10-1 shows an example circuit used to enter monitor
mode and communicate with a host computer via a standard RS-232
interface.
Simple monitor commands can access any memory address. In monitor
mode, the MCU can execute host-computer code in RAM while all MCU
pins retain normal operating mode functions. All communication
between the host computer and the MCU is through the PTA0 pin. A
level-shifting and multiplexing interface is required between PTA0 and
the host computer. PTA0 is used in a wired-OR configuration and
requires a pullup resistor.
General Release Specification
MC68HC08KL8 — Rev. 2.0
Monitor ROM (MON)
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Freescale Semiconductor, Inc.
68HC08
10 kΩ
RST
0.1 µF
VTST
10 Ω
VDD
VDDREG
0.1 µF
1
10 µF
10 µF
MC145407
20
+
+
+
3
18
4
17
2
19
10 µF
OSC1
+
10 µF
VDD
20 pF
X1
4.9152 MHz
10 MΩ
OSC2
20 pF
DB-25
2
5
16
3
6
15
VSS2
VSS1
VSSREG
VDD
VDD1, VDD2
7
0.1 µF
VDD
1
MC74HC125
14
2
3
6
5
VDD
10 kΩ
PTA0
4
7
NOTES:
Position A — Bus clock = CGMXCLK ÷ 4
Position B — Bus clock = CGMXCLK ÷ 2
PTC3
VDD
VDD
10 kΩ
A
(See
NOTES)
10 kΩ
B
PTC0
PTC1
Figure 10-1. Monitor Mode Circuit
MC68HC08KL8 — Rev. 2.0
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Monitor ROM (MON)
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IRQ1
A G R E E M E N T
VDD
R E Q U I R E D
Monitor ROM (MON)
Functional Description
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
10.4.1 Entering Monitor Mode
Table 10-1 shows the pin conditions for entering monitor mode.
VTST
0
1
0
PTA0 Pin
PTC1 Pin
PTC0 Pin
PTA7 Pin
IRQ1 Pin
Table 10-1. Monitor Mode Entry
PTC3 Pin
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Monitor ROM (MON)
CGMOUT
1
CGMXCLK
----------------------------2
0
CGMXCLK
1
Bus
Frequency
CGMOUT
-------------------------2
If PTC3 is low upon monitor mode entry, CGMOUT is equal to the crystal
frequency. The bus frequency in this case is a divide-by-two of the input
clock. If PTC3 is high upon monitor mode entry, the bus frequency will
be a divide-by-four of the input clock.
NOTE:
Holding the PTC3 pin low when entering monitor mode causes a bypass
of a divide-by-two stage at the oscillator. The CGMOUT frequency is
equal to the CGMXCLK frequency, and the OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have
a 50% duty cycle at maximum bus frequency.
Enter monitor mode with the pin configuration shown above by pulling
RST low and then high. The rising edge of RST latches monitor mode.
Once monitor mode is latched, the values on the specified pins can
change.
NOTE:
The PTA7 pin must remain at logic 0 for 24 bus cycles after the RST pin
goes high.
Once out of reset, the MCU waits for the host to send eight security
bytes. (See 10.5 Security.) After the security bytes, the MCU sends a
break signal (10 consecutive logic 0s) to the host, indicating that it is
ready to receive a command.
General Release Specification
MC68HC08KL8 — Rev. 2.0
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The COP module is disabled in monitor mode as long as VTST is applied
to either the IRQ pin or the RST pin.
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Table 10-2 summarizes the differences between user mode and monitor
mode.
Table 10-2. Mode Differences
Functions
Modes
COP
Reset
Vector
High
Reset
Vector
Low
Break
Vector
High
Break
Vector
Low
SWI
Vector
High
SWI
Vector
Low
User
Enabled
$FFFE
$FFFF
$FFFC
$FFFD
$FFFC
$FFFD
Monitor
Disabled(1)
$FEFE
$FEFF
$FEFC
$FEFD
$FEFC
$FEFD
N O N - D I S C L O S U R E
1. If the high voltage (VTST) is removed from the IRQ1 pin or the RST pin, the SIM asserts its
COP enable output. The COP is a mask option enabled or disabled by the COPD bit in the
mask option register.
A G R E E M E N T
In monitor mode, the MCU uses different vectors for reset, SWI, and
break interrupt than those for user mode. The alternate vectors are in the
$FE page instead of the $FF page and allow code execution from the
internal monitor firmware instead of user code.
R E Q U I R E D
Monitor ROM (MON)
Functional Description
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10.4.2 Data Format
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. Transmit and receive baud rates must
be identical.
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 6
BIT 5
BIT 7
STOP
BIT
NEXT
START
BIT
Figure 10-2. Monitor Data Format
10.4.3 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When
the monitor receives a break signal, it drives the PTA0 pin high for the
duration of two bits and then echoes back the break signal.
MISSING STOP BIT
2-STOP BIT DELAY BEFORE ZERO ECHO
0
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Monitor ROM (MON)
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 10-3. Break Transaction
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10.4.4 Baud Rate
The communication baud rate is controlled by the crystal frequency and
the state of the PTC3 pin upon entry into monitor mode. When PTC3 is
high, the divide by ratio is 1024. If the PTC3 pin is at logic 0 upon entry
into monitor mode, the divide by ratio is 512. Table 10-3 lists crystal
frequencies required to achieve standard baud rates. Other standard
baud rates can be accomplished using higher crystal frequencies.
R E Q U I R E D
Monitor ROM (MON)
Functional Description
PTC3 Pin
Baud Rate
4.9152
0
9600
4.9152
1
4800
10.4.5 Commands
The monitor ROM firmware uses these commands:
•
READ (read memory)
•
WRITE (write memory)
•
IREAD (indexed read)
•
IWRITE (indexed write)
•
READSP (read stack pointer)
•
RUN (run user program)
The monitor ROM firmware echoes each received byte back to the PTA0
pin for error checking. An 11-bit delay at the end of each command
allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ,
IREAD, or READSP data is returned. The data returned by a read
command appears after the echo of the last byte of the command.
NOTE:
Wait one bit time after each echo before sending the next byte.
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A G R E E M E N T
Crystal
Frequency
(MHz)
N O N - D I S C L O S U R E
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Table 10-3. Monitor Baud Rate Selection
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FROM
HOST
4
ADDRESS
HIGH
READ
READ
4
1
ADDRESS
HIGH
1
ADDRESS
LOW
4
ADDRESS
LOW
DATA
1
3, 2
4
ECHO
RETURN
NOTES:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
3 = Cancel command delay, 11 bit times
4 = Wait 1 bit time before sending next byte
Figure 10-4. Read Transaction
FROM
HOST
4
ADDRESS
HIGH
WRITE
WRITE
1
4
ADDRESS
HIGH
1
ADDRESS
LOW
4
ADDRESS
LOW
1
DATA
DATA
4
1
3, 4
ECHO
NOTES:
1 = Echo delay, 2 bit times
3 = Cancel command delay, 11 bit times
4 = Wait 1 bit time before sending next byte
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Monitor ROM (MON)
Figure 10-5. Write Transaction
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A brief description of each monitor mode command is shown in Table
10-4, Table 10-5, Table 10-6, and Table 10-7.
Table 10-4. READ (Read Memory) Command
Read Byte from Memory
Operand
2-Byte Address in High Byte:Low Byte Order
Data
Returned
Returns Contents of Specified Address
$4A
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Command Sequence
SENT TO
MONITOR
ADDRESS
HIGH
READ
READ
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
DATA
ECHO
RETURN
Table 10-5. WRITE (Write Memory) Command
Description
Write Byte to Memory
Operand
2-Byte Address in High Byte:Low Byte Order; Low Byte Followed
by Data Byte
Data
Returned
None
Opcode
$49
Command Sequence
FROM
HOST
WRITE
A G R E E M E N T
Opcode
WRITE
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
DATA
DATA
ECHO
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N O N - D I S C L O S U R E
Description
R E Q U I R E D
Monitor ROM (MON)
Functional Description
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Table 10-6. IREAD (Indexed Read) Command
Description
2-Byte Address in High Byte:Low Byte Order
Data
Returned
Returns Contents of Next Two Addresses
Opcode
$1A
Command Sequence
FROM
HOST
IREAD
IREAD
DATA
ECHO
DATA
RETURN
Table 10-7. IWRITE (Indexed Write) Command
Description
N O N - D I S C L O S U R E
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Read Next 2 Bytes in Memory from Last Address Accessed
Operand
A G R E E M E N T
R E Q U I R E D
Monitor ROM (MON)
Write to Last Address Accessed + 1
Operand
Single Data Byte
Data
Returned
None
Opcode
$19
Command Sequence
FROM
HOST
IWRITE
IWRITE
DATA
DATA
ECHO
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A sequence of IREAD or IWRITE commands can access a block of
memory sequentially over the full 64-Kbyte memory map.
Table 10-8. READSP (Read Stack Pointer) Command
Description
Operand
None
Data
Returned
Returns Incremented Stack Pointer Value (SP + 1) in High
Byte:Low Byte Order
Command Sequence
FROM
HOST
READSP
SP
HIGH
READSP
ECHO
SP
LOW
RETURN
Table 10-9. RUN (Run User Program) Command
Description
Executes PULH and RTI Instructions
Operand
None
Data
Returned
None
Opcode
$28
Command Sequence
FROM
HOST
RUN
RUN
ECHO
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A G R E E M E N T
$0C
N O N - D I S C L O S U R E
Opcode
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Reads Stack Pointer
R E Q U I R E D
Monitor ROM (MON)
Functional Description
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The MCU executes the SWI and PSHH instructions when it enters
monitor mode. The RUN command tells the MCU to execute the PULH
and RTI instructions. Before sending the RUN command, the host can
modify the stacked CPU registers to prepare to run the host program.
The READSP command returns the incremented stack pointer value,
SP + 1. The high and low bytes of the program counter are at addresses
SP + 5 and SP + 6.
SP
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A G R E E M E N T
R E Q U I R E D
Monitor ROM (MON)
HIGH BYTE OF INDEX REGISTER
SP + 1
CONDITION CODE REGISTER
SP + 2
ACCUMULATOR
SP + 3
LOW BYTE OF INDEX REGISTER
SP + 4
HIGH BYTE OF PROGRAM COUNTER
SP + 5
LOW BYTE OF PROGRAM COUNTER
SP + 6
SP + 7
N O N - D I S C L O S U R E
Figure 10-6. Stack Pointer at Monitor Mode Entry
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NOTE:
Do not leave locations $FFF6–$FFFD blank. For security reasons,
program locations $FFF6–$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for
the host to send the eight security bytes on pin PA0.
VDD
4096 + 32 CGMXCLK CYCLES
RST
24 BUS CYCLES
PA7
COMMAND
BYTE 8
BYTE 2
BYTE 1
256 BUS CYCLES (MINIMUM)
FROM HOST
PA0
4
BREAK
2
1
COMMAND ECHO
1
BYTE 8 ECHO
NOTES:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte
BYTE 1 ECHO
FROM MCU
1
BYTE 2 ECHO
4
1
Figure 10-7. Monitor Mode Entry Timing
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the ROM data difficult for unauthorized users.
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A G R E E M E N T
A security feature1 discourages unauthorized reading of ROM locations
while in monitor mode. The host can bypass the security feature at
monitor mode entry by sending eight security bytes that match the bytes
at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain userdefined data.
N O N - D I S C L O S U R E
10.5 Security
R E Q U I R E D
Monitor ROM (MON)
Security
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If the received bytes match those at locations $FFF6–$FFFD, the host
bypasses the security feature and can read all ROM locations and
execute code from ROM. Security remains bypassed until a power-on
reset occurs. After the host bypasses security, any reset other than a
power-on reset requires the host to send another eight bytes. If the reset
was not a power-on reset, security remains bypassed regardless of the
data that the host sends.
If the received bytes do not match the data at locations $FFF6–$FFFD,
the host fails to bypass the security feature. The MCU remains in monitor
mode, but reading ROM locations returns undefined data, and trying to
execute code from ROM causes an illegal address reset. After the host
fails to bypass security, any reset other than a power-on reset causes an
endless loop of illegal address resets.
After receiving the eight security bytes from the host, the MCU transmits
a break character signalling that it is ready to receive a command.
NOTE:
The MCU does not transmit a break character until after the host sends
the eight security bytes.
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Monitor ROM (MON)
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11.1 Contents
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
11.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
11.4.1
TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . .170
11.4.2
Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
11.4.3
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
11.4.3.1
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .170
11.4.3.2
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .171
11.4.4
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . .172
11.4.4.1
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .173
11.4.4.2
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .174
11.4.4.3
PWM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
11.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
11.6
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
11.7
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .177
11.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
11.8.1
TIM Clock Pin (PTE0/TCLK) . . . . . . . . . . . . . . . . . . . . . . .178
11.8.2
TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1). . . . . . .178
11.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
11.9.1
TIM Status and Control Register . . . . . . . . . . . . . . . . . . . .179
11.9.2
TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .181
11.9.3
TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . .182
11.9.4
TIM Channel Status and Control Registers. . . . . . . . . . . .183
11.9.5
TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .187
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A G R E E M E N T
Section 11. Timer Interface Module (TIM)
N O N - D I S C L O S U R E
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R E Q U I R E D
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A G R E E M E N T
R E Q U I R E D
Timer Interface Module (TIM)
11.2 Introduction
This section describes the timer interface module (TIM2, Version B). The
TIM is a 2-channel timer that provides a timing reference with input
capture, output compare, and pulse-width-modulation functions.
Figure 11-1 is a block diagram of the TIM.
NOTE:
The TIM module is available only on the 52-pin QFP package.
11.3 Features
Features of the TIM include:
•
Two Input Capture/Output Compare Channels
– Rising-Edge, Falling-Edge, or Any-Edge Input Capture Trigger
– Set, Clear, or Toggle Output Compare Action
•
Buffered and Unbuffered Pulse Width Modulation (PWM) Signal
Generation
•
Programmable TIM Clock Input
– 7-Frequency Internal Bus Clock Prescaler Selection
– External TIM Clock Input (Bus Frequency ÷2 Maximum)
•
Free-Running or Modulo Up-Count Operation
•
Toggle Any Channel Pin on Overflow
•
TIM Counter Stop and Reset Bits
•
Modular Architecture Expandable to Eight Channels
11.4 Functional Description
Figure 11-1 shows the structure of the TIM. The central component of
the TIM is the 16-bit TIM counter that can operate as a free-running
counter or a modulo up-counter. The TIM counter provides the timing
reference for the input capture and output compare functions. The TIM
counter modulo registers, TMODH:TMODL, control the modulo value of
the TIM counter. Software can read the TIM counter value at any time
without affecting the counting sequence.
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The two TIM channels are programmable independently as input
capture or output compare channels.
TCLK
PRESCALER SELECT
TSTOP
PS2
PS1
PS0
16-BIT COUNTER
TOF
TOIE
INTERRUPT
LOGIC
16-BIT COMPARATOR
TMODH:TMODL
TOV0
CHANNEL 0
ELS0B
ELS0A
CH0MAX
PTE1
LOGIC
PTE1/TCH0
16-BIT COMPARATOR
TCH0H:TCH0L
CH0F
16-BIT LATCH
MS0A
CH0IE
INTERRUPT
LOGIC
MS0B
TOV1
INTERNAL BUS
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TRST
CHANNEL 1
ELS1B
ELS1A
CH1MAX
PTE2
LOGIC
PTE2/TCH1
16-BIT COMPARATOR
TCH1H:TCH1L
CH1F
16-BIT LATCH
MS1A
CH1IE
INTERRUPT
LOGIC
Figure 11-1. TIM Block Diagram
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A G R E E M E N T
INTERNAL
BUS CLOCK
PRESCALER
N O N - D I S C L O S U R E
PTE0/TCLK
R E Q U I R E D
Timer Interface Module (TIM)
Functional Description
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N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Timer Interface Module (TIM)
Addr.
Register Name
Bit 7
Read:
$0010
$0012
$0013
$0014
TIM Status and Control Register
Write:
(TSC)
Reset:
6
5
TOIE
TSTOP
TOF
0
4
3
0
0
2
1
Bit 0
PS2
PS1
PS0
TRST
0
0
1
0
0
0
0
0
Read:
TIM Counter Register High
Write:
(TCNTH)
Reset:
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Read:
TIM Counter Register Low
Write:
(TCNTL)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
TIM Counter Modulo Register Low
Write:
(TMODL)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
Read:
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Read:
TIM Counter Modulo Register
Write:
High (TMODH)
Reset:
Read:
$0015
$0016
$0017
$0018
TIM Channel 0 Status and Control
Write:
Register (TSC0)
Reset:
Read:
TIM Channel 0 Register High
Write:
(TCH0H)
Reset:
Read:
TIM Channel 0 Register Low
Write:
(TCH0L)
Reset:
0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
= Unimplemented
Figure 11-2. TIM I/O Register Summary
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Register Name
Bit 7
Read:
$0019
$001B
Read:
TIM Channel 1 Register High
Write:
(TCH1H)
Reset:
Read:
TIM Channel 1 Register Low
Write:
(TCH1L)
Reset:
CH1F
5
4
3
2
1
Bit 0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
CH1IE
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
= Unimplemented
Figure 11-2. TIM I/O Register Summary
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$001A
TIM Channel 1 Status and Control
Write:
Register (TSC1)
Reset:
6
A G R E E M E N T
Addr.
R E Q U I R E D
Timer Interface Module (TIM)
Functional Description
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A G R E E M E N T
R E Q U I R E D
Timer Interface Module (TIM)
11.4.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs or the
TIM clock pin, PTE0/TCLK. The prescaler generates seven clock rates
from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM
status and control register (TSC) select the TIM clock source.
11.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an
external event occurs. When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is
programmable. Input captures can generate TIM CPU interrupt
requests.
11.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse
with a programmable polarity, duration, and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIM can set, clear, or toggle the channel pin. Output compares can
generate TIM CPU interrupt requests.
11.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare
pulses as described in 11.4.3 Output Compare. The pulses are
unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIM overflow interrupt routine to write a new, smaller output
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•
When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
•
When changing to a larger output compare value, enable channel
x TIM overflow interrupts and write the new value in the TIM
overflow interrupt routine. The TIM overflow interrupt occurs at the
end of the current counter overflow period. Writing a larger value
in an output compare interrupt routine (at the end of the current
pulse) could cause two output compares to occur in the same
counter overflow period.
11.4.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the PTE1/TCH0 pin. The TIM channel
registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The output compare value in the TIM
channel 0 registers initially controls the output on the PTE1/TCH0 pin.
Writing to the TIM channel 1 registers enables the TIM channel 1
registers to synchronously control the output after the TIM overflows. At
each subsequent overflow, the TIM channel registers (0 or 1) that control
the output are the ones written to last. TSC0 controls and monitors the
buffered output compare function, and TIM channel 1 status and control
register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
PTE2/TCH1, is available as a general-purpose I/O pin.
NOTE:
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output
compares.
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Use the following methods to synchronize unbuffered changes in the
output compare value on channel x:
N O N - D I S C L O S U R E
compare value may cause the compare to be missed. The TIM may pass
the new value before it is written.
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Timer Interface Module (TIM)
11.4.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare
channel, the TIM can generate a PWM signal. The value in the TIM
counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIM
counter modulo registers. The time between overflows is the period of
the PWM signal.
As Figure 11-3 shows, the output compare value in the TIM channel
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIM to clear the channel pin on output compare if the state of the PWM
pulse is logic 1. Program the TIM to set the pin if the state of the PWM
pulse is logic 0.
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
PTEx/TCHxA
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 11-3. PWM Period and Pulse Width
The value in the TIM counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is 000 (see 11.9.1 TIM Status and Control Register).
The value in the TIM channel registers determines the pulse width of the
PWM output. The pulse width of an 8-bit PWM signal is variable in 256
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Any output compare channel can generate unbuffered PWM pulses as
described in 11.4.4 Pulse Width Modulation (PWM). The pulses are
unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIM channel
registers.
An unsynchronized write to the TIM channel registers to change a pulse
width value could cause incorrect operation for up to two PWM periods.
For example, writing a new value before the counter reaches the old
value but after the counter reaches the new value prevents any compare
during that PWM period. Also, using a TIM overflow interrupt routine to
write a new, smaller pulse width value may cause the compare to be
missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
PWM pulse width on channel x:
NOTE:
•
When changing to a shorter pulse width, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
•
When changing to a longer pulse width, enable channel x TIM
overflow interrupts and write the new value in the TIM overflow
interrupt routine. The TIM overflow interrupt occurs at the end of
the current PWM period. Writing a larger value in an output
compare interrupt routine (at the end of the current pulse) could
cause two output compares to occur in the same PWM period.
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output
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11.4.4.1 Unbuffered PWM Signal Generation
N O N - D I S C L O S U R E
increments. Writing $0080 (128) to the TIM channel registers produces
a duty cycle of 128/256 or 50%.
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A G R E E M E N T
R E Q U I R E D
Timer Interface Module (TIM)
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
11.4.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the PTE1/TCH0 pin. The TIM channel registers of the
linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The TIM channel 0 registers initially
control the pulse width on the PTE1/TCH0 pin. Writing to the TIM
channel 1 registers enables the TIM channel 1 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIM channel registers (0 or 1)
that control the pulse width are the ones written to last. TSC0 controls
and monitors the buffered PWM function, and TIM channel 1 status and
control register (TSC1) is unused. While the MS0B bit is set, the channel
1 pin, PTE2/TCH1, is available as a general-purpose I/O pin.
NOTE:
In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
11.4.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered
PWM signals, use this initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter by setting the TIM reset bit, TRST.
2. In the TIM counter modulo registers (TMODH:TMODL), write the
value for the required PWM period.
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for
the required pulse width.
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b. Write 1 to the toggle-on-overflow bit, TOVx.
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c.
NOTE:
Write 1:0 (to clear output on compare) or 1:1 (to set output on
compare) to the edge/level select bits, ELSxB:ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. (See Table 11-2.)
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit,
TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially
control the buffered PWM output. TIM status control register 0 (TSCR0)
controls and monitors the PWM signal from the linked channels. MS0B
takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM
overflows. Subsequent output compares try to force the output to a state
it is already in and have no effect. The result is a 0% duty cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing
the TOVx bit generates a 100% duty cycle output. (See 11.9.4 TIM
Channel Status and Control Registers.)
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a. Write 0:1 (for unbuffered output compare or PWM signals) or
1:0 (for buffered output compare or PWM signals) to the mode
select bits, MSxB:MSxA. (See Table 11-2.)
N O N - D I S C L O S U R E
4. In TIM channel x status and control register (TSCx):
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Timer Interface Module (TIM)
11.5 Interrupts
The following TIM sources can generate interrupt requests:
•
TIM overflow flag (TOF) — The TOF bit is set when the TIM
counter value rolls over to $0000 after matching the value in the
TIM counter modulo registers. The TIM overflow interrupt enable
bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and
TOIE are in the TIM status and control register.
•
TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests
are enabled when CHxIE = 1. CHxF and CHxIE are in the TIM
channel x status and control register.
11.6 Wait Mode
The WAIT instruction puts the MCU in low-power standby mode.
The TIM remains active after the execution of a WAIT instruction. In wait
mode the TIM registers are not accessible by the CPU. Any enabled
CPU interrupt request from the TIM can bring the MCU out of wait mode.
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
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A break interrupt stops the TIM counter.
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
11.8 I/O Signals
Port E shares three of its pins with the TIM. PTE0/TCLK is an external
clock input to the TIM prescaler. The two TIM channel I/O pins are
PTE1/TCH0 and PTE2/TCH1.
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The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the break flag control register (BFCR) enables software to clear status
bits during the break state. (See 8.8.3 Break Flag Control Register.)
A G R E E M E N T
11.7 TIM During Break Interrupts
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TIM During Break Interrupts
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Timer Interface Module (TIM)
11.8.1 TIM Clock Pin (PTE0/TCLK)
PTE0/TCLK is an external clock input that can be the clock source for
the TIM counter instead of the prescaled internal bus clock. Select the
PTE0/TCLK input by writing logic 1s to the three prescaler select bits,
PS[2:0]. (See 11.9.1 TIM Status and Control Register.) The minimum
TCLK pulse width, TCLKLMIN or TCLKHMIN, is:
1
------------------------------------- + tSU
bus frequency
The maximum TCLK frequency is:
bus frequency ÷ 2
PTE0/TCLK is available as a general-purpose I/O pin when not used as
the TIM clock input. When the PTE0/TCLK pin is the TIM clock input, it
is an input regardless of the state of the DDRE0 bit in data direction
register E.
11.8.2 TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1)
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTE1/TCH0 can be configured as
buffered output compare or buffered PWM pins.
11.9 I/O Registers
These I/O registers control and monitor TIM operation:
•
TIM status and control register (TSC)
•
TIM control registers (TCNTH:TCNTL)
•
TIM counter modulo registers (TMODH:TMODL)
•
TIM channel status and control registers (TSC0 and TSC1)
•
TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
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11.9.1 TIM Status and Control Register
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The TIM status and control register:
•
Enables TIM overflow interrupts
•
Flags TIM overflows
•
Stops the TIM counter
•
Resets the TIM counter
•
Prescales the TIM counter clock
Address:
$0010
Bit 7
Read:
6
5
TOIE
TSTOP
TOF
Write:
0
Reset:
0
4
3
0
0
2
1
Bit 0
PS2
PS1
PS0
0
0
0
TRST
0
1
0
0
= Unimplemented
Figure 11-4. TIM Status and Control Register (TSC)
A G R E E M E N T
R E Q U I R E D
Timer Interface Module (TIM)
I/O Registers
This read/write flag is set when the TIM counter resets to $0000 after
reaching the modulo value programmed in the TIM counter modulo
registers. Clear TOF by reading the TIM status and control register
when TOF is set and then writing a logic 0 to TOF. If another TIM
overflow occurs before the clearing sequence is complete, then
writing logic 0 to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset
clears the TOF bit. Writing a logic 1 to TOF has no effect.
1 = TIM counter has reached modulo value.
0 = TIM counter has not reached modulo value.
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
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TOF — TIM Overflow Flag Bit
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Timer Interface Module (TIM)
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM
counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE:
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIM counter is reset and always reads as logic 0. Reset clears the
TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE:
Setting the TSTOP and TRST bits simultaneously stops the TIM counter
at a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTE0/TCLK pin or one of the
seven prescaler outputs as the input to the TIM counter as
Table 11-1 shows. Reset clears the PS[2:0] bits.
Table 11-1. Prescaler Selection
PS[2:0]
TIM Clock Source
000
Internal Bus Clock ÷1
001
Internal Bus Clock ÷ 2
010
Internal Bus Clock ÷ 4
011
Internal Bus Clock ÷ 8
100
Internal Bus Clock ÷ 16
101
Internal Bus Clock ÷ 32
110
Internal Bus Clock ÷ 64
111
PTE0/TCLK
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NOTE:
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
TCNTH
Read:
Address: $0012
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
Write:
Reset:
TCNTL
Address: $0013
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 11-5. TIM Counter Registers (TCNTH:TCNTL)
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The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
N O N - D I S C L O S U R E
11.9.2 TIM Counter Registers
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11.9.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the
TIM counter. When the TIM counter reaches the modulo value, the
overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next clock. Writing to the high byte (TMODH) inhibits
the TOF bit and overflow interrupts until the low byte (TMODL) is written.
Reset sets the TIM counter modulo registers.
TMODH
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Timer Interface Module (TIM)
Address: $0014
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
TMODL
Address: $0015
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
Figure 11-6. TIM Counter Modulo Registers (TMODH:TMODL)
NOTE:
Reset the TIM counter before writing to the TIM counter modulo registers.
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Each of the TIM channel status and control registers:
•
Flags input captures and output compares
•
Enables input capture and output compare interrupts
•
Selects input capture, output compare, or PWM operation
•
Selects high, low, or toggling output on output compare
•
Selects rising edge, falling edge, or any edge as the active input
capture trigger
•
Selects output toggling on TIM overflow
•
Selects 100% PWM duty cycle
•
Selects buffered or unbuffered output compare/PWM operation
TSC0
Address: $0016
Bit 7
Read:
CH0F
Write:
0
Reset:
0
TSC1
6
5
4
3
2
1
Bit 0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
5
4
3
2
1
Bit 0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
Address: $0019
Bit 7
Read:
6
CH1F
0
CH1IE
Write:
0
Reset:
0
0
0
= Unimplemented
Figure 11-7. TIM Channel Status and Control Registers
(TSC0:TSC1)
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11.9.4 TIM Channel Status and Control Registers
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I/O Registers
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Timer Interface Module (TIM)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE = 1), clear
CHxF by reading the TIM channel x status and control register with
CHxF set and then writing a logic 0 to CHxF. If another interrupt
request occurs before the clearing sequence is complete, then writing
logic 0 to CHxF has no effect. Therefore, an interrupt request cannot
be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on
channel x. Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIM channel 0 status and control register.
Setting MS0B disables the channel 1 status and control register and
reverts TCH1 to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation.
See Table 11-2.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
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When ELSxB:A = 00, this read/write bit selects the initial output level
of the TCHx pin. (See Table 11-2.). Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE:
Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
R E Q U I R E D
Timer Interface Module (TIM)
I/O Registers
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to port E, and pin PTEx/TCHx is available as a general-purpose I/O
pin. Table 11-2 shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
Table 11-2. Mode, Edge, and Level Selection
MSxB:MSxA
ELSxB:ELSxA
X0
00
X1
00
00
01
00
10
00
11
01
01
01
10
01
11
1X
01
1X
10
1X
11
Mode
Output
Preset
Configuration
Pin under Port Control; Initial
Output Level High
Pin under Port Control; Initial
Output Level Low
Capture on Rising Edge Only
Input
Capture
Capture on Falling Edge Only
Capture on Rising or Falling Edge
Output
Compare
or PWM
Buffered
Output
Compare or
Buffered
PWM
Toggle Output on Compare
Clear Output on Compare
Set Output on Compare
Toggle Output on Compare
Clear Output on Compare
Set Output on Compare
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When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
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ELSxB and ELSxA — Edge/Level Select Bits
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Timer Interface Module (TIM)
NOTE:
Before enabling a TIM channel register for input capture operation, make
sure that the PTEx/TCHx pin is stable for at least two bus clocks.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIM counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE:
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 0, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 11-8 shows, the CHxMAX bit takes effect in the cycle after it
is set or cleared. The output stays at the 100% duty cycle level until
the cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PTEx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
CHxMAX
Figure 11-8. CHxMAX Latency
General Release Specification
MC68HC08KL8 — Rev. 2.0
Timer Interface Module (TIM)
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In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
TCH0H
Read:
Write:
Address:
$0017
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset:
TCH0L
Read:
Write:
Indeterminate after Reset
Address:
$0018
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset:
TCH1H
Read:
Write:
Indeterminate after Reset
Address:
$001A
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset:
TCH1L
Read:
Write:
Reset:
Indeterminate after Reset
Address:
$001B
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indeterminate after Reset
Figure 11-9. TIM Channel Registers (TCH0H/L:TCH1H/L)
MC68HC08KL8 — Rev. 2.0
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Timer Interface Module (TIM)
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A G R E E M E N T
These read/write registers contain the captured TIM counter value of the
input capture function or the output compare value of the output
compare function. The state of the TIM channel registers after reset is
unknown.
N O N - D I S C L O S U R E
11.9.5 TIM Channel Registers
R E Q U I R E D
Timer Interface Module (TIM)
I/O Registers
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N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Timer Interface Module (TIM)
General Release Specification
MC68HC08KL8 — Rev. 2.0
Timer Interface Module (TIM)
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General Release Specification — MC68HC08KL8
Section 12. Input/Output Ports (I/O)
12.1 Contents
12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
12.3.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
12.3.2
Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . .193
12.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
12.4.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
12.4.2
Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . .196
12.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
12.5.1
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
12.5.2
Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . .199
12.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
12.6.1
Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
12.6.2
Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . .202
12.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
12.7.1
Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
12.7.2
Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . .206
12.8 Port Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
12.8.1
Port Option Control Register . . . . . . . . . . . . . . . . . . . . . . .208
MC68HC08KL8 — Rev. 2.0
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Input/Output Ports (I/O)
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A G R E E M E N T
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
N O N - D I S C L O S U R E
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12.2
R E Q U I R E D
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N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Input/Output Ports (I/O)
12.2 Introduction
Thirty-nine bidirectional input-output (I/O) pins form five parallel ports. All
I/O pins are programmable as inputs or outputs.
NOTE:
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Register Name
Read:
Port A Data Register
Write:
(PTA)
Reset:
Read:
Port B Data Register
Write:
(PTB)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTB2
PTB1
PTB0
PTC2
PTC1
PTC0
PTD2
PTD1
PTD0
Unaffected by Reset
PTB7
PTD7
Read:
DDRA7
Data Direction Register A
Write:
(DDRA)
Reset:
0
Read:
DDRB7
Data Direction Register B
Write:
(DDRB)
Reset:
0
Note 1. Only available on 52-pin QFP.
PTB5
PTB4
PTB3
Unaffected by Reset
Read:
PTC7(1)
Port C Data Register
Write:
(PTC)
Reset:
Read:
Port D Data Register
Write:
(PTD)
Reset:
PTB6
PTC6(1)
PTC5(1)
PTC4
PTC3
Unaffected by Reset
PTD6
PTD5
PTD4
PTD3
Unaffected by Reset
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-1. I/O Port Register Summary
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MC68HC08KL8 — Rev. 2.0
Input/Output Ports (I/O)
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Bit 7
6
5
4
3
2
1
Bit 0
$0006
Read:
DDRC7(1) DDRC6(1) DDRC5(1) DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Data Direction Register C
Write:
(DDRC)
Reset:
0
0
0
0
0
0
0
0
$0007
Read:
DDRD7
Data Direction Register D
Write:
(DDRD)
Reset:
0
$0008
$000C
$000F
Read:
Port E Data Register(1)
Write:
(PTE)
Reset:
0
Read:
Data Direction Register E(1)
Write:
(DDRE)
Reset:
0
Read:
Port Option Control Register
Write:
(POC)
Reset:
Note 1. Only available on 52-pin QFP.
DDRD6
DDRD5
DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
0
0
0
0
0
0
0
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
Unaffected by Reset
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
0
0
0
0
0
0
0
0
0
0
0
0
PCP
PBP
PAP
0
0
0
0
0
0
0
LDD
1
A G R E E M E N T
Register Name
= Unimplemented
Figure 12-1. I/O Port Register Summary (Continued)
MC68HC08KL8 — Rev. 2.0
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Input/Output Ports (I/O)
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N O N - D I S C L O S U R E
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Addr.
R E Q U I R E D
Input/Output Ports (I/O)
Introduction
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12.3 Port A
Port A is an 8-bit general-purpose bidirectional I/O port with software
configurable pullups.
12.3.1 Port A Data Register
The port A data register contains a data latch for each of the eight port
A pins.
Address:
$0000
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Read:
Write:
Reset:
Unaffected by Reset
Figure 12-2. Port A Data Register (PTA)
PTA[7:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Input/Output Ports (I/O)
The port A pullup enable bit, PAP, in the port option control register
(POC) enables pullups on port A pins if the respective pin is
configured as an input. (See 12.8 Port Options.)
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Input/Output Ports (I/O)
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12.3.2 Data Direction Register A
Data direction register A determines whether each port A pin is an input
or an output. Writing a logic 1 to a DDRA bit enables the output buffer for
the corresponding port A pin; a logic 0 disables the output buffer.
Address:
$0004
Bit 7
6
5
4
3
2
1
Bit 0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
Read:
R E Q U I R E D
Input/Output Ports (I/O)
Port A
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 12-4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
DDRAx
WRITE PTA ($0000)
PTAx
PTAx
READ PTA ($0000)
Figure 12-4. Port A I/O Circuit
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A G R E E M E N T
Figure 12-3. Data Direction Register A (DDRA)
N O N - D I S C L O S U R E
Reset:
INTERNAL DATA BUS
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Write:
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When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-1 summarizes
the operation of the port A pins.
Table 12-1. Port A Pin Functions
DDRA
Bit
PTA Bit
I/O Pin
Mode
Accesses
to DDRA
Accesses to PTA
Read/Write
Read
Write
0
X(1)
Input, Hi-Z(2)
DDRA[7:0]
Pin
PTA[7:0](3)
1
X
Output
DDRA[7:0]
PTA[7:0]
PTA[7:0]
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.
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A G R E E M E N T
R E Q U I R E D
Input/Output Ports (I/O)
General Release Specification
MC68HC08KL8 — Rev. 2.0
Input/Output Ports (I/O)
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12.4.1 Port B Data Register
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The port B data register contains a data latch for each of the eight port
B pins.
Address:
$0001
Bit 7
6
5
4
3
2
1
Bit 0
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Read:
Write:
Reset:
Unaffected by Reset
Figure 12-5. Port B Data Register (PTB)
PTB[7:0] — Port B Data Bits
These read/write bits are software-programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
The port B pullup enable bit, PBP, in the port option control register
(POC) enables pullups on port B pins if the respective pin is
configured as an input. (See 12.8 Port Options.)
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A G R E E M E N T
Port B is an 8-bit, general-purpose, bidirectional I/O port with software
configurable pullups.
N O N - D I S C L O S U R E
12.4 Port B
R E Q U I R E D
Input/Output Ports (I/O)
Port B
Freescale Semiconductor, Inc.
R E Q U I R E D
Input/Output Ports (I/O)
12.4.2 Data Direction Register B
Data direction register B determines whether each port B pin is an input
or an output. Writing a logic 1 to a DDRB bit enables the output buffer for
the corresponding port B pin; a logic 0 disables the output buffer.
Address:
$0005
Bit 7
6
5
4
3
2
1
Bit 0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
Write:
Reset:
Figure 12-6. Data Direction Register B (DDRB)
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[7:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE:
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 12-7 shows the port B I/O logic.
READ DDRB ($0005)
WRITE DDRB ($0005)
INTERNAL DATA BUS
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A G R E E M E N T
Read:
RESET
DDRBx
WRITE PTB ($0001)
PTBx
PTBx
READ PTB ($0001)
Figure 12-7. Port B I/O Circuit
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Table 12-2. Port B Pin Functions
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DDRB
Bit
PTB Bit
I/O Pin Mode
Accesses
to DDRB
Accesses to PTB
Read/Write
Read
Write
0
X(1)
Input, Hi-Z(2)
DDRB[7:0]
Pin
PTB[7:0](3)
1
X
Output
DDRB[7:0]
PTB[7:0]
PTB[7:0]
N O N - D I S C L O S U R E
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.
A G R E E M E N T
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx
data latch. When bit DDRBx is a logic 0, reading address $0001 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-2 summarizes
the operation of the port B pins.
R E Q U I R E D
Input/Output Ports (I/O)
Port B
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R E Q U I R E D
Input/Output Ports (I/O)
12.5 Port C
Port C is an 8-bit, general-purpose, bidirectional I/O port with software
configurable pullups and current drive options.
NOTE:
On the 42-lead SDIP package the PTC7–PTC5 pads are not bonded
out. Set these ports to output to avoid floating inputs.
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A G R E E M E N T
12.5.1 Port C Data Register
The port C data register contains a data latch for each of the eight port
C pins.
Address:
$0002
Bit 7
6
5
4
3
2
1
Bit 0
PTC7
PTC6
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
Read:
Write:
Reset:
Unaffected by Reset
Figure 12-8. Port C Data Register (PTC)
PTC[7:0] — Port C Data Bits
These read/write bits are software-programmable. Data direction of
each port C pin is under the control of the corresponding bit in data
direction register C. Reset has no effect on port C data.
The LED direct drive bit, LDD, in the port option control register (POC)
controls the drive options for port C.
The port C pullup enable bit, PCP, in the port option control register
(POC) enables pullups on PTC[7:0] if the respective pin is configured
as an input. (See 12.8 Port Options.)
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12.5.2 Data Direction Register C
Data direction register C determines whether each port C pin is an input
or an output. Writing a logic 1 to a DDRC bit enables the output buffer
for the corresponding port C pin; a logic 0 disables the output buffer.
Address:
$0006
Bit 7
6
5
4
3
2
1
Bit 0
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
0
R E Q U I R E D
Input/Output Ports (I/O)
Port C
Figure 12-9. Data Direction Register C (DDRC)
DDRC[7:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears
DDRC[7:0], configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE:
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Figure 12-10 shows the port C I/O logic.
READ DDRC ($0006)
WRITE DDRC ($0006)
RESET
DDRCx
WRITE PTC ($0002)
PTCx
PTCx
READ PTC ($0002)
Figure 12-10. Port C I/O Circuit
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A G R E E M E N T
Reset:
N O N - D I S C L O S U R E
Write:
INTERNAL DATA BUS
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Read:
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When bit DDRCx is a logic 1, reading address $0002 reads the PTCx
data latch. When bit DDRCx is a logic 0, reading address $0002 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-3 summarizes
the operation of the port C pins.
Table 12-3. Port C Pin Functions
DDRC
Bit
PTC Bit
I/O Pin Mode
Accesses
to DDRC
Accesses to PTC
Read/Write
Read
Write
0
X(1)
Input, Hi-Z(2)
DDRC[7:0]
Pin
PTC[7:0](3)
1
X
Output
DDRC[7:0]
PTC[7:0]
PTC[7:0]
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.
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A G R E E M E N T
R E Q U I R E D
Input/Output Ports (I/O)
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12.6.1 Port D Data Register
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The port D data register contains a data latch for each of the eight port
D pins.
Address:
$0003
Bit 7
6
5
4
3
2
1
Bit 0
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
Read:
Write:
Reset:
Unaffected by Reset
Figure 12-11. Port D Data Register (PTD)
PTD[7:0] — Port D Data Bits
These read/write bits are software programmable. Data direction of
each port D pin is under control of the corresponding bit in data
direction register D. Reset has no effect on port D data.
The keyboard interrupt enable bits, KBIE7–KBIE0, in the keyboard
interrupt control register (KBICR) enable the port D pins as external
interrupt pins. (See Section 15. Keyboard Interrupt Module (KBI).)
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A G R E E M E N T
Port D is an 8-bit, general-purpose, bidirectional I/O port that shares its
pins with the keyboard interrupt module (KBI).
N O N - D I S C L O S U R E
12.6 Port D
R E Q U I R E D
Input/Output Ports (I/O)
Port D
Freescale Semiconductor, Inc.
R E Q U I R E D
Input/Output Ports (I/O)
12.6.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic 0 disables the output buffer.
Address:
$0007
Bit 7
6
5
4
3
2
1
Bit 0
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
0
0
0
0
0
0
0
0
Write:
Reset:
Figure 12-12. Data Direction Register D (DDRD)
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 12-13 shows the port D I/O circuit logic.
READ DDRD ($0007)
WRITE DDRD ($0007)
INTERNAL DATA BUS
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A G R E E M E N T
Read:
RESET
DDRDx
WRITE PTD ($0003)
PTDx
PTDx
READ PTD ($0003)
Figure 12-13. Port D I/O Circuit
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Table 12-4. Port D Pin Functions
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DDRD
Bit
PTD Bit
I/O Pin Mode
Accesses
to DDRD
Accesses to PTD
Read/Write
Read
Write
0
X(1)
Input, Hi-Z(2)
DDRD[7:0]
Pin
PTD[7:0](3)
1
X
Output
DDRD[7:0]
PTD[7:0]
PTD[7:0]
N O N - D I S C L O S U R E
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.
A G R E E M E N T
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx
data latch. When bit DDRDx is a logic 0, reading address $0003 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-4 summarizes
the operation of the port D pins.
R E Q U I R E D
Input/Output Ports (I/O)
Port D
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R E Q U I R E D
Input/Output Ports (I/O)
12.7 Port E
Port E is a 7-bit special function port that shares three of its pins with the
timer interface module (TIM).
NOTE:
On the 42-lead SDIP package the port E pads are not bonded out. Set
these ports to output to avoid floating inputs.
N O N - D I S C L O S U R E
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A G R E E M E N T
12.7.1 Port E Data Register
The port E data register contains a data latch for each of the seven port
E pins.
Address:
$0008
Bit 7
Read:
6
5
4
3
2
1
Bit 0
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
TCH1
TCH0
TCLK
0
Write:
Reset:
Unaffected by Reset
= Unimplemented
Alternate
Function:
Figure 12-14. Port E Data Register (PTE)
PTE[6:0] — Port E Data Bits
PTE[6:0] are read/write, software-programmable bits. Data direction
of each port E pin is under the control of the corresponding bit in data
direction register E.
TCH1–TCH0 — Timer Channel I/O Bits
The PE2/TCH1–PE1/TCH0 pins are the TIM input capture/output
compare pins. The edge/level select bits, ELSxB and ELSxA,
determine whether the PE2/TCH1–PE1/TCH0 pins are timer channel
I/O pins or general-purpose I/O pins. (See Section 11. Timer
Interface Module (TIM).)
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Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the TIM. However, the DDRE bits
always determine whether reading port E returns the states of the
latches or the states of the pins.
TCLK — Timer Clock Input
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The PE0/TCLK pin is the external clock input for the TIM. The prescaler
select bits, PS2–PS0, selects PE0/TCLK as the TIM clock input. When
not selected as the TIM clock, PE0/TCLK is available for generalpurpose I/O. (See Section 11. Timer Interface Module (TIM).)
A G R E E M E N T
NOTE:
R E Q U I R E D
Input/Output Ports (I/O)
Port E
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R E Q U I R E D
Input/Output Ports (I/O)
12.7.2 Data Direction Register E
Data direction register E determines whether each port E pin is an input
or an output. Writing a logic 1 to a DDRE bit enables the output buffer for
the corresponding port E pin; a logic 0 disables the output buffer.
Address:
Bit 7
6
5
4
3
2
1
Bit 0
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
0
0
0
0
0
0
0
0
Write:
Reset:
0
= Unimplemented
Figure 12-15. Data Direction Register E (DDRE)
DDRE[6:0] — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears
DDRE[6:0], configuring all port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE:
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 12-16 shows the port E I/O circuit logic.
READ DDRE ($000C)
WRITE DDRE ($000C)
INTERNAL DATA BUS
Freescale Semiconductor, Inc...
A G R E E M E N T
Read:
N O N - D I S C L O S U R E
$000C
RESET
DDREx
WRITE PTE ($0008)
PTEx
PTEx
READ PTE ($0008)
Figure 12-16. Port E I/O Circuit
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Table 12-5. Port E Pin Functions
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DDRE
Bit
PTE
Bit
I/O Pin Mode
Accesses
to DDRE
Accesses to PTE
Read/Write
Read
Write
0
X(1)
Input, Hi-Z(2)
DDRE[6:0]
Pin
PTE[6:0](3)
1
X
Output
DDRE[6:0]
PTE[6:0]
PTE[6:0]
N O N - D I S C L O S U R E
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.
A G R E E M E N T
When bit DDREx is a logic 1, reading address $0008 reads the PTEx
data latch. When bit DDREx is a logic 0, reading address $0008 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-5 summarizes
the operation of the port E pins.
R E Q U I R E D
Input/Output Ports (I/O)
Port E
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A G R E E M E N T
R E Q U I R E D
Input/Output Ports (I/O)
12.8 Port Options
All pins of port A, port B, and port C have programmable pullup resistors.
Port C also has LED drive capability.
12.8.1 Port Option Control Register
The pullup option for each port is controlled by one bit in the port
option control register. One bit controls the LED drive configuration on
port C.
Address:
Read:
$000F
Bit 7
6
0
0
5
4
3
0
0
LDD
2
1
Bit 0
PCP
PBP
PAP
0
0
0
Write:
Reset:
0
0
1
0
0
= Unimplemented
Figure 12-17. Port Option Control Register (POC)
LDD — LED Direct Drive Control
This read/write bit controls the output current capability of port C.
When set, the port C pins have current limiting ability so that an LED
can be connected directly between the port pin and VDD or VSS
without the need of a series resistor.
1 = When respective port is configured as an output, make port C
become current, limiting 3 mA source/10 mA sink port pins.
0 = Configure port C to become standard I/O port pins.
PCP — Port C Pullup Enable
This read/write bit controls the pullup option for port C[7:0] if its
respective port pin is configured as an input.
1 = Configure port C to have internal pullups.
0 = Disconnect port C internal pullups.
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This read/write bit controls the pullup option for the eight bits of port B
if its respective port pin is configured as an input.
1 = Configure port B to have internal pullups.
0 = Disconnect port B internal pullups.
PAP — Port A Pullup Enable
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This read/write bit controls the pullup option for the eight bits of port A
if its respective port pin is configured as an input.
1 = Configure port A to have internal pullups.
0 = Disconnect port A internal pullups.
A G R E E M E N T
PBP — Port B Pullup Enable
R E Q U I R E D
Input/Output Ports (I/O)
Port Options
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A G R E E M E N T
R E Q U I R E D
Input/Output Ports (I/O)
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13.1 Contents
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
13.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
13.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
13.4.1
CGMXCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
13.4.2
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
13.4.3
COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
13.4.4
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
13.4.5
Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
13.4.6
Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
13.4.7
COPD (COP Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
13.4.8
COPRS (COP Rate Select). . . . . . . . . . . . . . . . . . . . . . . .214
13.5
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
13.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
13.7
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
13.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
13.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
13.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
13.9
COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .216
13.2 Introduction
This COP module contains a free-running counter that generates a reset
if allowed to overflow. The COP module helps software recover from
runaway code. Prevent a COP reset by clearing the COP counter
periodically. A mask option is available to disable the COP module.
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A G R E E M E N T
Section 13. Computer Operating Properly (COP)
N O N - D I S C L O S U R E
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13.3 Functional Description
Figure 13-1 shows the structure of the COP module.
SIM
RESET STATUS REGISTER
COP TIMEOUT
STOP INSTRUCTION
INTERNAL RESET SOURCES(1)
RESET VECTOR FETCH
CLEAR STAGES 5–12
CLEAR ALL STAGES
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N O N - D I S C L O S U R E
SIM RESET CIRCUIT
12-BIT COP PRESCALER
CGMXCLK
A G R E E M E N T
R E Q U I R E D
Computer Operating Properly (COP)
COPCTL WRITE
COP CLOCK
COP MODULE
6-BIT COP COUNTER
COPEN (FROM SIM)
COP DISABLE
(MASK OPTION)
RESET
CLEAR
COP COUNTER
COPCTL WRITE
COP TIMEOUT PERIOD
(MASK OPTION)
NOTE:
1. See Section 8. System Integration Module (SIM) for more details.
Figure 13-1. COP Block Diagram
Addr.
$FFFF
Register Name
Bit 7
COP Control Register
(COPCTL)
6
5
4
3
2
Read:
Low Byte of Reset Vector
Write:
Writing Clears COP Counter (Any Value)
Reset:
Unaffected by Reset
1
Bit 0
Figure 13-2. COP I/O Register Summary
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Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the reset status register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ1 is held
at VTST. During the break state, VTST on the RST pin disables the COP.
NOTE:
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
13.4 I/O Signals
The following paragraphs describe the signals shown in Figure 13-1.
13.4.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency
is equal to the crystal frequency.
13.4.2 STOP Instruction
The STOP instruction clears the COP prescaler.
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NOTE:
N O N - D I S C L O S U R E
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler counter. If not cleared by software, the COP counter overflows
and generates an asynchronous reset after 218 – 24 or 213 – 24
CGMXCLK cycles, depending on the mask option selected for COP
timeout period. With a 218 – 24 CGMXCLK cycle overflow option, a
4.9152-MHz crystal gives a COP timeout period of 53.3 ms. Writing any
value to location $FFFF before an overflow occurs prevents a COP reset
by clearing the COP counter and stages 12 through 5 of the SIM counter.
R E Q U I R E D
Computer Operating Properly (COP)
I/O Signals
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A G R E E M E N T
R E Q U I R E D
Computer Operating Properly (COP)
13.4.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 13.5 COP
Control Register) clears the COP counter and clears bits 12 through 4
of the SIM counter. Reading the COP control register returns the low
byte of the reset vector.
13.4.4 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the COP prescaler
4096 CGMXCLK cycles after power-up.
13.4.5 Internal Reset
An internal reset clears the SIM counter and the COP counter.
13.4.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the COP prescaler.
13.4.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit mask option.
13.4.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select mask option.
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$FFFF
Bit 7
6
5
4
3
2
Read:
Low Byte of Reset Vector
Write:
Writing Clears COP Counter (Any Value)
Reset:
Unaffected by Reset
1
Bit 0
Figure 13-3. COP Control Register (COPCTL)
13.6 Interrupts
The COP does not generate CPU interrupt requests.
13.7 Monitor Mode
The COP is disabled in monitor mode when VTST is present on the IRQ1
pin or on the RST pin.
13.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby
modes.
13.8.1 Wait Mode
The COP remains active during wait mode. To prevent a COP reset
during wait mode, periodically clear the COP counter in a CPU interrupt
routine.
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A G R E E M E N T
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
N O N - D I S C L O S U R E
13.5 COP Control Register
R E Q U I R E D
Computer Operating Properly (COP)
COP Control Register
Freescale Semiconductor, Inc.
13.8.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP
prescaler. Service the COP immediately before entering or after exiting
stop mode to ensure a full COP timeout period after entering or exiting
stop mode.
To prevent inadvertently turning off the COP with a STOP instruction, a
mask option is available that disables the STOP instruction. When the
STOP instruction is disabled, execution of a STOP instruction results in
an illegal opcode reset.
13.9 COP Module During Break Mode
The COP is disabled during a break interrupt when VTST is present on
the RST pin.
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Computer Operating Properly (COP)
General Release Specification
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Section 14. External Interrupt (IRQ)
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
14.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
14.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
14.5
IRQ1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
14.6
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .222
14.7
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .222
14.2 Introduction
The IRQ module provides an external interrupt input.
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14.1 Contents
A G R E E M E N T
General Release Specification — MC68HC08KL8
R E Q U I R E D
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A G R E E M E N T
R E Q U I R E D
External Interrupt (IRQ)
14.3 Features
Features of the IRQ module include:
•
A Dedicated External Interrupt Pin, IRQ1
•
IRQ1 Interrupt Control Bits
•
Hysteresis Buffer
•
Programmable Edge-Only or Edge and Level Interrupt Sensitivity
•
Automatic Interrupt Acknowledge
•
IRQ1 Pin Includes Internal Pullup Resistor
14.4 Functional Description
A logic 0 applied to the external interrupt pin can latch a CPU interrupt
request. Figure 14-1 shows the structure of the IRQ module.
Interrupt signals on the IRQ1 pin are latched into the IRQ1 latch. An
interrupt latch remains set until one of the following actions occurs:
•
Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the IRQ latch.
•
Software clear — Software can clear the interrupt latch by writing
to the acknowledge bit in the interrupt status and control register
(ISCR). Writing a logic 1 to the ACK1 bit clears the IRQ1 latch.
•
Reset — A reset automatically clears the interrupt latch.
The external interrupt pin is falling-edge-triggered and is softwareconfigurable to be either falling-edge or low-level-triggered. The MODE1
bit in the ISCR controls the triggering sensitivity of the IRQ1 pin.
When the interrupt pin is edge-triggered only, the CPU interrupt request
remains set until a vector fetch, software clear, or reset occurs.
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•
Vector fetch or software clear
•
Return of the interrupt pin to logic 1
When set, the IMASK1 bit in the ISCR mask all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the IMASK1 bit is clear.
NOTE:
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests. (See 8.6
Exception Control.)
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The vector fetch or software clear may occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE1 control bit,
thereby clearing the interrupt even if the pin stays low.
A G R E E M E N T
When the interrupt pin is both falling-edge and low-level-triggered, the
CPU interrupt request remains set until both of the following occur:
R E Q U I R E D
External Interrupt (IRQ)
Functional Description
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ACK1
RESET
INTERNAL ADDRESS BUS
R E Q U I R E D
External Interrupt (IRQ)
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
VDD
INTERNAL
PULLUP
DEVICE
VDD
IRQF1
D
SYNCHRONIZER
IRQ1
INTERRUPT
REQUEST
HIGH
VOLTAGE
DETECT
TO MODE
SELECT
LOGIC
IRQ1
FF
A G R E E M E N T
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Q
CK
IRQ1
N O N - D I S C L O S U R E
CLR
IMASK1
MODE1
Figure 14-1. IRQ Module Block Diagram
Addr.
$001E
Register Name
Read:
IRQ Status/Control Register
Write:
(ISCR)
Reset:
Bit 7
6
5
4
3
2
0
0
0
0
IRQF1
0
1
Bit 0
IMASK1 MODE1
ACK1
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-2. IRQ I/O Register Summary
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If the MODE1 bit is set, the IRQ1 pin is both falling-edge-sensitive and
low-level-sensitive. With MODE1 set, both of the following actions must
occur to clear IRQ1:
•
Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK1 bit in the interrupt status and control register (ISCR).
The ACK1 bit is useful in applications that poll the IRQ1 pin and
require software to clear the IRQ1 latch. Writing to the ACK1 bit
prior to leaving an interrupt service routine can also prevent
spurious interrupts due to noise. Setting ACK1 does not affect
subsequent transitions on the IRQ1 pin. A falling edge that occurs
after writing to the ACK1 bit latches another interrupt request. If
the IRQ1 mask bit, IMASK1, is clear, the CPU loads the program
counter with the vector address at locations $FFFA and $FFFB.
•
Return of the IRQ1 pin to logic 1 — As long as the IRQ1 pin is at
logic 0, IRQ1 remains active.
The vector fetch or software clear and the return of the IRQ1 pin to logic
1 may occur in any order. The interrupt request remains pending as long
as the IRQ1 pin is at logic 0. A reset will clear the latch and the MODE1
control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE1 bit is clear, the IRQ1 pin is falling-edge-sensitive only.
With MODE1 clear, a vector fetch or software clear immediately clears
the IRQ1 latch.
The IRQF1 bit in the ISCR register can be used to check for pending
interrupts. The IRQF1 bit is not affected by the IMASK1 bit, which makes
it useful in applications where polling is preferred.
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A G R E E M E N T
A logic 0 on the IRQ1 pin can latch an interrupt request into the IRQ1
latch. A vector fetch, software clear, or reset clears the IRQ1 latch.
N O N - D I S C L O S U R E
14.5 IRQ1 Pin
R E Q U I R E D
External Interrupt (IRQ)
IRQ1 Pin
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N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
External Interrupt (IRQ)
Use the BIH or BIL instruction to read the logic level on the IRQ1 pin.
NOTE:
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
14.6 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ1 latch
can be cleared during the break state. The BCFE bit in the break flag
control register (BFCR) enables software to clear the latches during the
break state. (See Section 8. System Integration Module (SIM).)
To allow software to clear the IRQ1 latch during a break interrupt, write
a logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the latches during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the ACK1 bit in the
IRQ status and control register during the break state has no effect on
the IRQ latch.
14.7 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module. The ISCR has the following functions:
•
Shows the state of the IRQ1 flag
•
Clears the IRQ1 latch
•
Masks IRQ1 and interrupt request
•
Controls triggering sensitivity of the IRQ1 interrupt pin
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External Interrupt (IRQ)
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Bit 7
6
5
4
3
2
0
0
0
0
IRQF1
0
Write:
Reset:
1
Bit 0
IMASK1
MODE1
0
0
ACK1
0
0
0
0
0
0
= Unimplemented
Freescale Semiconductor, Inc...
Figure 14-3. IRQ Status and Control Register (ISCR)
IRQF1 — IRQ1 Flag
This read-only status bit is high when the IRQ1 interrupt is
pending.
1 = IRQ1 interrupt pending
0 = IRQ1 interrupt not pending
ACK1 — IRQ1 Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ1 latch.
ACK1 always reads as logic 0. Reset clears ACK1.
IMASK1 — IRQ1 Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ1 interrupt
requests. Reset clears IMASK1.
1 = IRQ1 interrupt requests disabled
0 = IRQ1 interrupt requests enabled
MODE1 — IRQ1 Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ1
pin. Reset clears MODE1.
1 = IRQ1 interrupt requests on falling edges and low levels
0 = IRQ1 interrupt requests on falling edges only
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A G R E E M E N T
Read:
$001E
N O N - D I S C L O S U R E
Address:
R E Q U I R E D
External Interrupt (IRQ)
IRQ Status and Control Register
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
External Interrupt (IRQ)
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External Interrupt (IRQ)
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15.1 Contents
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
15.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
15.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
15.5
Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
15.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
15.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
15.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
15.7
Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .230
15.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
15.8.1
Keyboard Status and Control Register . . . . . . . . . . . . . . .230
15.8.2
Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . .232
15.2 Introduction
The keyboard module provides eight independently maskable external
interrupts.
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Keyboard Interrupt Module (KBI)
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A G R E E M E N T
Section 15. Keyboard Interrupt Module (KBI)
N O N - D I S C L O S U R E
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R E Q U I R E D
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N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Keyboard Interrupt Module (KBI)
15.3 Features
Features of the keyboard interrupt module (KBI) include:
•
Eight Keyboard Interrupt Pins with Separate Keyboard Interrupt
Enable Bits and One Keyboard Interrupt Mask
•
Hysteresis Buffers
•
Programmable Edge-Only or Edge- and Level-Interrupt Sensitivity
•
Exit from Low-Power Modes
INTERNAL BUS
KBD0
TO PULLUP ENABLE
KB0IE
ACKK
VDD
.
.
.
D
CLR
VECTOR FETCH
DECODER
KEYF
RESET
Q
SYNCHRONIZER
CK
KEYBOARD
INTERRUPT FF
KBD7
KEYBOARD
INTERRUPT
REQUEST
IMASKK
MODEK
TO PULLUP ENABLE
KB7IE
Figure 15-1. Keyboard Module Block Diagram
Addr.
Register Name
Read:
Bit 7
6
5
4
3
2
0
0
0
0
KEYF
0
Keyboard Status and Control Write:
$000D
Register (KBSCR)
Reset:
$000E
Read:
Keyboard Interrupt Enable
Write:
Register (KBIER)
Reset:
ACKK
1
Bit 0
IMASKK
MODEK
0
0
0
0
0
0
0
0
KBIE7
KBIE6
KBIE5
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 15-2. I/O Register Summary
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Keyboard Interrupt Module (KBI)
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A keyboard interrupt is latched when one or more keyboard pins goes
low after all were high. The MODEK bit in the keyboard status and
control register controls the triggering mode of the keyboard interrupt.
•
If the keyboard interrupt is edge-sensitive only, a falling edge on a
keyboard pin does not latch an interrupt request if another
keyboard pin is already low. To prevent losing an interrupt request
on one pin because another pin is still low, software can disable
the latter pin while it is low.
•
If the keyboard interrupt is falling edge- and low level-sensitive, an
interrupt request is present as long as any keyboard pin is low.
If the MODEK bit is set, the keyboard interrupt pins are both falling edgeand low level-sensitive, and both of the following actions must occur to
clear a keyboard interrupt request:
•
Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the interrupt request.
Software may generate the interrupt acknowledge signal by
writing a logic 1 to the ACKK bit in the keyboard status and control
register (KBSCR). The ACKK bit is useful in applications that poll
the keyboard interrupt pins and require software to clear the
keyboard interrupt request. Writing to the ACKK bit prior to leaving
an interrupt service routine also can prevent spurious interrupts
due to noise. Setting ACKK does not affect subsequent transitions
on the keyboard interrupt pins. A falling edge that occurs after
writing to the ACKK bit latches another interrupt request. If the
keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the
program counter with the vector address at locations $FFE0 and
$FFE1.
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A G R E E M E N T
Writing to the KBIE7–KBIE0 bits in the keyboard interrupt enable register
independently enables or disables each port D pin as a keyboard
interrupt pin. Enabling a keyboard interrupt pin also enables its internal
pullup device. A logic 0 applied to an enabled keyboard interrupt pin
latches a keyboard interrupt request.
N O N - D I S C L O S U R E
15.4 Functional Description
R E Q U I R E D
Keyboard Interrupt Module (KBI)
Functional Description
Freescale Semiconductor, Inc.
R E Q U I R E D
Keyboard Interrupt Module (KBI)
•
The vector fetch or software clear and the return of all enabled keyboard
interrupt pins to logic 1 may occur in any order.
If the MODEK bit is clear, the keyboard interrupt pin is falling-edgesensitive only. With MODEK clear, a vector fetch or software clear
immediately clears the keyboard interrupt request.
A G R E E M E N T
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N O N - D I S C L O S U R E
Return of all enabled keyboard interrupt pins to logic 1 — As long
as any enabled keyboard interrupt pin is at logic 0, the keyboard
interrupt remains set.
Reset clears the keyboard interrupt request and the MODEK bit, clearing
the interrupt request even if a keyboard interrupt pin stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register
can be used to see if a pending interrupt exists. The KEYF bit is not
affected by the keyboard interrupt mask bit (IMASKK) which makes it
useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, use the data
direction register to configure the pin as an input and read the data
register.
NOTE:
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction
register. However, the data direction register bit must be a logic 0 for
software to read the pin.
15.5 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal
pullup to reach a logic 1. Therefore, a false interrupt can occur as soon
as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting the IMASKK bit in the
keyboard status and control register.
2. Enable the KBI pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register.
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3. Write to the ACKK bit in the keyboard status and control register
to clear any false interrupts.
4. Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged
immediately after enabling the pin. An interrupt signal on an edge- and
level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
R E Q U I R E D
Keyboard Interrupt Module (KBI)
Low-Power Modes
2. Write logic 1s to the appropriate port D data register bits.
3. Enable the KBI pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register.
15.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby
modes.
15.6.1 Wait Mode
The keyboard module remains active in wait mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of wait mode.
15.6.2 Stop Mode
The keyboard module remains active in stop mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of stop mode.
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A G R E E M E N T
1. Configure the keyboard pins as outputs by setting the appropriate
DDRD bits in data direction register D.
N O N - D I S C L O S U R E
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Another way to avoid a false interrupt:
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A G R E E M E N T
R E Q U I R E D
Keyboard Interrupt Module (KBI)
15.7 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard
interrupt latch can be cleared during the break state. The BCFE bit in the
break flag control register (BFCR) enables software to clear status bits
during the break state.
To allow software to clear the keyboard interrupt latch during a break
interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the
break state, it remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the keyboard
acknowledge bit (ACKK) in the keyboard status and control register
during the break state has no effect. (See 15.8.1 Keyboard Status and
Control Register.)
15.8 I/O Registers
These registers control and monitor operation of the keyboard module:
•
Keyboard status and control register (KBSCR)
•
Keyboard interrupt enable register (KBIER)
15.8.1 Keyboard Status and Control Register
The keyboard status and control register:
•
Flags keyboard interrupt requests
•
Acknowledges keyboard interrupt requests
•
Masks keyboard interrupt requests
•
Controls keyboard interrupt triggering sensitivity
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6
5
4
3
2
0
0
0
0
KEYF
0
Write:
Reset:
1
Bit 0
IMASKK
MODEK
0
0
ACKK
0
0
0
0
0
0
= Unimplemented
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Figure 15-3. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used
These read-only bits always read as logic 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending. Reset
clears the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
ACKK — Keyboard Acknowledge Bit
Writing a logic 1 to this write-only bit clears the keyboard interrupt
request. ACKK always reads as logic 0. Reset clears ACKK.
IMASKK — Keyboard Interrupt Mask Bit
Writing a logic 1 to this read/write bit prevents the output of the
keyboard interrupt mask from generating interrupt requests. Reset
clears the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard
interrupt pins. Reset clears MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
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A G R E E M E N T
Read:
Bit 7
N O N - D I S C L O S U R E
Address: $000D
R E Q U I R E D
Keyboard Interrupt Module (KBI)
I/O Registers
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15.8.2 Keyboard Interrupt Enable Register
The keyboard interrupt enable register enables or disables each port D
pin to operate as a keyboard interrupt pin.
Address: $000E
Bit 7
6
5
4
3
2
1
Bit 0
KBIE7
KBIE6
KBIE5
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 15-4. Keyboard Interrupt Enable Register (KBIER)
KBIE7–KBIE0 — Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard
interrupt pin to latch interrupt requests. Reset clears the keyboard
interrupt enable register.
1 = PDx pin enabled as keyboard interrupt pin
0 = PDx pin not enabled as keyboard interrupt pin
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A G R E E M E N T
R E Q U I R E D
Keyboard Interrupt Module (KBI)
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16.1 Contents
16.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
16.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
16.4.1
Flag Protection During Break Interrupts . . . . . . . . . . . . . .236
16.4.2
CPU During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . .236
16.4.3
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .236
16.4.4
COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . .236
16.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
16.5.1
Break Status and Control Register . . . . . . . . . . . . . . . . . .237
16.5.2
Break Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . .238
16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
16.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
16.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
16.2 Introduction
This section describes the break module. To enter a background
program, the break module can generate a break interrupt that stops
normal program flow at a defined address.
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A G R E E M E N T
Section 16. Break Module (BREAK)
N O N - D I S C L O S U R E
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R E Q U I R E D
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A G R E E M E N T
R E Q U I R E D
Break Module (BREAK)
16.3 Features
Features of the break module include:
•
Accessible I/O Registers during the Break Interrupt
•
CPU-Generated Break Interrupts
•
Software-Generated Break Interrupts
•
COP Disabling during Break Interrupts
16.4 Functional Description
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal (BKPT)
to the SIM. The SIM then causes the CPU to load the instruction register
with a software interrupt instruction (SWI) after completion of the current
CPU instruction. The program counter vectors to $FFFC and $FFFD
($FEFC and $FEFD in monitor mode).
These events can cause a break interrupt to occur:
•
A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
•
Software writes a logic 1 to the BRKA bit in the break status and
control register.
When a CPU-generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation. Figure 16-1 shows the structure of the break module.
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BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
IAB[15:0]
BKPT
TO SIM
CONTROL
8-BIT COMPARATOR
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BREAK ADDRESS REGISTER LOW
IAB[7:0]
Figure 16-1. Break Module Block Diagram
Addr.
$FE0C
$FE0D
$FE0E
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Bit 15
Break Address Register High
Write:
(BRKH)
Reset:
0
Read:
Break Address Register Low
Write:
(BRKL)
Reset:
Read:
BRKE
Break Status and Control Register
Write:
(BRKSCR)
Reset:
0
BRKA
0
= Unimplemented
Figure 16-2. Break I/O Register Summary
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IAB[15:8]
A G R E E M E N T
R E Q U I R E D
Break Module (BREAK)
Functional Description
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R E Q U I R E D
Break Module (BREAK)
16.4.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module
status bits can be cleared during the break state. The BCFE bit in the
break flag control register (BFCR) enables software to clear status bits
during the break state. (See 8.8.3 Break Flag Control Register and see
the break interrupts subsection for each module.)
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A G R E E M E N T
16.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
•
Loading the instruction register with the SWI instruction
•
Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD
in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
16.4.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
16.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt when VTST is present on the
RST pin.
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R E Q U I R E D
Break Module (BREAK)
Break Module Registers
16.5 Break Module Registers
•
Break status and control register (BRKSCR)
•
Break address register high (BRKH)
•
Break address register low (BRKL)
The break status and control register contains break module enable and
status bits.
Address:
$FE0E
Bit 7
6
BRKE
BRKA
0
0
Read:
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 16-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches.
Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
BRKA — Break Active Bit
This read/write status and control bit is set when a break address
match occurs. Writing a logic 1 to BRKA generates a break interrupt.
Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = Break address match
0 = No break address match
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A G R E E M E N T
16.5.1 Break Status and Control Register
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Three registers control and monitor operation of the break module:
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16.5.2 Break Address Registers
The break address registers contain the high and low bytes of the
desired breakpoint address. Reset clears the break address registers.
BRKH Address: $FE0C
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N O N - D I S C L O S U R E
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Read:
Write:
A G R E E M E N T
R E Q U I R E D
Break Module (BREAK)
Reset:
BRKL Address: $FE0D
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 16-4. Break Address Registers (BRKH and BRKL)
16.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby
modes.
16.6.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine,
the user can subtract 1 from the return address on the stack if SBSW is
set (see 8.7 Low-Power Modes). Clear the SBSW bit by writing logic 0
to it.
16.6.2 Stop Mode
A break interrupt causes exit from stop mode and sets the SBSW bit in
the break status register. See 8.8 SIM Registers.
General Release Specification
MC68HC08KL8 — Rev. 2.0
Break Module (BREAK)
For More Information On This Product,
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Section 17. Electrical Specifications
17.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
17.3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .240
17.4
Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .241
17.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
17.6
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .242
17.7
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
17.8
Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
17.9
USB DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .244
17.10 USB Low-Speed Source Electrical Characteristics . . . . . . . .245
17.11 USB Signaling Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
17.12 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . .247
17.13 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
17.2 Introduction
This section contains electrical and timing specifications. These values
are design targets and have not yet been fully tested.
MC68HC08KL8 — Rev. 2.0
General Release Specification
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
17.1 Contents
A G R E E M E N T
General Release Specification — MC68HC08KL8
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
17.3 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table. Keep VIn and VOut within the range VSS ≤ (VIn or
VOut) ≤ VDD. Connect unused inputs to the appropriate voltage level,
either VSS or VDD.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
Characteristic(1)
Symbol
Value
Unit
Supply Voltage
VDD,
VDDREG
–0.3 to +6.0
V
Regulator Supply Voltage
VDDREG
–0.3 to +6.0
V
Input Voltage
VIN
VSS –0.3 to VDD +0.3
V
Programming Voltage
VPP
VSS–0.3 to 14.0
V
I
± 25
mA
Storage Temperature
TSTG
–55 to +150
°C
Maximum Current Out of VSS
IMVSS
100
mA
Maximum Current Into VDD
IMVDD
100
mA
Maximum Current Per Pin
Excluding VDD and VSS
1. Voltages referenced to VSS
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. Refer to 17.6 DC Electrical Characteristics for guaranteed
operating conditions.
General Release Specification
MC68HC08KL8 — Rev. 2.0
Electrical Specifications
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Operating Temperature Range
Operating Voltage Range
Freescale Semiconductor, Inc...
Operating Regulator Voltage Range
Bypass Not Enabled
Bypass Enabled
Symbol
Value
Unit
TA
0 to 85
°C
VDD
4.4 to 5.5
V
VDDREG
4.4 to 5.5
3.0 to 3.6
V
17.5 Thermal Characteristics
Characteristic
Symbol
Value
Unit
Thermal Resistance
Quad Flat Pack, 52 Pins
θJA
70
°C/W
I/O Pin Power Dissipation
PI/O
User Determined
W
Power Dissipation(1)
PD
PD = (IDD x VDD) + PI/O =
K/(TJ + 273 °C)
W
Constant(2)
K
PD x (TA + 273 °C)
+ PD2 x θJA
W/°C
Average Junction Temperature
TJ
TA + (PD x θJA)
°C
TJM
100
°C
Maximum Junction Temperature
1. Power dissipation is a function of temperature.
2. K is a constant unique to the device. K can be determined for a known TA and measured PD.
With this value of K, PD and TJ can be determined for any value of TA.
MC68HC08KL8 — Rev. 2.0
General Release Specification
Electrical Specifications
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A G R E E M E N T
Characteristic
N O N - D I S C L O S U R E
17.4 Functional Operating Range
R E Q U I R E D
Electrical Specifications
Functional Operating Range
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
17.6 DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output High Voltage
(ILoad = –2.0 mA) All I/O Pins
VOH
VDD –0.8
—
—
V
Output Low Voltage
(ILoad = 1.6 mA) All I/O Pins
VOL
—
—
0.4
V
Input High Voltage
All Ports, IRQ1, RST, OSC1
VIH
0.7 x VDD
—
VDD
V
Input Low Voltage
All Ports, IRQ1, RST, OSC1
VIL
VSS
—
0.3 x VDD
V
Output High Current
(VOH = 2.1 V) Port C in LDD Mode
IOH
2.5
4.6
7
mA
Output Low Current
(VOL = 2.3 V) Port C in LDD Mode
IOL
7
13.2
20
mA
VDD Supply Current, fop = 1.5 MHz
Run, Low Speed USB(3)
Run, USB Suspended(3)
Wait, Low Speed USB(4)
Wait, USB Suspended(4)
Stop(5)
25 °C
0 °C to 85 °C
IDD
—
—
—
—
4.25
3.75
2.25
1.75
6.0
5.0
3.5
3.0
mA
mA
mA
mA
—
—
180
190
225
250
µA
µA
I/O Ports Hi-Z Leakage Current
IIL
—
—
± 10
µA
Input Current
IIn
—
—
±1
µA
Capacitance
Ports (as Input or Output)
COut
CIn
—
—
—
—
12
8
pF
POR ReArm Voltage(6)
VPOR
0
—
100
mV
RPOR
0.035
—
—
V/ms
Monitor Mode Entry Voltage
VTST
VDD + 2.5
13.5
V
Pullup Resistor
PA0–PA7, PB0–PB7, PC0–PC7, PD0–PD7,
RST, IRQ1
RPU
20
50
kΩ
POR Rise Time Ramp
Rate(7)
35
1. VDD = VDDREG = 4.4 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source (fXCLK = 6 MHz). All inputs 0.2 V from rail. No dc loads.
Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run
IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fXCLK = 6 MHz); all inputs 0.2 V from rail; no dc loads; less than
100 pF on all outputs. CL = 20 pF on OSC2; 15 kΩ ± 5% termination resistors on D+ and D– pins; all ports configured as inputs;
OSC2 capacitance linearly affects wait IDD
5. STOP IDD measured with USB in suspend mode; OSC1 grounded; REGOUT, D+, and D– not connected; no port pins sourcing
current.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
General Release Specification
MC68HC08KL8 — Rev. 2.0
Electrical Specifications
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Internal Operating
Frequency(2)
RST Input Pulse Width Low(3)
Symbol
Min
Max
Unit
fOP
—
1.5
MHz
tIRL
50
—
ns
Freescale Semiconductor, Inc...
1. VDD = VDDREG = 4.4 to 5.5 Vdc; VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
17.8 Oscillator Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency(1)
fXCLK
1
—
8
MHz
External Clock
Reference Frequency(1), (2)
fXCLK
dc
—
32
MHz
Crystal Load Capacitance(3)
CL
—
—
—
Crystal Fixed Capacitance(3)
C1
—
2 x CL
—
C2
—
2 x CL
—
RB
—
10 MΩ
—
RS
—
—
—
Crystal
Crystal Tuning
Capacitance(3)
Feedback Bias Resistor
Series
Resistor(3), (4)
1. The USB module is designed to function at fXCLK = 6 MHz. The values given here are oscillator specifications.
2. No more than 10% duty cycle deviation from 50%
3. Consult crystal vendor data sheet
4. Not required for high-frequency crystals
MC68HC08KL8 — Rev. 2.0
General Release Specification
Electrical Specifications
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A G R E E M E N T
Characteristic(1)
N O N - D I S C L O S U R E
17.7 Control Timing
R E Q U I R E D
Electrical Specifications
Control Timing
Freescale Semiconductor, Inc.
17.9 USB DC Electrical Characteristics
Characteristic(1)
Symbol
Conditions
Min
Typ
Max
Unit
Hi-Z State Data Line Leakage
ILO
0 V<VIn<3.3 V
–10
—
+10
µA
Differential Input Sensitivity
VDI
|(D+) – (D–)|
0.2
—
Differential Common Mode
Range
VCM
Includes VDI
Range
0.8
—
2.5
V
Single Ended Receiver
Threshold
VSE
0.8
—
2.0
V
Static Output Low
VOL
RL of 1.5 k
to 3.6 V
—
—
0.3
V
Static Output High
VOH
RL of 15 k
to GND
2.8
—
3.6
V
VREGOUT
IL = 4 mA
3.0
3.3
3.6
V
Regulator Supply Voltage(2), (3)
V
Regulator Bypass Capacitor
CREGBYPASS
—
0.1
—
µF
Regulator Bulk Capacitor
CREGBULK
1.0
—
—
µF
1. VDD = 4.4 –5.5 V, VSS = 0 Vdc, TA = 0 °C to +85 °C, unless otherwise noted
2. Transceiver pullup resistor of 1.5 kΩ ± 5% between REGOUT and D– and 15 kΩ ± 5% to ground termination resistors on D+
and D–.
3. No external current draw besides the USB-required external resistors should be connected to the REGOUT pin.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
General Release Specification
MC68HC08KL8 — Rev. 2.0
Electrical Specifications
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Freescale Semiconductor, Inc.
Symbol
Conditions
Min
Typ
Max
Unit
Internal Operating Frequency
fOP
—
—
1.5
—
MHz
Transition Time(2)
Rise Time
tR
CL = 50 pF
CL = 350 pF
CL = 50 pF
CL = 350 pF
75
—
75
—
—
300
—
300
tR/tF
80
—
120
%
1.3
—
2.0
V
1.4775
676.8
1.500
666.0
1.5225
656.8
Mbs
ns
Freescale Semiconductor, Inc...
Fall Time
tF
ns
Rise/Fall Time Matching
tRFM
Output Signal Crossover Voltage
VCRS
Low Speed Data Rate
tDRATE
1.5 Mbs ± 1.5%
Source Differential Driver Jitter
To Next Transition
For Paired Transitions
tUDJ1
tUDJ2
CL = 350 pF
Measured at
Crossover Point
–25
–10
—
—
25
10
ns
Receiver Data Jitter Tolerance
To Next Transition
For Paired Transitions
tDJR1
tDJR2
CL = 350 pF
Measured at
Crossover Point
–75
–45
—
—
75
45
ns
Source EOP Width
tEOPT
Measured at
Crossover Point
1.25
—
1.50
µs
Differential to EOP Transition Skew
tDEOP
Measured at
Crossover Point
–40
—
100
ns
Receiver EOP Width
Must Reject as EOP
Must Accept
tEOPR1
tEOPR2
330
675
—
—
—
—
ns
Measured at
Crossover Point
1. All voltages are measured from local ground, unless otherwise specified. All timings use a capacitive load of 50 pF, unless
otherwise specified. Low-speed timings have a 1.5-kΩ pullup to 2.8 V on the D– data line.
2. Transition times are measured from 10% to 90% of the data signal. The rising and falling edges should be smoothly transitioning (monotonic). Capacitive loading includes 50 pF of tester capacitance.
MC68HC08KL8 — Rev. 2.0
General Release Specification
Electrical Specifications
For More Information On This Product,
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A G R E E M E N T
Characteristic(1)
N O N - D I S C L O S U R E
17.10 USB Low-Speed Source Electrical Characteristics
R E Q U I R E D
Electrical Specifications
USB Low-Speed Source Electrical Characteristics
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
17.11 USB Signaling Levels
Signaling Levels
Bus State
From Originating Driver
At Receiver
Differential 1
(D+) – (D–) > 200 mV and D+ or D– > VSE (min)
Differential 0
(D+) – (D–) < –200 mV and D+ or D– > VSE (min)
Data J State
Low Speed
Full Speed
Differential 0
Differential 1
Data K State
Low Speed
Full Speed
Differential 1
Differential 0
Idle State
Low Speed
Full Speed
Differential 0 and D– > VSE (max) and D+ < VSE (min)
Differential 1 and D+ > VSE (max) and D– < VSE (min)
Resume State
Low Speed
Full Speed
Differential 1 and D+ > VSE (max) and D– < VSE (min)
Differential 0 and D– > VSE (max and D+ < VSE (min)
Start of Packet (SOP)
Data lines switch from Idle to K State
End of Packet (EOP)
D+ and D– < VSE (min) for 2 Bit Times(1)
Followed by an Idle for 1 Bit Time
D+ and D– < VSE (min) for 1 Bit
Time(2) Followed by a J State
Disconnect Upstream Only
D+ and D– < VSE (max) for 2.5µs
Connect Upstream Only
D+ or D– > VSE (max) for 2.5µs
Reset Downstream Only
D+ and D– < VSE for 10 ms
D+ and D– < VSE (min) for 2.5µs;
Must be Recognized within 5.5 µs)(3)
1. The width of EOP is defined in bit times relative to the speed of transmission.
2. The width of EOP is defined in bit times relative to the device type receiving the EOP.
3. These times apply to an active device that is not in the suspend state.
General Release Specification
MC68HC08KL8 — Rev. 2.0
Electrical Specifications
For More Information On This Product,
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Characteristic
Input Capture Pulse Width
Input Clock Pulse Width
Symbol
Min
Max
Unit
tTIH, tTIL
125
—
ns
tTCH, tTCL
(1/fOP) + 5
—
ns
Characteristic
RAM Data Retention Voltage
Symbol
Min
Typ
Max
Unit
VRM
1.3
—
—
V
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
17.13 Memory Characteristics
A G R E E M E N T
17.12 Timer Interface Module Characteristics
R E Q U I R E D
Electrical Specifications
Timer Interface Module Characteristics
MC68HC08KL8 — Rev. 2.0
General Release Specification
Electrical Specifications
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N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
General Release Specification
MC68HC08KL8 — Rev. 2.0
Electrical Specifications
For More Information On This Product,
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Section 18. Mechanical Specifications
18.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
18.3
Quad Flat Pack (Case 848B-04). . . . . . . . . . . . . . . . . . . . . . .250
18.4
Shrink Dual In-Line Package (Case 858-01) . . . . . . . . . . . . .251
18.2 Introduction
The MC68HC08KL8 is available in a 52-lead plastic quad flat pack
(QFP) package and a 42-lead shrink dual in-line package (SDIP). This
section gives the dimensions for these packages.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
18.1 Contents
A G R E E M E N T
General Release Specification — MC68HC08KL8
R E Q U I R E D
Freescale Semiconductor, Inc.
MC68HC08KL8 — Rev. 2.0
General Release Specification
Mechanical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
18.3 Quad Flat Pack (Case 848B-04)
B
L
B
39
27
S
S
D
S
C A–B
V
B
M
L
F
M
–B–
0.20 (0.008)
H A–B
S
DETAIL A
0.20 (0.008)
A G R E E M E N T
Freescale Semiconductor, Inc...
–A–, –B–, –D–
DETAIL A
–A–
N O N - D I S C L O S U R E
D
26
40
0.05 (0.002) A–B
R E Q U I R E D
Mechanical Specifications
J
N
14
52
1
13
BASE METAL
D
–D–
0.20 (0.008)
M
B
H A–B
0.02 (0.008)
S
D
S
M
C A–B
S
D
S
SECTION B–B
0.05 (0.002) A–B
V
0.20 (0.008)
M
C A–B
S
D
S
DETAIL C
M_
C
E
–H–
DATUM
PLANE
0.10 (0.004)
H
–C–
M_
G
U_
R
Q_
K
T
W
X
DETAIL C
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT
DATUM PLANE –H–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE –H–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
Q
R
S
T
U
V
W
X
General Release Specification
MILLIMETERS
MIN
MAX
10.10
9.90
9.90
10.10
2.10
2.45
0.22
0.38
2.00
2.10
0.22
0.33
0.65 BSC
–––
0.25
0.13
0.23
0.65
0.95
7.80 REF
5_
10_
0.13
0.17
0_
7_
0.13
0.30
12.95
13.45
0.13
–––
0_
–––
12.95
13.45
0.35
0.45
1.6 REF
INCHES
MIN
MAX
0.398
0.390
0.390
0.398
0.083
0.096
0.009
0.015
0.079
0.083
0.009
0.013
0.026 BSC
–––
0.010
0.005
0.009
0.026
0.037
0.307 REF
5_
10_
0.005
0.007
0_
7_
0.005
0.012
0.510
0.530
0.005
–––
0_
–––
0.510
0.530
0.014
0.018
0.063 REF
MC68HC08KL8 — Rev. 2.0
Mechanical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
-A42
! ! %
! ! ! #
! " $" 22
-B1
21
L
H
-T
G
F
D 42 PL
N
K
! M
J 42 PL
°
°
°
°
! N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
C
A G R E E M E N T
18.4 Shrink Dual In-Line Package (Case 858-01)
R E Q U I R E D
Mechanical Specifications
Shrink Dual In-Line Package (Case 858-01)
MC68HC08KL8 — Rev. 2.0
General Release Specification
Mechanical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Mechanical Specifications
General Release Specification
MC68HC08KL8 — Rev. 2.0
Mechanical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc...
19.1 Contents
19.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
19.3
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
19.2 Introduction
This section contains ordering information.
19.3 MC Order Numbers
Table 19-1. MC Order Numbers
MC Order Number
Operating
Temperature Range
MC68HC08KL8FB(1)
0 °C to + 85 °C
MC68HC08KL8B(2)
0 °C to + 85 °C
1. FB = Quad Flat Pack
2. B = Shrink Dual In-Line Package
MC68HC08KL8 — Rev. 2.0
General Release Specification
Ordering Information
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A G R E E M E N T
Section 19. Ordering Information
N O N - D I S C L O S U R E
General Release Specification — MC68HC08KL8
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc...
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Ordering Information
General Release Specification
MC68HC08KL8 — Rev. 2.0
Ordering Information
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Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
For More Information On This Product,
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Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
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HC08KL8GRS/D