Freescale Semiconductor Data Sheet: Technical Data Document Number: MC9S08PT16 Rev. 1, 7/4/2012 MC9S08PT16 MC9S08PT16 Series Support: MC9S08PT16 and MC9S08PT8 Features • 8-Bit S08 central processor unit (CPU) – Up to 20 MHz bus at 2.7 V to 5.5 V across temperature range of -40 °C to 105 °C – Supporting up to 40 interrupt/reset sources – Supporting up to four-level nested interrupt – On-chip memory – Up to 16 KB flash read/program/erase over full operating voltage and temperature – Up to 256 byte EEPROM; 2-byte erase sector; program and erase while executing flash – Up to 2048 byte random-access memory (RAM) – Flash and RAM access protection • Power-saving modes – One low-power stop mode; reduced power wait mode – Peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode • Clocks – Oscillator (XOSC) - loop-controlled Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 39.0625 kHz or 4 MHz to 20 MHz – Internal clock source (ICS) - containing a frequencylocked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allowing 1% deviation across temperature range of 0 °C to 70 °C and 2% deviation across temperature range of -40 °C to 105 °C; up to 20 MHz • System protection – Watchdog with independent clock source – Low-voltage detection with reset or interrupt; selectable trip points – Illegal opcode detection with reset – Illegal address detection with reset • Development support – Single-wire background debug interface – Breakpoint capability to allow three breakpoints setting during in-circuit debugging – On-chip in-circuit emulator (ICE) debug module containing two comparators and nine trigger modes • Peripherals – ACMP - one analog comparator with both positive and negative inputs; separately selectable interrupt on rising and falling comparator output; filtering – ADC - 12-channel, 12-bit resolution; 2.5 µs conversion time; data buffers with optional watermark; automatic compare function; internal bandgap reference channel; operation in stop mode; optional hardware trigger – CRC - programmable cyclic redundancy check module – FTM - two flex timer modulators modules including one 6-channel and one 2-channel ones; 16-bit counter; each channel can be configured for input capture, output compare, edge- or center-aligned PWM mode – IIC - One inter-integrated circuit module; up to 400 kbps; multi-master operation; programmable slave address; supporting broadcast mode and 10-bit addressing – MTIM - One modulo timer with 8-bit prescaler and overflow interrupt – RTC - 16-bit real timer counter (RTC) – SCI - two serial communication interface (SCI/ UART) modules optional 13-bit break; full duplex non-return to zero (NRZ); LIN extension support – SPI - one 8-bit serial peripheral interface (SPI) modules; full-duplex or single-wire bidirectional; master or slave mode – TSI - supporting up to 16 external electrodes; configurable software or hardware scan trigger; fully support freescale touch sensing software library; capability to wake MCU from stop3 mode Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2011–2012 Freescale Semiconductor, Inc. • Input/Output – 37 GPIOs including one output-only pin – One 8-bit keyboard interrupt module (KBI) – Two true open-drain output pins – Four, ultra-high current sink pins supporting 20 mA source/sink current • Package options – 44-pin LQFP – 32-pin LQFP – 20-pin SOIC; 20-pin TSSOP – 16-pin TSSOP MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. 2 Freescale Semiconductor, Inc. Table of Contents 1 Ordering parts...........................................................................4 5.2.2 Debug trace timing specifications.........................15 1.1 Determining valid orderable parts......................................4 5.2.3 FTM module timing...............................................15 2 Part identification......................................................................4 2.1 Description.........................................................................4 5.3 Thermal specifications.......................................................16 5.3.1 Thermal characteristics.........................................16 2.2 Format...............................................................................4 6 Peripheral operating requirements and behaviors....................18 2.3 Fields.................................................................................4 6.1 External oscillator (XOSC) and ICS characteristics...........18 2.4 Example............................................................................5 6.2 NVM specifications............................................................19 3 Parameter Classification...........................................................5 6.3 Analog...............................................................................21 4 Ratings......................................................................................5 6.3.1 ADC characteristics...............................................21 4.1 Thermal handling ratings...................................................5 6.3.2 Analog comparator (ACMP) electricals.................23 4.2 Moisture handling ratings..................................................6 4.3 ESD handling ratings.........................................................6 4.4 Voltage and current operating ratings...............................6 5 General.....................................................................................7 5.1 Nonswitching electrical specifications...............................7 6.4 Communication interfaces.................................................24 6.4.1 SPI switching specifications..................................24 6.5 Human-machine interfaces (HMI)......................................27 6.5.1 TSI electrical specifications...................................27 7 Dimensions...............................................................................27 5.1.1 DC characteristics.................................................7 5.1.2 Supply current characteristics...............................12 8 Pinout........................................................................................28 5.1.3 EMC performance.................................................13 8.1 Signal multiplexing and pin assignments...........................28 5.2 Switching specifications.....................................................13 8.2 Device pin assignment......................................................30 5.2.1 Control timing........................................................13 7.1 Obtaining package dimensions.........................................27 9 Revision history.........................................................................32 MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. Freescale Semiconductor, Inc. 3 Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: PT16 and PT8. 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.2 Format Part numbers for this device have the following format: MC 9 S08 PT AA B CC 2.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values MC Qualification status • MC = fully qualified, general market flow 9 Memory • 9 = flash based S08 Core • S08 = 8-bit CPU PT Device family • PT AA Approximate flash size in KB • 16 = 16 KB • 8 = 8 KB B Temperature range (°C) • V = –40 to 105 Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. 4 Freescale Semiconductor, Inc. Parameter Classification Field CC Description Package designator Values • • • • • LD = 44-LQFP LC = 32-LQFP TJ = 20-TSSOP WJ = 20-SOIC TG = 16-TSSOP 2.4 Example This is an example part number: MC9S08PT16VLD 3 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table 1. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 4 Ratings 4.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. Freescale Semiconductor, Inc. 5 Ratings 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.3 ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -6000 +6000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 Latch-up current at ambient temperature of 105°C -100 +100 mA ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 4.4 Voltage and current operating ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in below table may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this document. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled. Symbol Description Min. Max. Unit VDD Supply voltage –0.3 5.8 V IDD Maximum current into VDD — 120 mA Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. 6 Freescale Semiconductor, Inc. General Symbol Description Min. Max. Unit VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 VDD + 0.3 V VAIO Analog1, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V Instantaneous maximum current single pin limit (applies to all port pins) –25 25 mA VDD – 0.3 VDD + 0.3 V ID VDDA Analog supply voltage 1. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 5 General 5.1 Nonswitching electrical specifications 5.1.1 DC characteristics This section includes information about power supply requirements and I/O pin characteristics. Table 2. DC characteristics Symbol C — — VOH P Min Typical1 Max Unit — 2.7 — 5.5 V 5 V, Iload = -2 mA VDD - 1.5 — — V 3 V, Iload = -0.6 mA VDD - 0.8 — — V High current drive pins, high-drive strength2 5 V, Iload = -20 mA VDD - 1.5 — — V 3 V, Iload = -6 mA VDD - 0.8 — — V Max total IOH for all ports 5V — — -100 mA 3V — — -60 — — 1.5 V 3 V, Iload = 0.6 mA — — 0.8 V 5 V, Iload =20 mA — — 1.5 V 3 V, Iload = 6 mA — — 0.8 V 5V — — 100 mA 3V — — 60 Descriptions Operating voltage Output high voltage All I/O pins, low-drive strength C P C IOHT VOL D P Output high current Output low voltage All I/O pins, low-drive 5 V, Iload = 2 strength mA C P High current drive pins, high-drive strength2 C IOLT D Output low current Max total IOL for all ports Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. Freescale Semiconductor, Inc. 7 Nonswitching electrical specifications Table 2. DC characteristics (continued) Symbol C VIH P VIL P Min Typical1 Max Unit VDD>4.1V 0.70 × VDD — — V VDD>2.7V 0.85 × VDD — — VDD>4.1V — — 0.35 × VDD VDD>2.7V — — 0.30 × VDD Descriptions Input high voltage All digital inputs Input low voltage All digital inputs V Vhys C Input hysteresis All digital inputs — 0.06 × VDD — — mV |IIn| P Input leakage current All input only pins (per pin) VIN = VDD or VSS — 0.1 1 µA |IOZ| P Hi-Z (offstate) leakage current All input/output (per pin) VIN = VDD or VSS — 0.1 1 µA |IOZTOT| C Total leakage All input only and I/O VIN = VDD or combined for VSS all inputs and Hi-Z pins — — 2 µA RPU P Pullup resistors All digital inputs, when enabled (all I/O pins other than PTA5/ IRQ/TCLK/RESET — 17.5 — 52.5 kΩ RPU3 P Pullup resistors PTA5/IRQ/TCLK/ RESET — 17.5 — 52.5 kΩ IIC D DC injection current4, 5, 6 Single pin limit VIN < VSS, VIN > VDD -0.2 — 2 mA -5 — 25 Total MCU limit, includes sum of all stressed pins CIn C Input capacitance, all pins — — — 8 pF VRAM C RAM retention voltage — 2.0 — — V 1. Typical values are measured at 25 °C. Characterized, not tested. 2. Only PTB4, PTB5, PTD0, PTD1 support ultra high current output. 3. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured externally on the pin. 4. All functional non-supply pins, except for PTA5, are internally clamped to VSS and VDD. 5. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the large one. 6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is higher than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current higher than maximum injection current when the MCU is not consuming power, such as no system clock is present, or clock rate is very low (which would reduce overall power consumption). Table 3. LVD and POR Specification Symbol C VPOR D VLVDH C Description POR re-arm voltage1 Falling low-voltage detect threshold - high range (LVDV = 1)2 Min Typ Max Unit 1.5 1.75 2.0 V 4.2 4.3 4.4 V Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. 8 Freescale Semiconductor, Inc. Nonswitching electrical specifications Table 3. LVD and POR Specification (continued) Symbol C VLVW1H C VLVW2H C VLVW3H C VLVW4H C VHYSH C VLVDL C VLVDW1L C VLVDW2L C VLVDW3L C VLVDW4L Description Min Typ Max Unit Level 1 falling (LVWV = 00) 4.3 4.4 4.5 V Level 2 falling (LVWV = 01) 4.5 4.5 4.6 V Level 3 falling (LVWV = 10) 4.6 4.6 4.7 V Level 4 falling (LVWV = 11) 4.7 4.7 4.8 V High range low-voltage detect/warning hysteresis — 100 — mV Falling low-voltage detect threshold - low range (LVDV = 0) 2.56 2.61 2.66 V Level 1 falling (LVWV = 00) 2.62 2.7 2.78 V Level 2 falling (LVWV = 01) 2.72 2.8 2.88 V Level 3 falling (LVWV = 10) 2.82 2.9 2.98 V C Level 4 falling (LVWV = 11) 2.92 3.0 3.08 V VHYSDL C Low range low-voltage detect hysteresis — 40 — mV VHYSWL C Low range low-voltage warning hysteresis — 80 — mV VBG P Buffered bandgap output 3 1.14 1.16 1.18 V Falling lowvoltage warning threshold high range Falling lowvoltage warning threshold low range 1. Maximum is highest voltage that POR is guaranteed. 2. Rising thresholds are falling threshold + hysteresis. 3. voltage Factory trimmed at VDD = 5.0 V, Temp = 25 °C MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. Freescale Semiconductor, Inc. 9 Nonswitching electrical specifications 0.7 0.6 VDD=3V 0.5 VDD-VOH(V) 0.4 VDD=5V 0.3 0.2 0.1 0 1 2 3 4 IOH(mA) 5 6 Figure 1. Typical IOH Vs. VDD-VOH 0.8 0.7 VDD=3V 0.6 0.5 VDD=5V VDD-VOH(V) 0.4 0.3 0.2 0.1 0 5 10 15 IOH(mA) 20 25 Figure 2. Typical IOH Vs. VDD-VOH (High current drive) MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. 10 Freescale Semiconductor, Inc. Nonswitching electrical specifications 0.6 VDD=3V 0.5 0.4 VDD=5V VOL(V) 0.3 0.2 0.1 0 1 2 3 4 IOL(mA) 5 6 Figure 3. Typical IOL Vs. VOL 0.7 0.6 VDD=3V 0.5 VOL(V) 0.4 VDD=5V 0.3 0.2 0.1 0 5 10 15 IOL(mA) 20 25 Figure 4. Typical IOL Vs. VOL (High current drive) MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. Freescale Semiconductor, Inc. 11 Nonswitching electrical specifications 5.1.2 Supply current characteristics This section includes information about power supply current in various operating modes. Table 4. Supply current characteristics Num C Parameter Symbol Bus Freq VDD (V) Typical1 Max Unit Temp 1 C Run supply current FEI mode, all modules on; run from flash RIDD 20 MHz 5 7.60 — mA -40 to 105 °C 10 MHz 4.65 — 1 MHz 1.90 — 7.05 — mA -40 to 105 °C mA -40 to 105 °C mA -40 to 105 °C mA -40 to 105 °C µA -40 to 105 °C C 2 C 20 MHz C 10 MHz 4.40 — 1 MHz 1.85 — 5.88 — 10 MHz 3.70 — 1 MHz 1.85 — 5.35 — C C 3 Run supply current FEI mode, all modules off & gated; run from flash RIDD 20 MHz C 10 MHz 3.42 — 1 MHz 1.80 — P Run supply current FBE mode, all modules on; run from RAM RIDD C P C C Run supply current FBE mode, all modules off & gated; run from RAM RIDD C C 10.9 14.0 10 MHz 6.10 — 1 MHz 1.69 — 8.18 — 10 MHz 5.14 — 1 MHz 1.44 — 8.50 13.0 5.07 — 1.59 — 6.11 — 10 MHz 4.10 — 1 MHz 1.34 — 5.95 — 10 MHz 3.50 — 1 MHz 1.24 — 5.45 — 10 MHz 3.25 — 1 MHz 1.20 — 20 MHz WIDD 20 MHz 20 MHz Stop3 mode supply current no clocks active (except 1kHz LPO clock) 5 3 5 1 MHz 20 MHz Wait mode current FEI mode, all modules on 3 10 MHz C 6 20 MHz 20 MHz C 5 5 C C 4 20 MHz 3 S3IDD 3 5 3 — 5 4.6 — — 3 4.5 — -40 to 105 °C Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. 12 Freescale Semiconductor, Inc. Switching specifications Table 4. Supply current characteristics (continued) Num C Parameter Symbol Bus Freq VDD (V) Typical1 Max Unit Temp 7 C ADC adder to stop3 — — 5 40 — µA -40 to 105 °C C ADLPC = 1 3 39 — 5 121 — µA -40 to 105 °C 3 120 — 5 128 — µA -40 to 105 °C 3 124 — ADLSMP = 1 ADCO = 1 MODE = 10B ADICLK = 11B 8 C TSI adder to stop32 C PS = 010B — — NSCN = 0x0F EXTCHRG = 0 REFCHRG = 0 DVOLT = 01B 9 C LVD adder to stop33 — C — 1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value. 2. The current varies with TSI configuration and capacity of touch electrode. Please refer toTSI electrical specifications. 3. LVD is periodically woken up from stop3 by 5% duty cycle. The period is equal to or less than 2 ms. 5.1.3 EMC performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. 5.2 Switching specifications 5.2.1 Control timing Table 5. Control timing Symbol Min Typical1 Max Unit Bus frequency (tcyc = 1/fBus) fBus DC — 20 MHz Internal low power oscillator frequency fLPO — 1.0 — KHz Num C Rating 1 P 2 C Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. Freescale Semiconductor, Inc. 13 Switching specifications Table 5. Control timing (continued) Num C 3 D Rating External reset pulse width2 Symbol Min textrst 1.5 × Typical1 Max Unit — — ns tSelf_reset 4 D Reset low drive trstdrv 34 × tcyc — — ns 5 D BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes tMSSU 500 — — ns 6 D BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes3 tMSH 100 — — ns 7 D Asynchronous path2 tILIH 100 — — ns Synchronous path4 tIHIL 1.5 × tcyc — — ns Asynchronous path2 tILIH — — ns Synchronous path tIHIL 1.5 × tcyc — — ns Port rise and fall time Normal drive strength (HDRVE_PTXx = 0) (load = 50 pF)5 — tRise — 10.2 — ns tFall — 9.5 — ns Port rise and fall time Extreme high drive strength (HDRVE_PTXx = 1) (load = 50 pF)5 — tRise — 5.4 — ns tFall — 4.6 — ns IRQ pulse width D 8 D Keyboard interrupt pulse width D 9 C C C C 100 1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated. 2. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. 3. To enter BDM mode following a POR, BKGD/MS must be held low during the powerup and for a hold time of tMSH after VDD rises above VLVD. 4. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized. 5. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 105 °C. textrst RESET PIN Figure 5. Reset timing tIHIL KBIPx IRQ/KBIPx tILIH Figure 6. IRQ/KBIPx timing MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. 14 Freescale Semiconductor, Inc. Switching specifications 5.2.2 Debug trace timing specifications Table 6. Debug trace operating behaviors Symbol Description Min. Max. Unit tcyc Clock period Frequency dependent MHz twl Low pulse width 2 — ns twh High pulse width 2 — ns tr Clock and data rise time — 3 ns tf Clock and data fall time — 3 ns ts Data setup 3 — ns th Data hold 2 — ns Figure 7. TRACE_CLKOUT specifications TRACE_CLKOUT Ts Ts Th Th TRACE_D[3:0] Figure 8. Trace data specifications 5.2.3 FTM module timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 7. FTM input timing No. C Function Symbol Min Max Unit 1 D External clock frequency fTCLK 0 fBus/4 Hz Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. Freescale Semiconductor, Inc. 15 Thermal specifications Table 7. FTM input timing (continued) No. C Function Symbol Min Max Unit 2 D External clock period tTCLK 4 — tcyc 3 D External clock high time tclkh — tcyc 4 D External clock low time tclkl 1.5 — tcyc 5 D Input capture pulse width tICPW 1.5 — tcyc 1.5 tTCLK tclkh TCLK tclkl Figure 9. Timer external clock tICPW FTMCHn FTMCHn tICPW Figure 10. Timer input capture pulse 5.3 Thermal specifications 5.3.1 Thermal characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is userdetermined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. 16 Freescale Semiconductor, Inc. Thermal specifications Table 8. Thermal characteristics Rating Symbol Value Unit Operating temperature range (packaged) TA TL to TH -40 to 105 °C Junction temperature range TJ -40 to 150 °C Thermal resistance single-layer board 44-pin LQFP θJA 76 °C/W 32-pin LQFP θJA 88 °C/W 20-pin SOIC θJA 82 °C/W 20-pin TSSOP θJA 116 °C/W 16-pin TSSOP θJA 130 °C/W Thermal resistance four-layer board 44-pin LQFP θJA 54 °C/W 32-pin LQFP θJA 59 °C/W 20-pin SOIC θJA 54 °C/W 20-pin TSSOP θJA 76 °C/W 16-pin TSSOP θJA 87 °C/W The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) Where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts - chip internal power PI/O = Power dissipation on input and output pins - user determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K ÷ (TJ + 273 °C) Solving the equations above for K gives: K = PD × (TA + 273 °C) + θJA × (PD)2 where K is a constant pertaining to the particular part. K can be determined by measuring PD (at equilibrium) for an known TA. Using this value of K, the values of PD and TJ can be obtained by solving the above equations iteratively for any value of TA. MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. Freescale Semiconductor, Inc. 17 Peripheral operating requirements and behaviors 6 Peripheral operating requirements and behaviors 6.1 External oscillator (XOSC) and ICS characteristics Table 9. XOSC and ICS specifications (temperature range = -40 to 105 °C ambient) Symbol Min Typical1 Max Unit Low range (RANGE = 0) flo 32 — 40 kHz High range (RANGE = 1) FEE or FBE mode2 fhi 4 — 20 MHz C High range (RANGE = 1), high gain (HGO = 1), FBELP mode fhi 4 — 20 MHz C High range (RANGE = 1), low power (HGO = 0), FBELP mode fhi 4 — 20 MHz Num C 1 C C 2 D 3 D 4 5 Oscillator crystal or resonator Load capacitors Feedback resistor Low Frequency, Low-Power Mode4 — — — MΩ Low Frequency, High-Gain Mode — 10 — MΩ High Frequency, LowPower Mode — 1 — MΩ High Frequency, High-Gain Mode — 1 — MΩ — — — kΩ — 200 — kΩ — — — kΩ 4 MHz — 0 — kΩ 8 MHz — 0 — kΩ 16 MHz — 0 — kΩ — 1000 — ms — 800 — ms — 3 — ms — 1.5 — ms tIRST — 20 50 µs fextal 0.03125 — 5 MHz 0 — 20 MHz Low-Power Mode 4 D Series resistor High Frequency Mode4 D Series resistor High Frequency, High-Gain Mode D C C C C 7 T 8 D D Crystal start-up time Low range = 32.768 KHz crystal; High range = 20 MHz crystal5, 6 RF RS High-Gain Mode Low-Power Low range, low power RS tCSTL Low range, high power High range, low power tCSTH High range, high power Internal reference start-up time Square wave input clock frequency See Note3 C1, C2 Series resistor Low Frequency D D 6 Characteristic FEE or FBE mode2 FBELP mode 9 P Average internal reference frequency trimmed fint_t — 32.768 — kHz 10 P DCO output frequency range - trimmed fdco_t 16 — 20 MHz Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. 18 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 9. XOSC and ICS specifications (temperature range = -40 to 105 °C ambient) (continued) Num C 11 P C Characteristic Total deviation of DCO output from trimmed frequency5 Symbol Min Typical1 Max Unit Δfdco_t — — ±2.0 %fdco Over full voltage and temperature range Over fixed voltage and temperature range of 0 to 70 °C ±1.0 12 C FLL acquisition time5, 7 tAcquire — — 2 ms 13 C Long term jitter of DCO output clock (averaged over 2 ms interval)8 CJitter — 0.02 0.2 %fdco 1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value. 2. When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz. 3. See crystal or resonator manufacturer's recommendation. 4. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO = 0. 5. This parameter is characterized and not tested on each device. 6. Proper PC board layout procedures must be followed to achieve specifications. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, DMX32 bit is changed, DRS bit is changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. XOSC EXTAL XTAL RF C1 RS Crystal or Resonator C2 Figure 11. Typical crystal or resonator circuit MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. Freescale Semiconductor, Inc. 19 Peripheral operating requirements and behaviors 6.2 NVM specifications This section provides details about program/erase times and program-erase endurance for the flash and EEPROM memories. Table 10. Flash characteristics 1. 2. 3. 4. C Characteristic Symbol Min1 Typical2 Max3 Unit4 D Supply voltage for program/erase -40 °C to 105 °C Vprog/erase 2.7 — 5.5 V D Supply voltage for read operation VRead 2.7 — 5.5 V D NVM Bus frequency fNVMBUS 1 — 25 MHz D NVM Operating frequency fNVMOP 0.8 — 1.05 MHz D Erase Verify All Blocks tVFYALL — — 17030 tcyc D Erase Verify Flash Block tRD1BLK — — 16977 tcyc D Erase Verify EEPROM Block tRD1BLK — — 843 tcyc D Erase Verify Flash Section tRD1SEC — — 517 tcyc D Erase Verify EEPROM Section tDRD1SEC 0.10 0.10 0.11 ms D Read Once tRDONCE — — 455 tcyc D Program Flash (2 word) tPGM2 0.12 0.12 0.14 ms D Program Flash (4 word) tPGM4 0.20 0.21 0.24 ms D Program Once tPGMONCE 0.20 0.21 0.24 ms D Program EEPROM (1 Byte) tDPGM1 0.02 0.02 0.02 ms D Program EEPROM (2 Byte) tDPGM2 0.17 0.18 0.20 ms D Erase All Blocks tERSALL 96.01 100.78 125.80 ms D Erase Flash Block tERSBLK 95.98 100.75 125.76 ms D Erase Flash Sector tERSPG 19.10 20.05 25.05 ms D Erase EEPROM Sector tDERSPG 4.81 5.05 6.30 ms D Unsecure Flash tUNSECU 96.01 100.78 125.80 ms D Verify Backdoor Access Key tVFYKEY — — 469 tcyc D Set User Margin Level tMLOADU — — 442 tcyc C FLASH Program/erase endurance TL to TH = -40 °C to 105 °C nFLPE 10 k 100 k — Cycles C EEPROM Program/erase endurance TL to TH = -40 °C to 105 °C nFLPE 50 k 500 k — Cycles C Data retention at an average junction temperature of TJavg = 85°C after up to 10,000 program/erase cycles tD_ret 15 100 — years Minimun times are based on maxmum fNVMOP and maximum fNVMBUS Typical times are based on typical fNVMOP and maximum fNVMBUS Maximum times are based on minimum fNVMOP and maximum fNVMBUS tcyc = 1 / fNVMBUS Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section. MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. 20 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.3 Analog 6.3.1 ADC characteristics Table 11. 5 V 12-bit ADC operating conditions Characteri stic Conditions Symb Min Typ1 Max Unit Comment Supply voltage Absolute VDDA 2.7 — 5.5 V — Delta to VDD (VDD-VDDAD) ΔVDDA -100 0 +100 mV )2 ΔVSSA -100 0 +100 mV Input voltage VADIN VREFL — VREFH V Input capacitance CADIN — 4.5 5.5 pF Input resistance RADIN — 3 5 kΩ — RAS — — 2 kΩ External to MCU — — 5 — — 5 — — 10 — — 10 0.4 — 8.0 MHz — 0.4 — 4.0 Ground voltage Analog source resistance Delta to VSS (VSS-VSSA • • 12-bit mode fADCK > 4 MHz fADCK < 4 MHz • • 10-bit mode fADCK > 4 MHz fADCK < 4 MHz 8-bit mode (all valid fADCK) ADC conversion clock frequency High speed (ADLPC=0) Low power (ADLPC=1) fADCK 1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. DC potential difference. MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. Freescale Semiconductor, Inc. 21 Peripheral operating requirements and behaviors SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT z ADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection ZAS R AS ADC SAR ENGINE R ADIN v ADIN v AS C AS R ADIN INPUT PIN R ADIN INPUT PIN R ADIN INPUT PIN C ADIN Figure 12. ADC input impedance equivalency diagram Table 12. 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) Characteristic Conditions Supply current C Symb Min Typ1 Max Unit T IDDA — 133 — µA T IDDA — 218 — µA T IDDA — 327 — µA T IDDAD — 582 990 µA T IDDA — 0.011 1 µA ADLPC = 1 ADLSMP = 1 ADCO = 1 Supply current ADLPC = 1 ADLSMP = 0 ADCO = 1 Supply current ADLPC = 0 ADLSMP = 1 ADCO = 1 Supply current ADLPC = 0 ADLSMP = 0 ADCO = 1 Supply current Stop, reset, module off Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. 22 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 12. 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Characteristic Conditions C Symb Min Typ1 Max Unit ADC asynchronous clock source High speed (ADLPC = 0) P fADACK 2 3.3 5 MHz 1.25 2 3.3 — 20 — — 40 — — 3.5 — — 23.5 — — ±5.0 — Low power (ADLPC = 1) Conversion time (including sample time) Short sample (ADLSMP = 0) Sample time Short sample (ADLSMP = 0) T tADC Long sample (ADLSMP = 1) T tADS Long sample (ADLSMP = 1) Total unadjusted Error2 Differential NonLiniarity 12-bit mode T ETUE 10-bit mode P — ±1.5 ±2.0 8-bit mode P — ±0.7 ±1.0 12-bit mode T — ±1.0 — 10-bit mode4 P — ±0.25 ±0.5 — ±0.15 ±0.25 — ±1.0 — DNL mode4 P Integral Non-Linearity 12-bit mode T 10-bit mode T — ±0.3 ±0.5 8-bit mode T — ±0.15 ±0.25 12-bit mode C — ±2.0 — 10-bit mode P — ±0.25 ±1.0 8-bit mode P — ±0.65 ±1.0 12-bit mode T — ±2.5 — 10-bit mode T — ±0.5 ±1.0 8-bit mode T — ±0.5 ±1.0 ≤12 bit modes D EQ — — ±0.5 all modes D EIL -40°C– 25°C D m 8-bit Zero-scale Full-scale error5 error6 Quantization error Input leakage error7 Temp sensor slope INL EZS EFS 25°C– 125°C Temp sensor voltage 25°C D VTEMP25 IIn * RAS ADCK cycles ADCK cycles LSB3 LSB3 LSB3 LSB3 LSB3 LSB3 mV — 3.266 — — 3.638 — — 1.396 — mV/°C V 1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. Includes quantization 3. 1 LSB = (VREFH - VREFL)/2N 4. Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes 5. VADIN = VSSA 6. VADIN = VDDA 7. IIn = leakage current (refer to DC characteristics) MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. Freescale Semiconductor, Inc. 23 Peripheral operating requirements and behaviors 6.3.2 Analog comparator (ACMP) electricals Table 13. Comparator electrical specifications C Characteristic Symbol Min Typical Max Unit D Supply voltage VDDA 2.7 — 5.5 V T Supply current (Operation mode) IDDA — 10 20 µA D Analog input voltage VAIN VSS - 0.3 — VDDA V P Analog input offset voltage VAIO — — 40 mV C Analog comparator hysteresis (HYST=0) VH — 15 20 mV C Analog comparator hysteresis (HYST=1) VH — 20 30 mV T Supply current (Off mode) IDDAOFF — 60 — nA C Propagation Delay tD — 0.4 1 µs 6.4 Communication interfaces 6.4.1 SPI switching specifications The serial peripheral interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. Refer to the SPI chapter of the chip's reference manual for information about the modified transfer formats used for communicating with slower peripheral devices. All timing is shown with respect to 20% VDD and 70% VDD, unless noted, and 100 pF load on all SPI pins. All timing assumes slew rate control is disabled and high drive strength is enabled for SPI output pins. Table 14. SPI master mode timing Nu m. Symbol Description Min. Max. Unit Comment 1 fop fBus/2048 fBus/2 Hz fBus is the bus clock 2 tSPSCK 2 x tBus 2048 x tBus ns tBus = 1/fBus 3 tLead Enable lead time 1/2 — tSPSCK — 4 tLag Enable lag time 1/2 — tSPSCK — 5 tWSPSCK 6 tSU Data setup time (inputs) tBus - 30 1024 x tBus ns — 15 — ns — 7 tHI Data hold time (inputs) 0 — ns — 8 tv Data valid (after SPSCK edge) — 25 ns — 9 tHO Data hold time (outputs) 0 — ns — Frequency of operation SPSCK period Clock (SPSCK) high or low time Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. 24 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 14. SPI master mode timing (continued) Nu m. Symbol 10 tRI Rise time input tFI Fall time input tRO Rise time output tFO Fall time output 11 Description Min. Max. Unit Comment — tBus - 25 ns — — 25 ns — SS1 (OUTPUT) 3 2 SPSCK (CPOL = 0) (OUTPUT) 10 11 10 11 4 5 5 SPSCK (CPOL = 1) (OUTPUT) 6 7 MISO (INPUT) MSB IN2 BIT 6 . . . 1 LSB IN 8 MOSI (OUTPUT) MSB OUT2 9 BIT 6 . . . 1 LSB OUT 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 13. SPI master mode timing (CPHA=0) SS1 (OUTPUT) 2 3 SPSCK (CPOL = 0) (OUTPUT) 5 SPSCK (CPOL = 1) (OUTPUT) 5 6 MISO (INPUT) 10 11 10 11 4 7 MSB IN2 BIT 6 . . . 1 LSB IN 9 8 MOSI 2 (OUTPUT)PORT DATA MASTER MSB OUT BIT 6 . . . 1 MASTER LSB OUT PORT DATA 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 14. SPI master mode timing (CPHA=1) MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. Freescale Semiconductor, Inc. 25 Peripheral operating requirements and behaviors Table 15. SPI slave mode timing Nu m. Symbol Description 1 fop 2 tSPSCK 3 tLead Enable lead time 4 tLag Enable lag time 5 tWSPSCK 6 tSU 7 Min. Max. Unit Comment 0 fBus/4 Hz fBus is the bus clock as defined in . 4 x tBus — ns tBus = 1/fBus 1 — tBus — Frequency of operation SPSCK period 1 — tBus — tBus - 30 — ns — Data setup time (inputs) 15 — ns — tHI Data hold time (inputs) 25 — ns — 8 ta Slave access time — tBus ns Time to data active from high-impedance state 9 tdis Slave MISO disable time — tBus ns Hold time to highimpedance state 10 tv Data valid (after SPSCK edge) — 25 ns — 11 tHO Data hold time (outputs) 0 — ns — 12 tRI Rise time input — tBus - 25 ns — tFI Fall time input tRO Rise time output — 25 ns — tFO Fall time output 13 Clock (SPSCK) high or low time SS (INPUT) 2 SPSCK (CPOL = 0) (INPUT) 5 3 SPSCK (CPOL = 1) (INPUT) 13 4 12 13 9 8 MISO (OUTPUT) 5 12 10 see note 6 MOSI (INPUT) SLAVE MSB BIT 6 . . . 1 11 11 SLAVE LSB OUT SEE NOTE 7 MSB IN BIT 6 . . . 1 LSB IN NOTE: Not defined! Figure 15. SPI slave mode timing (CPHA = 0) MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. 26 Freescale Semiconductor, Inc. Dimensions SS (INPUT) 4 2 3 SPSCK (CPOL = 0) (INPUT) 5 SPSCK (CPOL = 1) (INPUT) 5 see note SLAVE 8 MSB OUT 6 MOSI (INPUT) 13 12 13 9 11 10 MISO (OUTPUT) 12 BIT 6 . . . 1 SLAVE LSB OUT 7 MSB IN LSB IN BIT 6 . . . 1 NOTE: Not defined! Figure 16. SPI slave mode timing (CPHA=1) 6.5 Human-machine interfaces (HMI) 6.5.1 TSI electrical specifications Table 16. TSI electrical specifications Symbol Description Min. Type Max Unit TSI_RUNF Fixed power consumption in run mode — 100 — µA TSI_RUNV Variable power consumption in run mode (depends on oscillator's current selection) 1.0 — 128 µA TSI_EN Power consumption in enable mode — 100 — µA TSI_DIS Power consumption in disable mode — 1.2 — µA TSI_TEN TSI analog enable time — 66 — µs TSI_CREF TSI reference capacitor — 1.0 — pF TSI_DVOLT Voltage variation of VP & VM around nominal values -10 — 10 % 7 Dimensions 7.1 Obtaining package dimensions Package dimensions are provided in package drawings. MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. Freescale Semiconductor, Inc. 27 Pinout To find a package drawing, go to www.freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 16-pin TSSOP 98ASH70247A 20-pin SOIC 98ASB42343B 20-pin TSSOP 98ASH70169A 32-pin LQFP 98ASH70029A 44-pin LQFP 98ASS23225W 8 Pinout 8.1 Signal multiplexing and pin assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. Table 17. Pin availability by package pin-count Pin Number Lowest Priority <-- --> Highest 44-LQFP 32-LQFP 20-TSSOP 16-TSSOP Port Pin Alt 1 Alt 2 Alt 3 Alt 4 1 1 — — PTD11 — FTM2CH3 — — 2 2 — — PTD01 — FTM2CH2 — — 3 — — — PTE4 — TCLK2 — — 4 — — — PTE3 — BUSOUT — — 5 3 3 3 — — — — VDD 6 4 — — — — — VDDA VREFH 7 5 — — — — — VSSA VREFL 8 6 4 4 — — — — VSS 9 7 5 5 PTB7 — — SCL EXTAL 10 8 6 6 PTB6 — — SDA XTAL 11 — — — — — — — Vss 7 PTB51 — FTM2CH5 SS0 — — FTM2CH4 MISO0 — 12 9 7 13 10 8 8 PTB41 14 11 9 — PTC3 — FTM2CH3 ADP11 TSI9 15 12 10 — PTC2 — FTM2CH2 ADP10 TSI8 16 — — — PTD7 — — — — 17 — — — PTD6 — — — — Table continues on the next page... MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. 28 Freescale Semiconductor, Inc. Pinout Table 17. Pin availability by package pin-count (continued) Pin Number Lowest Priority <-- --> Highest 44-LQFP 32-LQFP 20-TSSOP 16-TSSOP Port Pin Alt 1 Alt 2 Alt 3 Alt 4 18 — — — PTD5 — — — — 19 13 11 — PTC1 — FTM2CH1 ADP9 TSI7 20 14 12 — PTC0 — FTM2CH0 ADP8 TSI6 21 15 13 9 PTB3 KBI0P7 MOSI0 ADP7 TSI5 22 16 14 10 PTB2 KBI0P6 SPSCK0 ADP6 TSI4 23 17 15 11 PTB1 KBI0P5 TXD0 ADP5 TSI3 24 18 16 12 PTB0 KBI0P4 RXD0 ADP4 TSI2 25 19 — — PTA7 — FTM2FAULT2 ADP3 TSI1 26 20 — — PTA6 — FTM2FAULT1 ADP2 TSI0 27 — — — — — — — Vss 28 — — — — — — — VDD 29 — — — PTD4 — — — — 30 21 — — PTD3 — — — TSI15 31 22 — — PTD2 — — — TSI14 13 PTA32 KBI0P3 TXD0 SCL — 32 23 17 33 24 18 14 PTA22 KBI0P2 RXD0 SDA — 34 25 19 15 PTA1 KBI0P1 FTM0CH1 ACMP1 ADP1 35 26 20 16 PTA0 KBI0P0 FTM0CH0 ACMP0 ADP0 36 27 — — PTC7 — TxD1 — TSI13 37 28 — — PTC6 — RxD1 — TSI12 38 — — — PTE2 — MISO0 — — 39 — — — PTE1 — MOSI0 — — 40 — — — PTE0 — SPSCK0 — — 41 29 — — PTC5 — FTM0CH1 — TSI11 42 30 — — PTC4 — FTM0CH0 — TSI10 43 31 1 1 PTA5 IRQ TCLK0 — RESET 44 32 2 2 PTA4 — ACMPO BKGD MS 1. This is a high current drive pin when operated as output. 2. This is a true open-drain pin when operated as output. Note When an alternative function is first enabled, it is possible to get a spurious edge to the module. User software must clear any associated flags before interrupts are enabled. The table above illustrates the priority if multiple modules are enabled. The highest priority module will have control over the pin. Selecting a higher priority pin function with a lower priority function MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. Freescale Semiconductor, Inc. 29 Pinout already enabled can cause spurious edges to the lower priority module. Disable all modules that share a pin before enabling another module. PTC7/TxD1/TSI13 PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1 36 34 35 PTE2/MISO0 PTC6/RxD1/TSI12 38 37 PTE0/SPSCK0 PTE1/MOSI0 40 39 42 41 PTA4/ACMPO/BKGD/MS PTA5/IRQ/TCLK0/RESET PTC4/FTM0CH0/TSI10 PTC5/FTM0CH1/TSI11 44 43 8.2 Device pin assignment 33 PTA2/KBI0P2/RxD0/SDA 2 32 PTA3/KBI0P3/TxD0/SCL2 PTD1/FTM2CH31 1 PTD0/FTM2CH21 2 PTE4/TCLK2 PTE3/BUSOUT VDD 3 31 PTD2/TSI14 4 30 PTD3/TSI15 5 29 PTD4 VDDA /VREFH 6 28 VDD 20 21 22 PTC0/FTM2CH0/ADP8/TSI6 PTB3/KBI0P7/MOSI0/ADP7/TSI5 PTB2/KBI0P6/SPSCK0/ADP6/TSI4 18 19 PTD5 PTC1/FTM2CH1/ADP9/TSI7 PTB1/KBI0P5/TxD0/ADP5/TSI3 16 23 17 11 PTD6 PTB0/KBI0P4/RxD0/ADP4/TSI2 VSS PTD7 PTA7/FTM2FAULT2/ADP3/TSI1 24 14 25 15 9 10 PTC3/FTM2CH3/ADP11/TSI9 PTB7/SCL/EXTAL PTB6/SDA/XTAL PTC2/FTM2CH2/ADP10/TSI8 VSS PTA6/FTM2FAULT1/ADP2/TSI0 12 26 13 27 8 PTB5/FTM2CH5/SS01 7 VSS PTB4/FTM2CH4/MISO01 VSSA /VREFL Pins in bold are not available on less pin-count packages. 1. High source/sink current pins 2. True open drain pins Figure 17. MC9S08PT16 44-pin LQFP package MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. 30 Freescale Semiconductor, Inc. PTC5/FTM0CH1/TSI11 PTC6/RxD1/TSI12 PTC7/TxD1/TSI13 PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1 29 28 27 26 25 PTA5/IRQ/TCLK0/RESET PTC4/FTM0CH0/TSI10 30 PTA4/ACMPO/BKGD/MS 32 31 Pinout PTD1/FTM2CH31 1 PTD0/FTM2CH2 1 2 VDD 3 22 PTD2/TSI14 VDDA/VREFH 4 21 PTD3/TSI15 24 PTA2/KBI0P2/RxD0/SDA 2 23 PTA3/KBI0P3/TxD0/SCL2 14 15 16 PTC0/FTM2CH0/ADP8/TSI6 PTB3/KBI0P7/MOSI0/ADP7/TSI5 PTB2/KBI0P6/SPSCK0/ADP6/TSI4 PTB1/KBI0P5/TxD0/ADP5/TSI3 12 17 13 8 PTC1/FTM2CH1/ADP9/TSI7 PTB0/KBI0P4/RxD0/ADP4/TSI2 PTB6/SDA/XTAL PTC2/FTM2CH2/ADP10/TSI8 18 11 7 PTC3/FTM2CH3/ADP11/TSI9 PTA7/FTM2FAULT2/ADP3/TSI1 PTB7/SCL/EXTAL 9 PTA6/FTM2FAULT1/ADP2/TSI0 19 10 20 6 PTB5/FTM2CH5/SS01 5 VSS PTB4/FTM2CH4/MISO01 VSSA/VREFL Pins in bold are not available on less pin-count packages. 1. High source/sink current pins 2. True open drain pins Figure 18. MC9S08PT16 32-pin LQFP package PTA5/IRQ/TCLK0/RESET 1 20 PTA4/ACMPO/BKGD/MS VDD VSS 2 19 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1 3 18 PTA2/KBI0P2/RxD0/SDA 2 4 5 17 16 PTA3/KBI0P3/TxD0/SCL 2 PTB7/SCL/EXTAL PTB6/SDA/XTAL 6 15 14 13 PTB1/KBI0P5/TxD0/ADP5/TSI3 PTB3/KBI0P7/MOSI0/ADP7/TSI5 12 PTC0/FTM2CH0/ADP8/TSI6 11 PTC1/FTM2CH1/ADP9/TSI7 PTB5/FTM2CH5/SS01 PTB4/FTM2CH4/MISO0 1 7 PTC3/FTM2CH3/ADP11/TSI9 8 9 PTC2/FTM2CH2/ADP10/TSI8 10 PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTB0/KBI0P4/RxD0/ADP4/TSI2 PTB2/KBI0P6/SPSCK0/ADP6/TSI4 Pins in bold are not available on less pin-count packages. 1. High source/sink current pins 2. True open drain pins Figure 19. MC9S08PT16 20-pin SOIC and TSSOP package MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. Freescale Semiconductor, Inc. 31 Revision history PTA5/IRQ/TCLK0/RESET 1 16 PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTA4/ACMPO/BKGD/MS VDD VSS 2 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1 4 15 14 13 PTA3/KBI0P3/TxD0/SCL2 PTB7/SCL/EXTAL 5 12 PTB0/KBI0P4/RxD0/ADP4/TSI2 PTB6/SDA/XTAL 6 PTB1/KBI0P5/TxD0/ADP5/TSI3 7 11 10 8 9 PTB5/FTM2CH5/SS01 PTB4/FTM2CH4/MISO01 3 PTA2/KBI0P2/RxD0/SDA 2 PTB2/KBI0P6/SPSCK0/ADP6/TSI4 PTB3/KBI0P7/MOSI0/ADP7/TSI5 Pins in bold are not available on less pin-count packages. 1. High source/sink current pins 2. True open drain pins Figure 20. MC9S08PT16 16-pin TSSOP package 9 Revision history The following table provides a revision history for this document. Table 18. Revision history Rev. No. Date 1 7/2012 Substantial Changes Initial public release MC9S08PT16 Series Data Sheet, Rev. 1, 7/4/2012. 32 Freescale Semiconductor, Inc. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 [email protected] Document Number: MC9S08PT16 Rev. 1, 7/4/2012 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductors products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claims alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-complaint and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011–2012 Freescale Semiconductor, Inc.