MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA 2.5V and 3.3V LVCMOS Clock Freescale Semiconductor, Inc... Fanout Buffer The MPC9456 is a 2.5V and 3.3V compatible 1:10 clock distribution buffer designed for low-voltage mid-range to high-performance telecom, networking and computing applications. Both 3.3V, 2.5V and dual supply voltages are supported for mixed-voltage applications. The MPC9456 offers 10 low-skew outputs and a differential LVPECL clock input. The outputs are configurable and support 1:1 and 1:2 output to input frequency ratios. The MPC9456 is specified for the extended temperature range of –40 to 85°C. Features • Configurable 10 outputs LVCMOS clock distribution buffer Order Number: MPC9456/D Rev 1, 03/2002 MPC9456 LOW VOLTAGE SINGLE OR DUAL SUPPLY 2.5V AND 3.3V LVCMOS CLOCK DISTRIBUTION BUFFER • Compatible to single, dual and mixed 3.3V/2.5V voltage supply • Wide range output clock frequency up to 250 MHz • Designed for mid-range to high-performance telecom, networking and computer applications • Supports high-performance differential clocking applications • • • • • Max. output skew of 200 ps (150 ps within one bank) Selectable output configurations per output bank Tristable outputs FA SUFFIX LQFP PACKAGE CASE 873A–02 32 ld LQFP package Ambient operating temperature range of –40 to 85°C Functional Description The MPC9456 is a full static design supporting clock frequencies up to 250 MHz. The signals are generated and retimed on-chip to ensure minimal skew between the three output banks. Each of the three output banks can be individually supplied by 2.5V or 3.3V supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the three output banks. The MPC9456 can be reset and the outputs are disabled by deasserting the MR/OE pin (logic high state). Asserting MR/OE will enable the outputs. All control inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. The clock input is low voltage PECL compatible for differential clock distribution support. Please consult the MPC9446 specification for a full CMOS compatible device. For series terminated transmission lines, each of the MPC9456 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a 7x7 mm2 32-lead LQFP package. Motorola, Inc. 2002 For More Information On This Product, 1 Go to: www.freescale.com Freescale Semiconductor, Inc. MPC9456 Bank A CLK 0 CLK ÷ 2 1 PCLK QA0 25k QA1 PCLK QA2 25k VCC/2 Bank B QB0 0 QB1 1 QB2 QC0 Bank C Freescale Semiconductor, Inc... FSELA 25k 0 QC1 25k 1 QC2 FSELB FSELC QC3 25k MR/OE 25k VCCC VCCB QB2 GND QB1 VCCB QB0 GND Figure 1. MPC9456 Logic Diagram VCCB is internally connected to VCC 24 23 22 21 20 19 18 17 VCCA 25 16 QC3 QA2 26 15 GND GND 27 14 QC2 QA1 28 13 VCCC MPC9456 VCCA 29 12 QC1 QA0 30 11 GND GND 31 10 QC0 MR/OE 32 2 3 4 5 6 7 8 NC VCC PECL_CLK PECL_CLK FSELA FSELB FSELC GND 9 1 VCCC Figure 2. Pinout: 32–Lead Package Pinout (Top View) MOTOROLA For More Information On This Product, 2 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9456 Table 1: Pin Configuration Freescale Semiconductor, Inc... Pin I/O Type Function PECL_CLK, PECL_CLK Input LVPECL Differential clock reference Low voltage positive ECL input FSELA, FSELB, FSELC Input LVCMOS Output bank divide select input MR/OE Input LVCMOS Internal reset and output tristate control GND Supply Negative voltage supply output bank (GND) VCCA, VCCB*, VCCC Supply Positive voltage supply for output banks VCC Supply Positive voltage supply core (VCC) QA0 - QA2 Output LVCMOS Bank A outputs QB0 - QB2 Output LVCMOS Bank B outputs QC0 - QC3 Output LVCMOS Bank C outputs * VCCB is internally connected to VCC. Table 2: Supported Single and Dual Supply Configurations VCCa VCCAb VCCBc VCCCd GND 3.3V 3.3V 3.3V 3.3V 3.3V 0V Mixed voltage supply 3.3V 3.3V or 2.5V 3.3V 3.3V or 2.5V 0V 2.5V 2.5V 2.5V 2.5V 2.5V 0V Supply voltage configuration a. b. c. d. VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels. VCCB is internally connected to VCC. VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels Table 3: Function Table (Controls) Control Default 0 1 FSELA 0 fQA0:2 = fREF fQA0:2 = fREF ÷ 2 FSELB 0 fQB0:2 = fREF fQB0:2 = fREF ÷ 2 FSELC 0 fQC0:3 = fREF fQC0:3 = fREF ÷ 2 MR/OE 0 Outputs enabled Internal reset Outputs disabled (tristate) Table 4: Absolute Maximum Ratingsa Symbol Characteristics Min Max Unit VCC Supply Voltage -0.3 4.6 V VIN DC Input Voltage -0.3 VCC+0.3 V DC Output Voltage -0.3 VCC+0.3 V DC Input Current ±20 mA DC Output Current ±50 mA VOUT IIN IOUT Condition TS Storage temperature -40 125 °C a. Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 5: General Specifications Symbol Characteristics Min Typ VCC ÷ 2 Max Unit VTT Output Termination Voltage MM ESD Protection (Machine Model) 200 HBM ESD Protection (Human Body Model) 2000 V Latch–Up Immunity 200 mA LU V V CPD Power Dissipation Capacitance 10 pF CIN Input Capacitance 4.0 pF TIMING SOLUTIONS Condition For More Information On This Product, 3 Go to: www.freescale.com Per output MOTOROLA Freescale Semiconductor, Inc. MPC9456 Table 6: DC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3V Symbol Min Input high voltage VPP Peak-to-peak input voltage PCLK 250 Common Mode Range Input currentb PCLK 1.1 VCMRa IIN VOH VOL Freescale Semiconductor, Inc... Characteristics VIH VIL ± 5%, TA = –40 to +85°C) Typ 2.0 Input low voltage -0.3 Output High Voltage Max Unit VCC + 0.3 0.8 V LVCMOS VCC-0.6 200 2.4 V LVCMOS mV LVPECL V LVPECL µA VIN=GND or VIN=VCC IOH=-24 mAc IOL= 24mAb IOL= 12mA V Output Low Voltage 0.55 0.30 Condition V V W ZOUT Output impedance 14 - 17 ICCQd Maximum Quiescent Supply Current 2.0 mA All VCC Pins a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. b. Input pull-up / pull-down resistors influence input current. c. The MPC9456 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines. d. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 7: AC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3V Symbol fref Maximum Output Frequency VPP Peak-to-peak input voltage Common Mode Range tr, tf tPLH tPHL tPLZ, HZ tPZL, LZ e. Typ 0 0 Max 250b 250b 125 PCLK 500 1000 PCLK 1.3 VCC-0.8 0 ÷1 output ÷2 output Reference Input Pulse Width 1.4 Unit MHz MHz FSELx=0 FSELx=1 mV LVPECL V LVPECL 1.0d ns 4.45 4.2 ns ns Output Disable Time 10 ns Output Enable Time 10 ns 150 200 350 2.25 ps ps ps 200 ps 53 55 % % Propagation delay CCLK to any Q CCLK to any Q Output-to-output Skew Within one bank Any output bank, same output divider Any output, Any output divider tsk(PP) tSK(P) Device-to-device Skew Output pulse skewe Output Duty Cycle ÷1 output ÷2 output 2.2 2.2 47 45 Condition MHz ns PCLK Input Rise/Fall Time tsk(O) DCQ d. Min Input Frequency fMAX VCMRc tP, REF a. b. c. Characteristics ± 5%, TA = –40 to +85°C)a 2.8 2.8 50 50 0.8 to 2.0V ns DCREF = 50% DCREF = 25%-75% tr, tf Output Rise/Fall Time 0.1 1.0 ns 0.55 to 2.4V AC characteristics apply for parallel output termination of 50Ω to VTT. The MPC9456 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. MOTOROLA For More Information On This Product, 4 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9456 Table 8: DC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5V Symbol Characteristics Min VIH VIL Input high voltage VPP Peak-to-peak input voltage PCLK 250 Common Mode Range PCLK 1.1 VCMRa VOH VOL ZOUT IIN ± 5%, TA = –40 to +85°C) Typ 1.7 Input low voltage -0.3 Output High Voltage Max Unit VCC + 0.3 0.7 V LVCMOS V LVCMOS mV LVPECL V LVPECL V IOH=-15 mAb IOL= 15 mA VCC-0.7 1.8 Output Low Voltage 0.6 V W 17 - 20b Output impedance Input currentc Condition ±200 µA VIN=GND or VIN=VCC All VCC Pins ICCQd Maximum Quiescent Supply Current 2.0 mA VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. b. The MPC9456 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines per output. c. Input pull-up / pull-down resistors influence input current. d. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Freescale Semiconductor, Inc... a. Table 9: AC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5V Symbol fref fMAX Characteristics Min Input Frequency Maximum Output Frequency ± 5%, TA = –40 to +85°C)a Typ Max 250b 250b 125 0 ÷1 output ÷2 output 0 0 Unit Condition MHz MHz MHz FSELx=0 FSELx=1 VPP VCMRc tP, REF Peak-to-peak input voltage PCLK 500 1000 mV LVPECL Common Mode Range PCLK 1.1 VCC-0.7 V LVPECL tr, tf PCLK Input Rise/Fall Time tPLH tPHL Propagation delay Reference Input Pulse Width 1.4 ns 1.0d ns 5.6 5.5 ns ns Output Disable Time 10 ns Output Enable Time 10 ns tsk(O) Output-to-output Skew Within one bank Any output bank, same output divider Any output, Any output divider ps ps ps tsk(PP) tSK(P) Device-to-device Skew Output pulse skewe 150 200 350 3.0 200 ps tPLZ, HZ tPZL, LZ PCLK to any Q PCLK to any Q 2.6 2.6 0.7 to 1.7V ns 55 % 45 50 DCREF = 50% Output Duty Cycle ÷1 or ÷2 output tr, tf Output Rise/Fall Time 0.1 1.0 ns 0.6 to 1.8V AC characteristics apply for parallel output termination of 50Ω to VTT. The MPC9456 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. DCQ a. b. c. d. e. TIMING SOLUTIONS For More Information On This Product, 5 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC9456 Table 10: AC Characteristics (VCC = 3.3V TA = –40 to +85°C)a b VCCA = VCCB = VCCC = 2.5V Symbol Characteristics tsk(O) Output-to-output Skew Within one bank Any output bank, same output divider Any output, Any output divider tsk(PP) tPLH,HL tSK(P) DCQ Min ± 5% or 3.3V ± 5%, Typ Device-to-device Skew Propagation delay PCLK to any Q ÷1 or ÷2 output Unit 150 250 350 2.5 ps ps ps 250 ps 55 % Condition ns See 3.3V table Output pulse skewc Output Duty Cycle Max 45 50 DCREF = 50% AC characteristics apply for parallel output termination of 50Ω to VTT. For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. Freescale Semiconductor, Inc... a. b. c. ± 5%, MOTOROLA For More Information On This Product, 6 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9456 APPLICATIONS INFORMATION The MPC9456 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20Ω the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50Ω resistance to VCC÷2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9456 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 3. “Single versus Dual Transmission Lines” illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9456 clock driver is effectively doubled due to its capability to drive multiple lines. MPC9456 OUTPUT BUFFER IN 14Ω MPC9456 OUTPUT BUFFER IN = VS ( Z0 ÷ (RS+R0 +Z0)) = 50Ω || 50Ω = 36Ω || 36Ω = 14Ω = 3.0 ( 25 ÷ (18+14+25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). VL Z0 RS R0 VL 3.0 2.5 OutA tD = 3.8956 OutB tD = 3.9386 2.0 In 1.5 1.0 0.5 RS = 36Ω ZO = 50Ω 0 OutA 2 4 6 8 TIME (nS) 10 12 14 Figure 4. Single versus Dual Waveforms RS = 36Ω ZO = 50Ω OutB0 14Ω RS = 36Ω ZO = 50Ω OutB1 Figure 3. Single versus Dual Transmission Lines The waveform plots in Figure 4. “Single versus Dual Line Termination Waveforms” show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9456 output buffer is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9456. The output waveform in Figure 4. “Single versus Dual Line Termination Waveforms” shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36Ω series resistor plus the output TIMING SOLUTIONS impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VOLTAGE (V) Freescale Semiconductor, Inc... Driving Transmission Lines Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 5. “Optimized Dual Line Termination” should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9456 OUTPUT BUFFER RS = 22Ω ZO = 50Ω RS = 22Ω ZO = 50Ω 14Ω 14Ω + 22Ω k 22Ω = 50Ω k 50Ω 25Ω = 25Ω Figure 5. Optimized Dual Line Termination For More Information On This Product, 7 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC9456 MPC9456 DUT ZO = 50Ω Differential Pulse Generator Z = 50 ZO = 50Ω W RT = 50Ω RT = 50Ω VCC – 2V VTT Figure 6. PCLK MPC9456 AC test reference for Vcc = 3.3V and Vcc = 2.5V Freescale Semiconductor, Inc... PCLK VCC=3.3V 2.4 VCC=2.5V 1.8V PCLK 0.55 0.6V QX VCMR VPP VCC VCC 2 B GND tF tR t(LH) Figure 7. Output Transition Time Test Reference t(HL) Figure 8. Propagation delay (tPD) test reference VCC VCC 2 VCC VCC 2 GND GND B B VOH VCC 2 B tP T0 GND DC = tP /T0 x 100% tSK(LH) The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage The pin–to–pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 9. Output Duty Cycle (DC) tF tSK(HL) Figure 10. Output–to–output Skew tSK(O) VCC=3.3V 2.4 VCC=2.5V 1.8V 0.55 0.6V tR Figure 11. Output Transition Time test reference MOTOROLA For More Information On This Product, 8 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9456 OUTLINE DIMENSIONS A –T–, –U–, –Z– FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A 4X A1 32 0.20 (0.008) AB T–U Z 25 1 –U– –T– B V AE B1 DETAIL Y 17 8 V1 AE DETAIL Y 9 4X –Z– 9 0.20 (0.008) AC T–U Z S1 S DETAIL AD G –AB– 0.10 (0.004) AC AC T–U Z –AC– BASE METAL ÏÏ ÏÏ ÏÏ ÏÏ F 8X M_ R J M N D 0.20 (0.008) SEATING PLANE SECTION AE–AE H W K X DETAIL AD TIMING SOLUTIONS Q_ 0.250 (0.010) C E GAUGE PLANE Freescale Semiconductor, Inc... P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED AT DATUM PLANE –AB–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –AC–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –AB–. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X For More Information On This Product, 9 Go to: www.freescale.com MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF MOTOROLA Freescale Semiconductor, Inc. MPC9456 Freescale Semiconductor, Inc... NOTES MOTOROLA For More Information On This Product, 10 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9456 Freescale Semiconductor, Inc... NOTES TIMING SOLUTIONS For More Information On This Product, 11 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MPC9456 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA and the logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. E Motorola, Inc. 2002. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334 Technical Information Center: 1–800–521–6274 HOME PAGE: http://www.motorola.com/semiconductors/ MOTOROLA ◊ More Information For On This Product, 12 Go to: www.freescale.com MPC9456/D TIMING SOLUTIONS