x-mGC, Electrical Transceiver for 10GBASE-CX4 x-mGC Part Number: FCU-010M002 Features Compliant with IEEE802.3ak (10GBASE-CX4) XENPAK MSA Rev 3.0 type Compatible module Industry standard electrical connector, microGiGaCNTM (I/O interface) XAUI Four channel electrical interface (Host side card edge) XAUI Standard 70 pin connector for host connection Front panel hot swap ability. XENPAK MSA Rev 3.0 compliant MDIO Link Alarm Status Interrupt (LASI) support Total Power consumption under 3.0 watt 20 meters over standard InfiniBand copper cable (24AWG) With media detect converter (o-mGC), up to 100 meters over standard multi mode fiber. No external clocks requirement – oscillator on board Description The x-mGC is a 10Gigabit Ethernet CX4 Module that designed to ease XENPAK MSA 3.0 and it is an electrical module that incorporates the complete physical layer functionality from XAUI compliant 4 lanes x 3.125 Gb/s four differential electrical interface to the microGiGaCN™ CX4 compliant electrical interface. The x-mGC is plugged into a XENPAK hosting system and connects to a 4X InfiniBand cable. The control interface (MDIO)is also integrated. The x-mGC module includes 10Gb/s Ethernet transmitter and receiver ports. The host may control the x-mGC registers using XAUI interface as defined in the XENPAK MSA. The MUX/DEMUX, XAUI interface and MDIO management functions are all integrated into the module, as is a precision oscillator that removes any need for an external reference clock. Fujitsu Component Limited Page 1 of 24 x-mGC, Electrical Transceiver for 10GBASE-CX4 XAUI Interface (70pin connector) Tx Rx XGXS MDIO, MDC, Other signal Re-timer XAUI IN Normalization CX4 Interface (microGiGaCN™ connector) XAUI IN 7 XAUI OUT Transceiver Management Reference Clock XAUI OUT Power (*1) InfiniBand Cable (< 20m) o-mGC + Optical fiber (< 100m (*1) ) x-mGC Block Diagram Media Detect Hot Swap Control Vcc Figure 1: Functional Brock Diagram of x-mGC module (*1) In case of InfiniBand cable is connected, the power does not supply to cable, and if o-mGC is connected, a ground contact is changed Vcc for power supply to o-mGC by Media detect function. Absolute Maximum Ratings Parameter Storage Temperature Storage Humidity Supply Voltage(3.3V) Adaptable Power Supply(1.5V) Voltage on LVCMOS pins Min -20 0 3.135 1.425 Recommended Operating Conditions Parameter Min Operating Temperature 0 Operating Humidity 0 Typ 3.3 1.5 1.2 Max 60 80 3.465 1.575 Units Notes ℃ % Wet bulb 38℃ V V V Max Units Notes ℃ % Wet bulb 38℃ Typ 50 80 General Electrical Specification Interface: XAUI side; 70 pin SMT connector (See XENPAK MSA Rev3.0, chapter 8.3 and 10.7) CX4 side; InfiniBand 4X connector ( microGiGaCN™ , Fujitsu Component LTD. Patented) Differential signal rate: Tx and Rx each 3.125 Gb/s x 4 pair Impedance: 100 ohms differential, AC-coupled I/O Fujitsu Component Limited Page 2 of 24 x-mGC, Electrical Transceiver for 10GBASE-CX4 Adaptable Cable and Link Length: InfiniBand 4X cable 20m over Environmental Specification Operating case temperature: 0 - 70 degree (In an uniform air flow of 0.5 m/s.) Power consumption: 3 Watt Max Mechanical Forces Maximum insertion force = 80 N (Includes connector, interposer and connector shield ground spring) Maximum extraction force = 50 N Minimum retention force (with screws engaged) = 130 N Fastener Torque: 0.1 Nm (3mm captive screw) Transceiver and Connector Durability Minimum mate/de-mate cycles for transceiver = 50 cycles Minimum mate/de-mate cycles for 70-pin connector = 200 cycles Minimum mate/de-mate cycles for CX4 connector = 250 cycles Fujitsu Component Limited Page 3 of 24 x-mGC, Electrical Transceiver for 10GBASE-CX4 Figure 2: Top Level Brock Diagram of x-mGC Driver Fujitsu Component Limited Page 4 of 24 x-mGC, Electrical Transceiver for 10GBASE-CX4 Technical specification Table 1: Transmitter characteristics Parameter Typical Signal data rate 3.125 Gb/s 320 ps 1200 800 150 See figure 3 mVp-p mVp-p mVp-p V 130 60 ps ps Unit interval (UI) nominal Differential peak to peak output voltage Maximum Minimum Differential peak to peak output voltage difference Differential output template Transition time (20-80%) Maximum Minimum Units Notes +/-100ppm Maximum 1.500 Normalized Amplitude (V) 1.000 0.500 0.000 -1.500 -1.000 -1.500 0.000 5.000 Time (UI) Figure 3: Normalized transmit template Fujitsu Component Limited Page 5 of 24 10.000 x-mGC, Electrical Transceiver for 10GBASE-CX4 Table 2: Receiver characteristics Parameter Typical Units Bit error ratio 10-12 Signal data rate 3.125 Gb/s Unit interval (UI) nominal 320 ps Differential input amplitude 1200 mVp-p See figure 4 dB Return loss differential (minimum) Notes +/-100ppm Maximum 100ohm Frequency (MHz) 100 1,000 0 Loss (dB) 5 10 15 Figure 4: Return loss differential (minimum) Fujitsu Component Limited Page 6 of 24 10,000 x-mGC, Electrical Transceiver for 10GBASE-CX4 x-mGC XAUI Pin out Toward Bezel Top of Transceiver PCB Bottom of Transceiver PCB (as viewed through top) Figure 6: x-mGC transceiver Electrical pad layout Fujitsu Component Limited Page 7 of 24 x-mGC, Electrical Transceiver for 10GBASE-CX4 Toward Bezel Lower Row Upper Row Figure 7: 10Gb host board pad layout Fujitsu Component Limited Page 8 of 24 x-mGC, Electrical Transceiver for 10GBASE-CX4 Pin function definitions Table 6: XAUI Pin function 1 Pin No Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Dir GND GND GND 5.0V 3.3V 3.3V APS (1.5V) APS (1.5V) LASI RESET VEND SPECIFIC-signal detect TX ON/OFF RESERVED MOD DETECT VEND SPECIFIC-spare VEND SPECIFIC-spare MDIO I Function Notes Electrical Ground Electrical Ground Electrical Ground Power Power Power Adaptive Power Supply Adaptive Power Supply LVCMOS 1.2V Open Drain 1 1 1 2 2 2 2 2 3 3 LVCMOS 1.2V Open Drain Passive O I/O Reserved Passive Passive Passive Management Data IO 4 3,4 LVCMOS 1.2V Open Drain 18 19 20 21 22 23 24 25 26 27 MDC PRTAD4 PRTAD3 PRTAD2 PRTAD1 PRTAD0 VEND SPECIFIC-not connected APS SET (1.5V) RESERVED APS SENSE 28 29 30 31 32 33 34 35 APS (1.5V) APS (1.5V) 3.3V 3.3V 5.0V GND GND GND I I I I I I Management Data Clock Port Address Bit 4 (Low = 0) Port Address Bit 3 (Low = 0) Port Address Bit 2 (Low = 0) Port Address Bit 1 (Low = 0) Port Address Bit 0 (Low = 0) Passive Passive Reserved Passive Connector to a 348 ohm resistor Adaptive Power Supply Adaptive Power Supply Power Power Power Electrical Ground Electrical Ground Electrical Ground Fujitsu Component Limited Page 9 of 24 3,4 3 3 3 3 3 4 2 2 2 2 2 1 1 1 x-mGC, Electrical Transceiver for 10GBASE-CX4 Table 7: XAUI Pin function 2 Pin No Name 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 GND GND RESERVED RESERVED GND RX LANE0+ RX LANE0- GND RX LANE1+ RX LANE1- GND RX LANE2+ RX LANE2- GND RX LANE3+ RX LANE3- GND GND GND TX LANE0+ TX LANE0- GND TX LANE1+ TX LANE1- GND TX LANE2+ TX LANE2- GND TX LANE3+ TX LANE3- GND RESERVED RESERVED GND GND Dir Function Notes Electrical Ground Electrical Ground Reserved Reserved Electrical Ground Module XAUI Output Lane 0+ Module XAUI Output Lane 0Electrical Ground Module XAUI Output Lane 1+ Module XAUI Output Lane 1Electrical Ground Module XAUI Output Lane 2+ Module XAUI Output Lane 2Electrical Ground Module XAUI Output Lane 3+ Module XAUI Output Lane 3Electrical Ground Electrical Ground Electrical Ground Module XAUI Input Lane 0+ Module XAUI Input Lane 0Electrical Ground Module XAUI Input Lane 1+ Module XAUI Input Lane 1Electrical Ground Module XAUI Input Lane 2+ Module XAUI Input Lane 2Electrical Ground Module XAUI Input Lane 3+ Module XAUI Input Lane 3Electrical Ground Reserved Reserved Electrical Ground Electrical Ground 1 1 Notes: 1) Ground connections are common for TX and RX. 2) All contacts of XAUI 70 pin connector are rated at 0.5A nominal. 3) 1.2V CMOS compatible. 4) MDIO and MDC timing must comply with IEEE802.3ae, Clause 45.3 5) XAUI output characteristics should comply with IEEE802.3ae Clause 47. Fujitsu Component Limited Page 10 of 24 1 5 5 1 5 5 1 5 5 1 5 5 1 1 1 5 5 1 5 5 1 5 5 1 5 5 1 1 1 x-mGC, Electrical Transceiver for 10GBASE-CX4 Package Design Mechanical design of x-mGC is shown as in following figure8. (Part Number: FCU-010M001) Datum E is transceiver top surface of slot. Datum H is leading edge of transceiver's PCB. (Part Number: FCU-010M002) Note4) This module is unable to withstand aqueous wash. Note3) Lot code, the product part number, serial number and Fujitsu Component Limited logo are indicated. Note2) Unless otherwise specified, tolerance shall be +/-0.5mm. Note1) This module is XENPAK‐CX4 transceiver. Figure 8: Mechanical Design Fujitsu Component Limited Page 11 of 24 x-mGC, Electrical Transceiver for 10GBASE-CX4 APPENDIX A : Programmable Logic Implementation 1 SCOPE This document scopes to x-mGC (XENPAK/X2-CX4), P/N :FCU-010M002-** (XENPAK), FCU-02*M101-** (X2) 2 INTRODUCTION This document describes management block implementation when x-mGC is used as 10G-CX4 PHY transceiver in XENPAK/X2-type application. Figure 1 describes the generic x-mGC design block diagram using retimer IC. CX4 connector Retimer XENPAK/X2 host Interface Power Supply Managment Block NVR interface • NVR High speed block includes a retimer IC 10G CX4-compliant device which ensures full-duplex XAUI-to-CX4 communication link • Power block that includes adaptive power supply support and Power filtering • The management block includes a register file that host can access. a non volatile memory (NVR) stores the default value of this register file. The host reads the register file for system capabilities, vendor information and link status information. The host may read or write from the register file, store its content in the NVR or load the default value from the NVR. Fujitsu Component Limited Page 12 of 24 x-mGC, Electrical Transceiver for 10GBASE-CX4 The host may indirectly access the link and host transceivers to change setting or to read status information. Following reset or power up the management block initializes the host and link transceiver by a pre defined initialization sequence. After the initialization the management reads a defined link of link status registers and stores them in the register file. In case of a link status event the management generates an interrupt signal name Link Alarm Status Interrupt (LASI). 3. Functional description The Management block in the retimer IC XENPAK/X2-RD is implemented in a FPGA. The The FPGA is updated over JTAG. The code is written to be ported to any other technology with minimal usage of technology specific macro. Any macro that can not be avoided is set to a specific verilog file. Features • Compliant with XENPAK MSA 3.0 / X2 MSA 2.0 • SMI (MDIO/MDC) – 802.3ae compliant • I2C I/O – to upload EPROM content (Vendor Specific Info) • Link Alarm Status Interrupt (LASI) support. • Non volatile memory that contains XENPAK/X2 registers default value. • In Circuit programming for FPGA over JTAG • XENPAK/X2 registers file mapped to Host MDIO space with configurable port address. • Retimer IC initialization • Retimer IC performance optimization routine (optional) • Signal detect indication Fujitsu Component Limited Page 13 of 24 x-mGC, Electrical Transceiver for 10GBASE-CX4 Internal architecture The following figure describes internal FPGA functionality: External serial EEPORM EECLK EEDO EEDI EECS PHY ini data (ROM) eeprom interface NVR rd data NVR write NVR read NVR wr data NVR add PHYin.data PHYini.address PHY reg.add PHYreg.wrdata PHY address PHYreg.wr PHYreg.rd HOST SMI SMI master FSM MDC MDC SMI master MDI MDO MDOOE MDO PHYreg.rddata XM_SMI MDOOE XEN Reg wr SMI Target MDI NVR acess FSM Xen reg rd NVR commands NVR command status Xenpack registers LASI status registers update LASI control LASI block LASI status SMI control by host PHYreg.rddata LASI PHY reg.add PHYreg.wrdata PHY address PHYreg.wr PHYreg.rd Figure 1 FPGA block diagram The management block is comprised of several sub blocks. A XENPAK/X2 register file is a volatile memory that is mapped to the host MDIO address space. The XENPAK/X2 register file is defined by the XENPAK/X2 MSA. It makes use of the lower eight bit of the MDIO data register. (Except from the host indirect SMI access registers) The host may read or write each register from the XENPAK/X2 register file. It can load or save the whole register file in a Non Volatile memory. The XENPAK/X2 register file is mapped into device number 2, at the port address set by the host. The Non Volatile RAM (NVR) FSM, manages NVR access. The following NVR commands are supported: Write all Read all In case of read/write all the state machine manages address incrementing and data transfer from register file to NVR. NVR master, performs a 2 wire NVR commands as described by the EEPROM vendor, this is a separate module support of other NVR devices is done by replacing this module. Link Alarm Status Interrupt (LASI) circuit. Generates an interrupt if one of the events in the following table occurs (set). The user may mask each one of the events. The LASI block implementation follows figure 21 in Fujitsu Component Limited Page 14 of 24 x-mGC, Electrical Transceiver for 10GBASE-CX4 the MSA. With the following exceptions: Global PMD signal PK is not applicable PCS block lock 1 is not applicable. WIS Local fault not applicable Laser Fault not applicable Initialization ROM data is a ROM that stores the initialization date. SMI master together read writes the transceivers register files. In initialize the transceivers after power up and reset and reads the status registers used by the LASI block. The following state machine describes the SMI master state machine. RESET/POWER UP Finished ini sequence (rid_last =1) fetch data from ini data ROM state 0 ROMFERCH Data from ROM is being trasfered via a trasparent latch that is open duriong this state set the address/data generate start pulse wait to ready read reg 1.10.0 state 2 SMI initalization write state 1 read reg 3.32.0 state 3 Pol reg 1.8.11 state 9 read reg 4.24.12 state 4 Pol reg 3.8.11 state 10 read reg 1.8.10 state 5 Pol reg 4.8.11 state 11 read reg 3.8.10 state 6 HOST control state 12 To Indirect MDIO access FSM read reg 4.8.10 state 7 Fujitsu Component Limited Page 15 of 24 set the address/data generate start pulse wait to ready data is transfered from RID to SMIM, generate start pulse, latch ROM data on exist from state increase ROM address Wait till SMI tranaction finsh wait for ready from SMI master x-mGC, Electrical Transceiver for 10GBASE-CX4 Interface Host interface Signal Name MDC MDI MDO Type HSTL HSTL LVCMOS OD HSTL Direction I I O Description Host Management clock Host Management Data Input Host Management Data Output I Xenpak/X2 registers Port Address HSTL I O VSPEC[3:1] LVCMOS OD LVCMOS Transmit on off (only apply for optical module) Link Alarm Status Interrupt output O Vendor specific [3:1] PHY interface Signal Name XM_MDC Type HSTL Direction O O I O Xenpak/X2 module management input Xenpak/X2 module active low reset output D1_LED_TX0 D2_LED_TX0 RMTCTRL LVCMOS OD HSTL LVCMOS OD HSTL HSTL HSTL Description Xenpak/X2 module management clock output, toggling at XM_CLK /8 Xenpak/X2 module management data output I I O Signal detect from port1 Signal detect from port2 Remote control EEPROM interface Signal Name SDA SCL WP Type LVCMOS LVCMOS LVCMOS Direction IO O O Description EEPROM data EEPROM clock EEPROM Write protect Global Signal Name XM_CLK Type LVCOMS Direction I Description Clock input HRST_N LVCMOS I Hardware Active Low reset Input XENP_PRTAD [4:0] TX_ON_OFF LASI_OUT XM_MDO XM_MDI XM_RST_N Fujitsu Component Limited Page 16 of 24 20Mhz x-mGC, Electrical Transceiver for 10GBASE-CX4 Programming interface Port and device mapping The XENPAK/X2 module is mapped to the host MDIO address space. The host accesses the module using SMI transactions. SMI frame description appeared in Table 45-64 in the IEEE 802.3ea standard. • The Host sets the XENPAK/X2 module port address. The XENPAK/X2 register file is mapped to device 2 at that port address. • The XENPAK/X2 module as an internal SMI bus that enable the management block to access the retimer registers this bus is S_SMI. In this bus the line transceiver is at port address 1 and the host transceiver is at port address 2. The registers in the retimer are mapped to devices 4. • The host has indirect access to the retimer via registers mapped to the XENPAK/X2 vendor specific space. The XENPAK/X2 module has an internal SMI secondary bus. On that bus, port one is mapped to SMI port address “2” while port two is mapped to SMI port address “3”. Register Map Register Address 32768 32775 32776 32777 32778 32779 32780 32781 32782 32783 32784 32785 32786 32787 32788 32789 32790 32791 32792 32793 32794 32795 32796 32797 32798 32799 32800 Register Name Default value NVR control/Status Version NVR_size 0 NVR_size 1 Mem_Used Mem_Used Basic Addr Cust Adde Vend Addr Ext Vend Addr 0 Ext Vend Addr 1 reserved Tcvr Type Connector Encoding Bit rate H Bit rate L Protocol Std comp Code 0 Std comp Code 1 Std comp Code 2 Std comp Code 3 Std comp Code 4 Std comp Code 5 Std comp Code 6 Std comp Code 7 Std comp Code 8 Refer to page 23 1E 1 0 1 0 B 77 A7 0 0 0 1: XENPAK, 2: X2 0 1 27 10 1 0 0 0 0 0 0 0 0 0 Fujitsu Component Limited Page 17 of 24 x-mGC, Electrical Transceiver for 10GBASE-CX4 Register Address 32801 32802 32803 32804 32805 32806 32807 32808 32809 32810 32811 32812 32813 32814 32815 32816 32817 32818 32819 32820 32821 32822 32823 32824 32825 32826 32827 32828 32829 32830 32831 32832 32833 32834 32835 32836 32837 32838 32839 32840 32841 32842 32843 32844 32845 32846 32847 32848 32849 32850 32851 Register Name Default value Std comp Code 9 Range 0 Range 1 Fiber type 0 Fiber type 1 Wave Length ch. 00 Wave Length ch. 01 Wave Length ch. 02 Wave Length ch. 10 Wave Length ch. 11 Wave Length ch. 12 Wave Length ch. 20 Wave Length ch. 21 Wave Length ch. 22 Wave Length ch. 30 Wave Length ch. 31 Wave Length ch. 32 Package OUI 0 Package OUI 1 Package OUI 2 Package OUI 3 Vendor OUI 0 Vendor OUI 1 Vendor OUI 2 Vendor OUI 3 Vendor Name 0 Vendor Name 1 Vendor Name 2 Vendor Name 3 Vendor Name 4 Vendor Name 5 Vendor Name 6 Vendor Name 7 Vendor Name 8 Vendor Name 9 Vendor Name 10 Vendor Name 11 Vendor Name 12 Vendor Name 13 Vendor Name 14 Vendor Name 15 Vendor P/N 0 Vendor P/N 1 Vendor P/N 2 Vendor P/N 3 Vendor P/N 4 Vendor P/N 5 Vendor P/N 6 Vendor P/N 7 Vendor P/N 8 Vendor P/N 9 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41:XENPAK, C0:X2 F4:XENPAK, 98:X2 0 0 9 2 2 46 75 6A 69 74 73 75 43 6F 6D 70 6F 6E 65 6E 74 46 43 55 2D 30 31:XENPAK, 32:X2 30:XENPAK, 32:X2 4D 30:XENPAK, 31:X2 30 Fujitsu Component Limited Page 18 of 24 x-mGC, Electrical Transceiver for 10GBASE-CX4 Register Address 32852 32853 32854 32855 32856 32857 32858 32859 32860 32861 32862 32863 32864 32865 32866 32867 32868 32869 32870 32871 32872 32873 32874 32875 32876 32877 32878 32879 32880 32881 32882 32883 32884 32885 32886 32887 32888 32889 32890 32891 32892 32893 32894 32895 32896 32897 32898 32899 32900 32901 32902 Register Name Default value Vendor P/N 10 Vendor P/N 11 Vendor P/N 12 Vendor P/N 13 Vendor P/N 14 Vendor P/N 15 Vendor Rev 0 Vendor Rev 1 Vendor SN 0 Vendor SN 1 Vendor SN 2 Vendor SN 3 Vendor SN 4 Vendor SN 5 Vendor SN 6 Vendor SN 7 Vendor SN 8 Vendor SN 9 Vendor SN 10 Vendor SN 11 Vendor SN 12 Vendor SN 13 Vendor SN 14 Vendor SN 15 Data code Year 0 Data code Year 1 Data code Year 2 Data code Year 3 Date Code Month 0 Date Code Month 1 Date Code Day 0 Date Code Day 1 Date Code Lot 0 Date Code Lot 1 Current ref 5v Current ref 3.3v Current ref APS Stress APS voltage DOM cap Optional Cap reserved Basic Check sum Customer Area 0 Customer Area 1 Customer Area 2 Customer Area 3 Customer Area 4 Customer Area 5 Customer Area 6 Customer Area 7 Customer Area 8 32:XENPAK, 31:X2 20 20 20 20 20 Vender information Vender information 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Vender information Vender information Vender information Vender information Vender information Vender information Vender information Vender information Vender information Vender information 0 4 4 10 0 0 0 0 0 0 0 0 0 0 0 0 0 Fujitsu Component Limited Page 19 of 24 x-mGC, Electrical Transceiver for 10GBASE-CX4 Register Address 32903 32904 32905 32906 32907 32908 32909 32910 32911 32912 32913 32914 32915 32916 32917 32918 32919 32920 32921 32922 32923 32924 32925 32926 32927 32928 32929 32930 32931 32932 32933 32934 32935 32936 32937 32938 32939 32940 32941 32942 32943 32944 32945 32946 - 33030 36864 36865 36866 36867 36868 36869 Register Name Default value Customer Area 9 Customer Area 10 Customer Area 11 Customer Area 12 Customer Area 13 Customer Area 14 Customer Area 15 Customer Area 16 Customer Area 17 Customer Area 18 Customer Area 19 Customer Area 20 Customer Area 21 Customer Area 22 Customer Area 23 Customer Area 24 Customer Area 25 Customer Area 26 Customer Area 27 Customer Area 28 Customer Area 29 Customer Area 30 Customer Area 31 Customer Area 32 Customer Area 33 Customer Area 34 Customer Area 35 Customer Area 36 Customer Area 37 Customer Area 38 Customer Area 39 Customer Area 40 Customer Area 41 Customer Area 42 Customer Area 43 Customer Area 44 Customer Area 45 Customer Area 46 Customer Area 47 XM_SMI Register address XM_SMI Register data XM_SMI command 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to page 23 Refer to page 23 Refer to page 23 Refer to page 24 0 Refer to page 24 Refer to page 24 Refer to page 25 Refer to page 25 Refer to page 25 Refer to page 26 AGGREGATE_MOD_CTRL Vender Specific RX_ALARM_CTRL TX_ALARM_CTRL LASI_CTRL RX_ALARM_STAT TX_ALARM_STAT LASI_STAT Fujitsu Component Limited Page 20 of 24 x-mGC, Electrical Transceiver for 10GBASE-CX4 Register detailed description Register 0x8000 -- NVR_CTRL_STAT Address 0.15:6 0.5 Name Reserved COMM 0.4 0.3:2 Reserved COMM_STAT 0.1:0 EXT_COMM Description Command 0 = Read NVR 1 = Write NVR The set this bit to perform write operation or clear it for read operation command status 00 = Idle 01 = Command completed successfully 10 = Command in progress 11 = Command failed Extended command 00 = Reserved 01 = Reserved 10 = Reserved 11 = Read/Write all NVR Mode NO RW Default 0 NO RO 00 RW 11 Mode RW Default 0h Mode RW Default 0h Mode NO RW Default RW 0 RW 0 Writing 11 to this filed performs write or read operation to/from all registers depends on the value of command field. Register 0x80AE -- XM_SMI_ADDR Address 174.15:0 Name Description XM_SMI_ADDR Address register for HOST indirect SMI transactions Register 0x80AF -- XM_SMI_DATA Address 175.15:0 Name Description XM_SMI_DATA Data register for HOST indirect SMI transactions Register 0x80B0 -- XM_SMI_COMMAND Address Name Description 176.15:3 Reserved 176.2 WR_COMMAND Specifies the host initiate SMI write transaction. This register is cleared at the end of the write operation 0 = idle 1 = write command 176.1 RD_COMMAND Specifies the host initiate SMI read transaction This register is cleared at the end of the write operation 0 = idle 1 = read operation 176.0 HOST_LINE Notice: a write operation has priority over read operation. Specifies to which PHY the host turns 0 = host turns to line phy 1 = host turns to host phy Fujitsu Component Limited Page 21 of 24 0 x-mGC, Electrical Transceiver for 10GBASE-CX4 Register 0x80B1 -- AGGREGATE_MOD_CTRL Address 7:4 3 Name Reserved XMRESET 2 write_protect 1 D2_INT_AGG 0 D1_INT_AGG Description The content of this register drives xmreset 0 – Normal operation 1 – Retimer is held at reset Mode NO RW This register write protecting the basic region and vendor RW specific register 0 = vendor specific register area is not write protected 1 = vendor specific is write protected The content of this register drives INT/AGG input of the RW retimer port 2 The content of this register drives INT/AGG input of the RW retimer port 1 Default 0 1 1 1 Register 0x9000 -- RX_ALARM_CTRL Address Name Description Mode 0.15:5 Reserved NO 0.4 PMA_PMD_REC_ PMA/PMD local receiver fault control, setting this bit RW LOC_FAULT_CT enables LASI indication for PMA/PMD local receiver fault. RL 0 – Disable 1 - Enable 0.3 PCS_REC_LOC_F PCS local receiver fault control, setting this bit enables RW AULT_CTRL LASI indication for PCS local receiver fault. 0 – Disable 1 - Enable 0.2:1 0.0 Reserved NO PHY_XS_REC_L PHY XS local receiver fault control, setting this bit enables RW OC_FAULT_CTR LASI indication for PHY XS local receiver fault. L 0 – Disable 1 - Enable Default 1 1 1 Register 0x9001 -- TX_ALARM_CTRL Address Name Description Mode 15:5 Reserved NO 4 PMA_PMD_TAR_ PMA/PMD local transmitter fault control, setting this bit RW LOC_FAULT_CT enables LASI indication for PMA/PMD local transmitter RL fault. 0 – Disable 1 - Enable 3 2:1 PCS_TAR_LOC_F PCS local transmitter fault control, setting this bit enables RW AULT_CTRL LASI indication for PCS local transmitter fault. 0 – Disable 1 - Enable Reserved NO Fujitsu Component Limited Page 22 of 24 Default 1 1 x-mGC, Electrical Transceiver for 10GBASE-CX4 Address 0 Name Description Mode PHY_XS_TAR_L PHY XS local transmitter fault control, setting this bit RW OC_FAULT_CTR enables LASI indication for PHY XS local transmitter fault. L 0 – Disable 1 - Enable Default 1 Register 0x9002 -- LASI_CTRL Address 15:3 2 1 0 Name Description Reserved RX_ALARM_EN receive alarm enable 0 – disable 1 - Enable TX_ALARM_EN Transmit alarm enable 0 – disable 1 – enable LS_ALARM_EN LASI alarm enable 0 – disable 1 - enable Mode NO RW Default RW 0 RW 0 Mode NO RO Default RO 0 NO RO 0 0 Register 0x9003 -- RX_ALARM_STAT Address Name Description 15:5 Reserved 4 PMA_PMD_REC_ PMA/PMD local receiver fault status, LOC_FAULT_STA 0 – Normal T 1 – Fault indication 3 PCS_REC_LOC_F PCS local receiver fault status, AULT_STAT 0 – Normal 1 – Fault indication 2:1 Reserved 0 PHY_XS_REC_L PHY XS local receiver fault status, OC_FAULT_STAT 0 – Normal 1 – Fault indication 0 Register 0x9004 -- TX_ALARM_STAT Address Name Description 15:5 Reserved 4 PMA_PMD_TAR_ PMA/PMD local transmitter fault status, LOC_FAULT_STA 0 – Normal T 1 – Fault indication 3 PCS_TAR_LOC_F PCS local transmitter fault status, AULT_STAT 0 – Normal 1 – Fault indication 2:1 Reserved 0 PHY_XS_TAR_L PHY XS local transmitter fault status, OC_FAULT_STAT 0 – Normal 1 – Fault indication Fujitsu Component Limited Page 23 of 24 Mode NO RO Default RO 0 NO RO 0 0 x-mGC, Electrical Transceiver for 10GBASE-CX4 Register 0x9005 -- LASI_STAT Address 15:4 3 2 1 0 Name Description Reserved SMI_MFSM_HOS T_CONTROL_GR ANT RX_ALARM Receive alarm status TX_ALARM Transmit alarm status LS_ALARM LASI alarm status References • XENPAK 10 Gigabit Ethernet MSA rev 3.0, • IEEE 802.3ae clause 45 X2 10 Gigabit Ethernet MSA rev 2.0 Fujitsu Component Limited Page 24 of 24 Mode NO RO Default RO RO RO 0 0 0 0