FUJITSU MICROELECTRONICS
DATA SHEET
DS07-13705-7E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90595G Series
MB90598G/F598G/V595G
■ DESCRIPTION
The MB90595G series with FULL-CAN interface and FLASH ROM is especially designed for automotive and
industrial applications. Its main features are two on board CAN Interfaces, which conform to V2.0 Part A and Part
B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN
approach.
The instruction set of F2MC-16LX CPU core inherits an AT architecture of the F2MC* family with additional
instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing
long word data.
The MB90595G series has peripheral resources of 8/10-bit A/D converters, UART (SCI), extended I/O serial
interface, 8/16-bit PPG timer, I/O timer (input capture (ICU), output compare (OCU)) and stepping motor controller.
* : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2002-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2008.9
MB90595G Series
■ FEATURES
• Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation
(at oscillation of 4 MHz, 4 MHz to 16 MHz).
Minimum instruction execution time: 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock,
VCC of 5.0 V)
• Instruction set to optimize controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C language) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed: 4-byte instruction queue
• Enhanced interrupt function: 8 levels, 34 factors
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI2OS): Up to 10 channels
• Embedded ROM size and types
Mask ROM: 128 Kbytes
Flash ROM: 128 Kbytes
Embedded RAM size: 4 Kbytes (MB90595G: 6 Kbytes)
• Flash ROM
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector
Erase can be performed on each block
Block protection with external programming voltage
• Low-power consumption (stand-by) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Hardware stand-by mode
• Process: 0.5 µm CMOS technology
• I/O port
General-purpose I/O ports: 78 ports
Push-pull output and Schmitt trigger input.
Programmable on each bit as I/O or signal for peripherals.
• Timer
Watchdog timer: 1 channel
8/16-bit PPG timer: 8/16-bit × 6 channels
16-bit re-load timer: 2 channels
(Continued)
2
DS07-13705-7E
MB90595G Series
(Continued)
• 16-bit I/O timer
16-bit Free-run timer: 1 channel
Input capture: 4 channels
Output compare: 4 channels
• Extended I/O serial interface: 1 channel
• UART0
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used.
• UART1 (SCI)
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized serial transmission (I/O extended transmission) can be selectively
used.
• Stepping motor controller (4 channels)
• External interrupt circuit (8 channels)
A module for starting an extended intelligent I/O service (EI2OS) and generating an external interrupt which
is triggered by an external input.
• Delayed interrupt generation module: Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels)
8/10-bit resolution can be selectively used.
Starting by an external trigger input.
• FULL-CAN interface: 1 channel
Conforming to Version 2.0 Part A and Part B
Flexible message buffering (mailbox and FIFO buffering can be mixed)
• 18-bit Time-base counter
• External bus interface: Maximum address space 16 Mbytes
DS07-13705-7E
3
MB90595G Series
■ PRODUCT LINEUP
Features
MB90598G
MB90F598G
MB90V595G
Mask ROM product
Flash ROM product
Evaluation product
ROM size
128 Kbytes
128 Kbytes
Boot block
Hard-wired reset vector
None
RAM size
4 Kbytes
4 Kbytes
6 Kbytes
Classification
Emulator-specific power
supply *1
⎯
None
CPU functions
The number of instructions: 351
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 8 bits, 16 bits
Minimum execution time: 62.5 ns (at machine clock frequency of 16 MHz)
Interrupt processing time: 1.5 µs
(at machine clock frequency of 16 MHz, minimum value)
UART0
Clock synchronized transmission (500 K/1 M/2 Mbps)
Clock asynchronized transmission (4808/5208/9615/10417/19230/38460/62500
/500000 bps at machine clock frequency of 16 MHz)
Transmission can be performed by bi-directional serial transmission or by master/
slave connection.
UART1(SCI)
Clock synchronized transmission (62.5 K/125 K/250 K/500 K/1 Mbps)
Clock asynchronized transmission (1202/2404/4808/9615/31250 bps)
Transmission can be performed by bi-directional serial transmission or by master/
slave connection.
8/10-bit A/D converter
Conversion precision: 8/10-bit can be selectively used.
Number of inputs: 8
One-shot conversion mode (converts selected channel once only)
Scan conversion mode (converts two or more successive channels and can program
up to 8 channels)
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)
8/16-bit PPG timers
(6 channels)
Number of channels: 6 (8/16-bit × 6 channels)
PPG operation of 8-bit or 16-bit
A pulse wave of given intervals and given duty ratios can be output.
Pulse interval: fsys, fsys/21, fsys/22, fsys/23, fsys/24 (fsys = system clock frequency)
128µs (fosc = 4MHz: oscillation clock frequency)
16-bit Reload timer
Number of channels: 2
Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = System clock frequency)
Supports External Event Count function
16-bit
I/O
timer
16-bit
Number of channels: 4
Output compares Pin input factor: A match signal of compare register
Input captures
Number of channels: 4
Rewriting a register value upon a pin input (rising, falling, or both edges)
(Continued)
4
DS07-13705-7E
MB90595G Series
(Continued)
Features
CAN Interface
MB90598G
MB90F598G
MB90V595G
Number of channels: 1
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering:
Full bit compare / Full bit mask / Two partial bit masks
Supports up to 1Mbps
CAN bit timing setting:
MB90598G/F598G:TSEG2 ≥ RSJW
Stepping motor controller Four high current outputs for each channel
(4 channels)
Synchronized two 8-bit PWM’s for each channel
External interrupt circuit
Number of inputs: 8
Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.
Serial IO
Clock synchronized transmission (31.25 K/62.5 K/125 K/500 K/1 Mbps at system clock
frequency of 16 MHz)
LSB first/MSB first
Watchdog timer
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(at oscillation of 4 MHz, minimum value)
Flash Memory
Supports automatic programming, Embedded Algorithm and
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector in Flash
Memory
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Writer from Minato Electronics, Inc.
Low-power consumption
Sleep/stop/CPU intermittent operation/watch timer/hardware stand-by
(stand-by) mode
Process
CMOS
Power supply voltage for
operation*2
Package
+5 V±10 %
QFP-100
PGA-256
*1: It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.
Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details.
*2: Varies with conditions such as the operating frequency. (See “■ ELECTRICAL CARACTERISTICS.”)
DS07-13705-7E
5
MB90595G Series
■ PIN ASSIGNMENT
Vss
81
X1
X0
83
82
P00/IN0
Vcc
85
84
P02/IN2
P01/IN1
86
87
88
89
90
P10/PPG0
P07/OUT3
P06/OUT2
P05/OUT1
P04/OUT0
P03/IN3
91
92
93
P12/PPG2
P11/PPG1
95
94
P14/PPG4
P13/PPG3
97
96
P16/TIN1
P15/PPG5
99
98
P17/TOT1
100
(Top view)
P20
1
80
P95/INT3
P21
2
79
P94/INT2
P22
3
78
P93/INT1
P23
P24
4
77
5
76
RST
P92/INT0
P75/PWM1M1
P44/SCK1
Vcc
22
59
P74/PWM1P1
23
58
DVCC
P45/SOT1
P46/SOT2
24
57
P73/PWM2M0
25
56
P72/PWM2P0
P47/SCK2
26
55
P71/PWM1M0
C
27
54
P70/PWM1P0
P50/SIN2
P51/INT4
28
53
DVSS
29
52
HST
P52/INT5
30
51
MD2
50
60
MD1
21
49
P76/PWM2P1
P43/SIN1
48
61
MD0
P77/PWM2M1
20
P57/TOT0
62
P56/TIN0
19
47
DVSS
P41/SCK0
P42/SIN0
46
63
P67/AN7
18
45
P80/PWM1P2
P40/SOT0
P66/AN6
17
64
44
P81/PWM1M2
P37
P65/AN5
65
43
16
P64/AN4
P82/PWM2P2
P36
42
66
41
15
Vss
P83/PWM2M2
P35
P63/AN3
67
40
DVCC
14
P62/AN2
68
39
P84/PWM1P3
13
38
69
P61/AN1
12
P60/AN0
P85/PWM1M3
P32
P33
P34
37
11
70
36
P86/PWM2P3
Vss
AVss
71
AVRL
10
35
P87/PWM2M3
P31
34
DVSS
72
AVcc
73
9
AVRH
8
33
P27
P30
P55/ADTG
P91/RX
P90/TX
32
74
31
75
7
P54/INT7
6
P53/INT6
P25
P26
(FPT-100P-M06)
6
DS07-13705-7E
MB90595G Series
■ PIN DESCRIPTION
Pin no.
Pin name
82
X0
83
X1
77
52
85 to 88
89 to 92
93 to 98
Oscillator pin
RST
B
Reset input
HST
C
Hardware standby input
IN0 to IN3
P04 to P07
OUT0 to OUT3
P10 to P15
PPG0 to PPG5
P16
TIN1
P17
100
Function
A
P00 to P03
99
Circuit type
TOT1
G
G
D
D
D
General purpose IO
Inputs for the Input Captures
General purpose IO
Outputs for the Output Compares.
General purpose IO
Outputs for the Programmable Pulse Generators
General purpose IO
TIN input for the 16-bit Reload Timer 1
General purpose IO
TOT output for the 16-bit Reload Timer 1
1 to 8
P20 to P27
G
General purpose IO
9 to 10
P30 to P31
G
General purpose IO
12 to 16
P32 to P36
G
General purpose IO
17
P37
D
General purpose IO
18
19
20
21
22
24
25
26
P40
SOT0
P41
SCK0
P42
SIN0
P43
SIN1
P44
SCK1
P45
SOT1
P46
SOT2
P47
SCK2
G
G
G
G
G
G
G
G
General purpose IO
SOT output for UART 0
General purpose IO
SCK input/output for UART 0
General purpose IO
SIN input for UART 0
General purpose IO
SIN input for UART 1
General purpose IO
SCK input/output for UART 1
General purpose IO
SOT output for UART 1
General purpose IO
SOT output for the Serial IO
General purpose IO
SCK input/output for the Serial IO
(Continued)
DS07-13705-7E
7
MB90595G Series
Pin no.
28
29 to 32
33
38 to 41
43 to 46
47
48
Pin name
P50
SIN2
P51 to P54
INT4 to INT7
P55
ADTG
P60 to P63
AN0 to AN3
P64 to P67
AN4 to AN7
P56
TIN0
P57
TOT0
Circuit type
D
D
D
E
E
D
D
P70 to P73
54 to 57
PWM1P0
PWM1M0
PWM2P0
PWM2M0
PWM1P1
PWM1M1
PWM2P1
PWM2M1
F
PWM1P2
PWM1M2
PWM2P2
PWM2M2
F
74
75
PWM1P3
PWM1M3
PWM2P3
PWM2M3
P90
TX
P91
RX
General purpose IO
External interrupt input for INT4 to INT7
General purpose IO
Input for the external trigger of the A/D Converter
General purpose IO
Inputs for the A/D Converter
General purpose IO
Inputs for the A/D Converter
General purpose IO
TIN input for the 16-bit Reload Timer 0
General purpose IO
TOT output for the 16-bit Reload Timer 0
Output for Stepper Motor Controller channel 0
Output for Stepper Motor Controller channel 1
General purpose IO
F
P84 to P87
69 to 72
SIN Input for the Serial IO
General purpose IO
P80 to P83
64 to 67
General purpose IO
General purpose IO
P74 to P77
59 to 62
Function
Output for Stepper Motor Controller channel 2
General purpose IO
F
D
D
Output for Stepper Motor Controller channel 3
General purpose IO
TX output for CAN Interface
General purpose IO
RX input for CAN Interface
(Continued)
8
DS07-13705-7E
MB90595G Series
(Continued)
Pin no.
Pin name
P92
76
78 to 80
INT0
P93 to P95
INT1 to INT3
Circuit type
D
D
Function
General purpose IO
External interrupt input for INT0
General purpose IO
External interrupt input for INT1 to INT3
58, 68
DVCC
⎯
Dedicated power supply pins for the high current output buffers
(Pin No. 54 to 72)
53, 63, 73
DVSS
⎯
Dedicated ground pins for the high current output buffers
(Pin No. 54 to 72)
34
AVCC
Power supply
Dedicated power supply pin for the A/D Converter
37
AVSS
Power supply
Dedicated ground pin for the A/D Converter
35
AVRH
Power supply
Upper reference voltage input for the A/D Converter
36
AVRL
Power supply
Lower reference voltage input for the A/D Converter
49, 50
MD0
MD1
C
Operating mode selection input pins. These pins should be connected to VCC or VSS.
51
MD2
H
Operating mode selection input pin. This pin should be connected
to VCC or VSS.
27
C
⎯
External capacitor pin. A capacitor of 0.1µF should be
connected to this pin and VSS.
23, 84
VCC
Power supply
Power supply pins (5.0 V).
11, 42, 81
VSS
Power supply
Ground pins (0.0 V).
DS07-13705-7E
9
MB90595G Series
■ I/O CIRCUIT TYPE
Circuit Type
Circuit
Remarks
X1
Clock
input
• Oscillation feedback resistor:
1 MΩ approx.
X0
A
Hard, Soft Standby control
• Hysteresis input with pull-up
Resistor: 50 kΩ approx.
B
R
C
R
HYS
R
HYS
• Hysteresis input
• CMOS output
• CMOS Hysteresis input
VCC
P-ch
N-ch
D
R
HYS
• CMOS output
• CMOS Hysteresis input
• Analog input
VCC
P-ch
N-ch
E
Analog input
R
HYS
(Continued)
10
DS07-13705-7E
MB90595G Series
(Continued)
Circuit Type
Circuit
Remarks
• CMOS high current output
• CMOS Hysteresis input
VCC
P-ch
High current
N-ch
F
R
HYS
VCC
P-ch
• CMOS output
• CMOS Hysteresis input
• TTL input
(MB90F598G, only in Flash mode)
N-ch
G
R
HYS
R
T
R
H
DS07-13705-7E
TTL
HYS
• Hysteresis input
Pull-down Resistor: 50 kΩ approx.
(except MB90F598G)
R
11
MB90595G Series
■ HANDLING DEVICES
(1) Make Sure that the Voltage not Exceed the Maximum Rating (to Avoid a Latch-up).
In CMOS ICs, a latch-up phenomenon is caused when an voltage exceeding VCC or an voltage below VSS is
applied to input or output pins or a voltage exceeding the rating is applied across VCC and VSS.
When a latch-up is caused, the power supply current may be dramatically increased causing resultant thermal
break-down of devices. To avoid the latch-up, make sure that the voltage not exceed the maximum rating.
In turning on/turning off the analog power supply, make sure the analog power voltage (AVCC, AVRH, DVCC) and
analog input voltages not exceed the digital voltage (VCC).
(2) Treatment of Unused Pins
Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused
input pins should be pulled up or pulled down through at least 2 kΩ resistance.
Unused input/output pins may be left open in output state, but if such pins are in input state they should be
handled in the same way as input pins.
(3) Using external clock
In using the external clock, drive X0 pin only and leave X1 pin unconnected.
Using external clock
X0
MB90595G Series
Open
X1
(4) Power supply pins (Vcc/Vss)
In products with multiple Vcc or Vss pins, pins with the same potential are internally connected in the device to
avoid abnormal operations including latch-up. However, you must connect the pins to an external power and a
ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused
by the rise in the ground level, and to conform to the total current rating (See the figure below.)
Make sure to connect Vcc and Vss pins via lowest impedance to power lines.
It is recommended to provide a bypass capacitor of around 0.1 µF between Vcc and Vss pins near the device.
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90595G
Series
Vcc
Vss
Vss
12
Vcc
DS07-13705-7E
MB90595G Series
(5) Pull-up/down resistors
The MB90595G Series does not support internal pull-up/down resistors. Use external components where needed.
(6) Crystal Oscillator Circuit
Noises around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via
shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure
that lines of oscillation circuit not cross the lines of other circuits.
A printed circuit board artwork surrounding the X0 and X1 pins with ground area for stabilizing the operation is
highly recommended.
(7) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after
turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable).
(8) Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = DVCC = VSS.
(9) N.C. Pin
The N.C. (internally connected) pin must be opened for use.
(10) Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 µs or more (0.2 V to 2.7 V).
(11) Indeterminate outputs from ports 0 and 1 (MB90V595G only)
During oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the
outputs from ports 0 and 1 become following state.
• If RST pin is “H”, the outputs become indeterminate.
• If RST pin is “L”, the outputs become high-impedance.
Pay attention to the port output timing shown as follows.
Oscillation setting time∗2
RST pin is “H”
Power-on reset∗1
Vcc (Power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal
Period of indeterminated
*1:Power-on reset time: Period of “clock frequency × 217” (Clock frequency of 16 MHz: 8.19 ms)
*2:Oscillation setting time: Period of “clock frequency × 218” (Clock frequency of 16 MHz: 16.38ms)
DS07-13705-7E
13
MB90595G Series
Oscillation setting time∗2
RST pin is “L”
Power-on reset∗1
Vcc (Power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal
High-impedance
*1:Power-on reset time: Period of “clock frequency × 217” (Clock frequency of 16 MHz: 8.19 ms)
*2:Oscillation setting time: Period of “clock frequency × 218” (Clock frequency of 16 MHz: 16.38ms)
(12) Initialization
The device contains internal registers which are initialized only by a power-on reset. To initialize these registers,
please turn on the power again.
(13) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions
In the signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”), the value of the corresponding bank register (DTB, ADB, USB, SSB) is set in “00H”.
If the values of the corresponding bank register (DTB,ADB,USB,SSB) are set to other than “00H”, the remainder
by the execution result of the instruction is not stored in the register of the instruction operand.
(14) Using REALOS
The use of EI2OS is not possible with the REALOS real time operating system.
(15) Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected in the microcontroller, it may attempt to continue the operation using the freerunning frequency of the automatic oscillating circuit in the PLL circuitry even if the oscillator is out of place or
the clock input is stopped. Performance of this operation, however, cannot be guaranteed.
14
DS07-13705-7E
MB90595G Series
■ BLOCK DIAGRAM
X0,X1
RST
HST
Clock
Controller
F2MC-16LX
CPU
16-bit
Free-run
Timer
RAM 4 K
ROM/Flash
128 K
16-bit Input
Capture
4 ch
IN0 to IN3
16-bit Output
Compare
4 ch
OUT0 to OUT3
8/16-bit
PPG
6 ch
PPG0 to PPG5
Prescaler
SOT0
SCK0
SIN0
UART0
CAN
Controller
Prescaler
UART1
(SCI)
Timer 2 ch
Prescaler
SOT2
SCK2
SIN2
AVCC
AVSS
AN0 to AN7
AVRH
AVRL
ADTG
DS07-13705-7E
16-bit Reload
Serial I/O
F2MC-16 Bus
SOT1
SCK1
SIN1
RX
TX
TIN0, TIN1
TOT0, TOT1
PWM1M0 to PWM1M3
PWM1P0 to PWM1P3
SMC
4ch
PWM2M0 to PWM2M3
PWM2P0 to PWM2P3
DVCC
DVSS
10-bit ADC
8 ch
External
Interrupt
8 ch
INT0 to INT7
15
MB90595G Series
■ MEMORY SPACE
The memory space of the MB90595G Series is shown below
MB90V595G
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
00FFFFH
004000H
001FFFH
001900H
0018FFH
MB90598G/F598G
FFFFFFH
FF0000H
FEFFFFH
FE0000H
ROM (FF bank)
ROM (FE bank)
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM
(Image of FF bank)
00FFFFH
004000H
ROM
(Image of FF bank)
Peripheral
001FFFH
001900H
Peripheral
RAM 6 K
0010FFH
RAM 4 K
000100H
0000BFH
000000H
000100H
Peripheral
0000BFH
000000H
Peripheral
Memory space map
Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C
compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the same
address, enabling reference of the table on the ROM without stating “far”.
For example, if an attempt has been made to access 00C000H , the contents of the ROM at FFC000H are
accessed. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in
the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image
for 004000H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H
to FFFFFFH.
16
DS07-13705-7E
MB90595G Series
■ I/O MAP
Address
Register
Abbreviation
Access
Peripheral
Initial value
00H
Port 0 Data Register
PDR0
R/W
Port 0
XXXXXXXXB
01H
Port 1 Data Register
PDR1
R/W
Port 1
XXXXXXXXB
02H
Port 2 Data Register
PDR2
R/W
Port 2
XXXXXXXXB
03H
Port 3 Data Register
PDR3
R/W
Port 3
XXXXXXXXB
04H
Port 4 Data Register
PDR4
R/W
Port 4
XXXXXXXXB
05H
Port 5 Data Register
PDR5
R/W
Port 5
XXXXXXXXB
06H
Port 6 Data Register
PDR6
R/W
Port 6
XXXXXXXXB
07H
Port 7 Data Register
PDR7
R/W
Port 7
XXXXXXXXB
08H
Port 8 Data Register
PDR8
R/W
Port 8
XXXXXXXXB
09H
Port 9 Data Register
PDR9
R/W
Port 9
_ _ XXXXXXB
0AH to 0FH
Reserved
10H
Port 0 Direction Register
DDR0
R/W
Port 0
0 0 0 0 0 0 0 0B
11H
Port 1 Direction Register
DDR1
R/W
Port 1
0 0 0 0 0 0 0 0B
12H
Port 2 Direction Register
DDR2
R/W
Port 2
0 0 0 0 0 0 0 0B
13H
Port 3 Direction Register
DDR3
R/W
Port 3
0 0 0 0 0 0 0 0B
14H
Port 4 Direction Register
DDR4
R/W
Port 4
0 0 0 0 0 0 0 0B
15H
Port 5 Direction Register
DDR5
R/W
Port 5
0 0 0 0 0 0 0 0B
16H
Port 6 Direction Register
DDR6
R/W
Port 6
0 0 0 0 0 0 0 0B
17H
Port 7 Direction Register
DDR7
R/W
Port 7
0 0 0 0 0 0 0 0B
18H
Port 8 Direction Register
DDR8
R/W
Port 8
0 0 0 0 0 0 0 0B
19H
Port 9 Direction Register
DDR9
R/W
Port 9
_ _ 0 0 0 0 0 0B
R/W
Port 6, A/D
1 1 1 1 1 1 1 1B
1AH
1BH
Reserved
Analog Input Enable Register
1CH to 1FH
ADER
Reserved
20H
Serial Mode Control Register 0
UMC0
R/W
0 0 0 0 0 1 0 0B
21H
Serial status Register 0
USR0
R/W
0 0 0 1 0 0 0 0B
22H
Serial Input/Output Data Register 0
UIDR0/
UODR0
R/W
23H
Rate and Data Register 0
URD0
R/W
0 0 0 0 0 0 0 XB
24H
Serial Mode Register 1
SMR1
R/W
0 0 0 0 0 0 0 0B
25H
Serial Control Register 1
SCR1
R/W
0 0 0 0 0 1 0 0B
26H
Serial Input/Output Data Register 1
SIDR1/
SODR1
R/W
27H
Serial Status Register 1
SSR1
R/W
0 0 0 0 1 _ 0 0B
28H
UART1 Prescaler Control Register
U1CDCR
R/W
0 _ _ _ 1 1 1 1B
UART0
UART1
XXXXXXXXB
XXXXXXXXB
(Continued)
DS07-13705-7E
17
MB90595G Series
Address
Register
29H to 2AH
Abbreviation
Access
Peripheral
Initial value
Reserved
2BH
Serial IO Prescaler
SCDCR
R/W
0 _ _ _ 1 1 1 1B
2CH
Serial Mode Control Register (low-order)
SMCS
R/W
_ _ _ _ 0 0 0 0B
2DH
Serial Mode Control Register (high-order)
SMCS
R/W
2EH
Serial Data Register
SDR
R/W
XXXXXXXXB
2FH
Edge Selector
SES
R/W
_ _ _ _ _ _ _ 0B
30H
External Interrupt Enable Register
ENIR
R/W
0 0 0 0 0 0 0 0B
31H
External Interrupt Request Register
EIRR
R/W
32H
External Interrupt Level Register
ELVR
R/W
33H
External Interrupt Level Register
ELVR
R/W
0 0 0 0 0 0 0 0B
34H
A/D Control Status Register 0
ADCS0
R/W
0 0 0 0 0 0 0 0B
35H
A/D Control Status Register 1
ADCS1
R/W
36H
A/D Data Register 0
ADCR0
R
37H
A/D Data Register 1
ADCR1
R/W
38H
PPG0 Operation Mode Control Register
PPGC0
R/W
39H
PPG1 Operation Mode Control Register
PPGC1
R/W
3AH
PPG0, 1 Output Pin Control Register
PPG01
R/W
3BH
External Interrupt
A/D Converter
0 0 0 0 0 0 1 0B
XXXXXXXXB
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
XXXXXXXXB
0 0 0 0 1 _ XXB
16-bit Programmable Pulse
Generator 0/1
0 _ 0 0 0 _ _ 1B
0 _ 0 0 0 0 0 1B
0 0 0 0 0 0 _ _B
Reserved
3CH
PPG2 Operation Mode Control Register
PPGC2
R/W
3DH
PPG3 Operation Mode Control Register
PPGC3
R/W
3EH
PPG2, 3 Output Pin Control Register
PPG23
R/W
3FH
16-bit Programmable Pulse
Generator 2/3
0 _ 0 0 0 _ _ 1B
0 _ 0 0 0 0 0 1B
0 0 0 0 0 0 _ _B
Reserved
40H
PPG4 Operation Mode Control Register
PPGC4
R/W
41H
PPG5 Operation Mode Control Register
PPGC5
R/W
42H
PPG4, 5 Output Pin Control Register
PPG45
R/W
43H
16-bit Programmable Pulse
Generator 4/5
0 _ 0 0 0 _ _ 1B
0 _ 0 0 0 0 0 1B
0 0 0 0 0 0 _ _B
Reserved
44H
PPG6 Operation Mode Control Register
PPGC6
R/W
45H
PPG7 Operation Mode Control Register
PPGC7
R/W
46H
PPG6, 7 Output Pin Control Register
PPG67
R/W
47H
16-bit Programmable Pulse
Generator 6/7
0 _ 0 0 0 _ _ 1B
0 _ 0 0 0 0 0 1B
0 0 0 0 0 0 _ _B
Reserved
48H
PPG8 Operation Mode Control Register
PPGC8
R/W
49H
PPG9 Operation Mode Control Register
PPGC9
R/W
4AH
PPG8, 9 Output Pin Control Register
PPG89
R/W
4BH
Serial IO
16-bit Programmable Pulse
Generator 8/9
0 _ 0 0 0 _ _ 1B
0 _ 0 0 0 0 0 1B
0 0 0 0 0 0 _ _B
Reserved
(Continued)
18
DS07-13705-7E
MB90595G Series
Address
Register
4CH
PPGA Operation Mode Control Register
PPGCA
R/W
4DH
PPGB Operation Mode Control Register
PPGCB
R/W
4EH
PPGA, B Output Pin Control Register
PPGAB
R/W
4FH
Abbreviation Access
Peripheral
Initial value
16-bit
Programmable
Pulse
Generator A/B
0 _ 0 0 0 _ _ 1B
0 _ 0 0 0 0 0 1B
0 0 0 0 0 0 _ _B
Reserved
50H
Timer Control Status Register 0
TMCSR0
R/W
0 0 0 0 0 0 0 0B
51H
Timer Control Status Register 0
TMCSR0
R/W
_ _ _ _ 0 0 0 0B
52H
Timer 0/Reload Register 0
TMR0/
TMRLR0
R/W
53H
Timer 0/Reload Register 0
TMR0/
TMRLR0
R/W
XXXXXXXXB
54H
Timer Control Status Register 1
TMCSR1
R/W
0 0 0 0 0 0 0 0B
55H
Timer Control Status Register 1
TMCSR1
R/W
16-bit
Reload Timer 0
XXXXXXXXB
_ _ _ _ 0 0 0 0B
16-bit
Reload Timer 1
56H
Timer Register 1/Reload Register 1
TMR1/
TMRLR1
R/W
57H
Timer Register 1/Reload Register 1
TMR1/
TMRLR1
R/W
58H
Output Compare Control Status Register 0
OCS0
R/W
59H
Output Compare Control Status Register 1
OCS1
R/W
5AH
Output Compare Control Status Register 2
OCS2
R/W
5BH
Output Compare Control Status Register 3
OCS3
R/W
5CH
Input Capture Control Status Register 0/1
ICS01
R/W
Input Capture 0/1 0 0 0 0 0 0 0 0B
5DH
Input Capture Control Status Register 2/3
ICS23
R/W
Input Capture 2/3 0 0 0 0 0 0 0 0B
5EH
PWM Control Register 0
PWC0
R/W
Stepping Motor
Controller 0
0 0 0 0 0 _ _ 0B
R/W
Stepping Motor
Controller 1
0 0 0 0 0 _ _ 0B
R/W
Stepping Motor
Controller 2
0 0 0 0 0 _ _ 0B
R/W
Stepping Motor
Controller 3
0 0 0 0 0 _ _ 0B
5FH
XXXXXXXXB
XXXXXXXXB
Output
Compare 0/1
0 0 0 0 _ _ 0 0B
Output
Compare 2/3
0 0 0 0 _ _ 0 0B
_ _ _ 0 0 0 0 0B
_ _ _ 0 0 0 0 0B
Reserved
60H
PWM Control Register 1
61H
PWC1
Reserved
62H
PWM Control Register 2
63H
PWC2
Reserved
64H
PWM Control Register 3
65H
PWC3
Reserved
66H
Timer Data Register (low-order)
TCDT
R/W
67H
Timer Data Register (high-order)
TCDT
R/W
68H
Timer Control Status Register
TCCS
R/W
69H to 6EH
0 0 0 0 0 0 0 0B
16-bit Free-run
Timer
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
Reserved
(Continued)
DS07-13705-7E
19
MB90595G Series
Address
Register
Abbreviation Access
Peripheral
Initial value
6FH
ROM Mirror Function Selection Register
ROMM
R/W
ROM Mirror
_ _ _ _ _ _ _ 1B
70H
PWM1 Compare Register 0
PWC10
R/W
71H
PWM2 Compare Register 0
PWC20
R/W
72H
PWM1 Select Register 0
PWS10
R/W
73H
PWM2 Select Register 0
PWS20
R/W
_ 0 0 0 0 0 0 0B
74H
PWM1 Compare Register 1
PWC11
R/W
XXXXXXXXB
75H
PWM2 Compare Register 1
PWC21
R/W
76H
PWM1 Select Register 1
PWS11
R/W
77H
PWM2 Select Register 1
PWS21
R/W
_ 0 0 0 0 0 0 0B
78H
PWM1 Compare Register 2
PWC12
R/W
XXXXXXXXB
79H
PWM2 Compare Register 2
PWC22
R/W
7AH
PWM1 Select Register 2
PWS12
R/W
7BH
PWM2 Select Register 2
PWS22
R/W
_ 0 0 0 0 0 0 0B
7CH
PWM1 Compare Register 3
PWC13
R/W
XXXXXXXXB
7DH
PWM2 Compare Register 3
PWC23
R/W
7EH
PWM1 Select Register 3
PWS13
R/W
7FH
PWM2 Select Register 3
PWS23
R/W
XXXXXXXXB
Stepping Motor
Controller 0
Stepping Motor
Controller 1
Stepping Motor
Controller 2
Stepping Motor
Controller 3
XXXXXXXXB
_ _ 0 0 0 0 0 0B
XXXXXXXXB
_ _ 0 0 0 0 0 0B
XXXXXXXXB
_ _ 0 0 0 0 0 0B
XXXXXXXXB
_ _ 0 0 0 0 0 0B
_ 0 0 0 0 0 0 0B
80H to 8FH
CAN Controller. Refer to section about CAN Controller
90H to 9DH
Reserved
9EH
Program Address Detection Control
Status Register
PACSR
R/W
Address Match
0 0 0 0 0 0 0 0B
Detection Function
9FH
Delayed Interrupt/Request Register
DIRR
R/W
Delayed Interrupt _ _ _ _ _ _ _ 0B
A0H
Low-Power Mode Control Register
LPMCR
R/W
Low Power
Controller
0 0 0 1 1 0 0 0B
A1H
Clock Selection Register
CKSCR
R/W
Low Power
Controller
1 1 1 1 1 1 0 0B
XXXXX 1 1 1B
A2H to A7H
Reserved
A8H
Watchdog Timer Control Register
WDTC
R/W
Watchdog Timer
A9H
Time Base Timer Control Register
TBTC
R/W
Time Base Timer 1 _ _ 0 0 1 0 0B
AAH to ADH
AEH
AFH
Reserved
Flash Memory Control Status Register
(MB90F598G only.
Otherwise reserved)
FMCS
R/W
Flash Memory
0 0 0 X 0 0 0 0B
Reserved
(Continued)
20
DS07-13705-7E
MB90595G Series
Address
Register
B0H
Interrupt Control Register 00
ICR00
R/W
B1H
Interrupt Control Register 01
ICR01
R/W
B2H
Interrupt Control Register 02
ICR02
R/W
B3H
Interrupt Control Register 03
ICR03
R/W
0 0 0 0 0 1 1 1B
B4H
Interrupt Control Register 04
ICR04
R/W
0 0 0 0 0 1 1 1B
B5H
Interrupt Control Register 05
ICR05
R/W
0 0 0 0 0 1 1 1B
B6H
Interrupt Control Register 06
ICR06
R/W
0 0 0 0 0 1 1 1B
B7H
Interrupt Control Register 07
ICR07
R/W
0 0 0 0 0 1 1 1B
B8H
Interrupt Control Register 08
ICR08
R/W
0 0 0 0 0 1 1 1B
B9H
Interrupt Control Register 09
ICR09
R/W
BAH
Interrupt Control Register 10
ICR10
R/W
BBH
Interrupt Control Register 11
ICR11
R/W
0 0 0 0 0 1 1 1B
BCH
Interrupt Control Register 12
ICR12
R/W
0 0 0 0 0 1 1 1B
BDH
Interrupt Control Register 13
ICR13
R/W
0 0 0 0 0 1 1 1B
BEH
Interrupt Control Register 14
ICR14
R/W
0 0 0 0 0 1 1 1B
BFH
Interrupt Control Register 15
ICR15
R/W
0 0 0 0 0 1 1 1B
C0H to FFH
Abbreviation Access
Peripheral
Initial value
0 0 0 0 0 1 1 1B
Interrupt controller
Interrupt controller
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
Reserved
XXXXXXXXB
1900H
Reload Register L
PRLL0
R/W
1901H
Reload Register H
PRLH0
R/W
1902H
Reload Register L
PRLL1
R/W
1903H
Reload Register H
PRLH1
R/W
XXXXXXXXB
1904H
Reload Register L
PRLL2
R/W
XXXXXXXXB
1905H
Reload Register H
PRLH2
R/W
1906H
Reload Register L
PRLL3
R/W
1907H
Reload Register H
PRLH3
R/W
XXXXXXXXB
1908H
Reload Register L
PRLL4
R/W
XXXXXXXXB
1909H
Reload Register H
PRLH4
R/W
190AH
Reload Register L
PRLL5
R/W
190BH
Reload Register H
PRLH5
R/W
XXXXXXXXB
190CH
Reload Register L
PRLL6
R/W
XXXXXXXXB
190DH
Reload Register H
PRLH6
R/W
190EH
Reload Register L
PRLL7
R/W
190FH
Reload Register H
PRLH7
R/W
16-bit Programmable
Pulse
Generator 0/1
16-bit Programmable
Pulse
Generator 2/3
16-bit Programmable
Pulse
Generator 4/5
16-bit Programmable
Pulse
Generator 6/7
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
DS07-13705-7E
21
MB90595G Series
Address
Register
Abbreviation Access
1910H
Reload Register L
PRLL8
R/W
1911H
Reload Register H
PRLH8
R/W
1912H
Reload Register L
PRLL9
R/W
1913H
Reload Register H
PRLH9
R/W
1914H
Reload Register L
PRLLA
R/W
1915H
Reload Register H
PRLHA
R/W
1916H
Reload Register L
PRLLB
R/W
1917H
Reload Register H
PRLHB
R/W
1918H to 191FH
Peripheral
Initial value
XXXXXXXXB
16-bit Programmable
Pulse
Generator 8/9
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
16-bit Programmable
Pulse
Generator A/B
XXXXXXXXB
16-bit Programmable
Pulse Generator A/B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Reserved
1920H
Input Capture Register 0
(low-order)
IPCP0
R
XXXXXXXXB
1921H
Input Capture Register 0
(high-order)
IPCP0
R
XXXXXXXXB
1922H
Input Capture Register 1
(low-order)
IPCP1
R
XXXXXXXXB
1923H
Input Capture Register 1
(high-order)
IPCP1
R
XXXXXXXXB
1924H
Input Capture Register 2
(low-order)
IPCP2
R
XXXXXXXXB
1925H
Input Capture Register 2
(high-order)
IPCP2
R
XXXXXXXXB
1926H
Input Capture Register 3
(low-order)
IPCP3
R
XXXXXXXXB
1927H
Input Capture Register 3
(high-order)
IPCP3
R
XXXXXXXXB
1928H
Output Compare Register 0
(low-order)
OCCP0
R/W
XXXXXXXXB
1929H
Output Compare Register 0
(high-order)
OCCP0
R/W
XXXXXXXXB
192AH
Output Compare Register 1
(low-order)
OCCP1
R/W
XXXXXXXXB
192BH
Output Compare Register 1
(high-order)
OCCP1
R/W
XXXXXXXXB
Input Capture 0/1
Input Capture 2/3
Output Compare 0/1
(Continued)
22
DS07-13705-7E
MB90595G Series
(Continued)
Address
Register
Abbreviation Access
Peripheral
Initial value
192CH
Output Compare Register 2
(low-order)
OCCP2
R/W
XXXXXXXXB
192DH
Output Compare Register 2
(high-order)
OCCP2
R/W
XXXXXXXXB
192EH
Output Compare Register 3
(low-order)
OCCP3
R/W
XXXXXXXXB
192FH
Output Compare Register 3
(high-order)
OCCP3
R/W
XXXXXXXXB
Output Compare 2/3
1930H to 19FFH
Reserved
1A00H to 1AFFH
CAN Controller. Refer to section about CAN Controller
1B00H to 1BFFH
CAN Controller. Refer to section about CAN Controller
1C00H to 1EFFH
Reserved
1FF0H
Program Address Detection
Register 0 (low-order)
1FF1H
Program Address Detection
Register 0 (middle-order)
1FF2H
Program Address Detection
Register 0 (high-order)
1FF3H
Program Address Detection
Register 1 (low-order)
1FF4H
Program Address Detection
Register 1 (middle-order)
1FF5H
Program Address Detection
Register 1 (high-order)
XXXXXXXXB
PADR0
R/W
XXXXXXXXB
Address Match
Detection Function
PADR1
1FF6H to 1FFFH
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Reserved
• Description for Read/Write
R/W : Readable/writable
R : Read only
W : Write only
• Description of initial value
0 : the initial value of this bit is "0".
1 : the initial value of this bit is "1".
X : the initial value of this bit is undefined.
_ : this bit is unused. the initial value is undefined.
Note : Addresses in the range of 0000H to 00FFH, which are not listed in the table, are reserved for the primary
functions of the MCU. A read access to these reserved addresses results in reading “X”, and any write
access should not be performed.
DS07-13705-7E
23
MB90595G Series
■ CAN CONTROLLER
The CAN controller has the following features:
• Conforms to CAN Specification Version 2.0 Part A and B
- Supports transmission/reception in standard frame and extended frame formats
• Supports transmission of data frames by receiving remote frames
• 16 transmitting/receiving message buffers
- 29-bit ID and 8-byte data
- Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as ID acceptance mask
- Two acceptance mask registers in either standard frame format or extended frame format
• Bit rate programmable from 10 kbps to 2 Mbps (when input clock is at 16 MHz)
• List of Control Registers
Address
000080H
000081H
000082H
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
00008BH
00008CH
00008DH
00008EH
00008FH
001B00H
001B01H
001B02H
001B03H
001B04H
001B05H
001B06H
001B07H
Register
Abbreviation
Access
Initial Value
Message buffer valid register
BVALR
R/W
00000000 00000000B
Transmit request register
TREQR
R/W
00000000 00000000B
Transmit cancel register
TCANR
W
00000000 00000000B
Transmit complete register
TCR
R/W
00000000 00000000B
Receive complete register
RCR
R/W
00000000 00000000B
Remote request receiving register
RRTRR
R/W
00000000 00000000B
Receive overrun register
ROVRR
R/W
00000000 00000000B
Receive interrupt enable register
RIER
R/W
00000000 00000000B
Control status register
CSR
R/W, R
00---000 0----0-1B
Last event indicator register
LEIR
R/W
-------- 000-0000B
Receive/transmit error counter
RTEC
R
00000000 00000000B
BTR
R/W
-1111111 11111111B
Bit timing register
(Continued)
24
DS07-13705-7E
MB90595G Series
(Continued)
Address
001B08H
001B09H
001B0AH
001B0BH
001B0CH
001B0DH
001B0EH
001B0FH
Register
Abbreviation
Access
Initial Value
IDER
R/W
XXXXXXXX XXXXXXXXB
Transmit RTR register
TRTRR
R/W
00000000 00000000B
Remote frame receive waiting register
RFWTR
R/W
XXXXXXXX XXXXXXXXB
TIER
R/W
00000000 00000000B
IDE register
Transmit interrupt enable register
001B10H
001B11H
001B12H
XXXXXXXX XXXXXXXXB
Acceptance mask select register
AMSR
R/W
XXXXXXXX XXXXXXXXB
001B13H
001B14H
001B15H
001B16H
XXXXXXXX XXXXXXXXB
Acceptance mask register 0
AMR0
R/W
XXXXX--- XXXXXXXXB
001B17H
001B18H
001B19H
001B1AH
001B1BH
DS07-13705-7E
XXXXXXXX XXXXXXXXB
Acceptance mask register 1
AMR1
R/W
XXXXX--- XXXXXXXXB
25
MB90595G Series
• List of Message Buffers (ID Registers)
Address
Register
001A00H
to
General-purpose RAM
001A1FH
Abbreviation
Access
Initial Value
--
R/W
XXXXXXXXB
to
XXXXXXXXB
001A20H
001A21H
001A22H
XXXXXXXX XXXXXXXXB
ID register 0
IDR0
R/W
XXXXX--- XXXXXXXXB
001A23H
001A24H
001A25H
001A26H
XXXXXXXX XXXXXXXXB
ID register 1
IDR1
R/W
XXXXX--- XXXXXXXXB
001A27H
001A28H
001A29H
001A2AH
XXXXXXXX XXXXXXXXB
ID register 2
IDR2
R/W
XXXXX--- XXXXXXXXB
001A2BH
001A2CH
001A2DH
001A2EH
XXXXXXXX XXXXXXXXB
ID register 3
IDR3
R/W
XXXXX--- XXXXXXXXB
001A2FH
001A30H
001A31H
001A32H
XXXXXXXX XXXXXXXXB
ID register 4
IDR4
R/W
XXXXX--- XXXXXXXXB
001A33H
001A34H
001A35H
001A36H
XXXXXXXX XXXXXXXXB
ID register 5
IDR5
R/W
XXXXX--- XXXXXXXXB
001A37H
001A38H
001A39H
001A3AH
XXXXXXXX XXXXXXXXB
ID register 6
IDR6
R/W
XXXXX--- XXXXXXXXB
001A3BH
001A3CH
001A3DH
001A3EH
001A3FH
XXXXXXXX XXXXXXXXB
ID register 7
IDR7
R/W
XXXXX--- XXXXXXXXB
(Continued)
26
DS07-13705-7E
MB90595G Series
(Continued)
Address
Register
Abbreviation
Access
001A40H
001A41H
001A42H
XXXXXXXX XXXXXXXXB
ID register 8
IDR8
R/W
XXXXX--- XXXXXXXXB
001A43H
001A44H
001A45H
001A46H
XXXXXXXX XXXXXXXXB
ID register 9
IDR9
R/W
XXXXX--- XXXXXXXXB
001A47H
001A48H
001A49H
001A4AH
XXXXXXXX XXXXXXXXB
ID register 10
IDR10
R/W
XXXXX--- XXXXXXXXB
001A4BH
001A4CH
001A4DH
001A4EH
XXXXXXXX XXXXXXXXB
ID register 11
IDR11
R/W
XXXXX--- XXXXXXXXB
001A4FH
001A50H
001A51H
001A52H
XXXXXXXX XXXXXXXXB
ID register 12
IDR12
R/W
XXXXX--- XXXXXXXXB
001A53H
001A54H
001A55H
001A56H
XXXXXXXX XXXXXXXXB
ID register 13
IDR13
R/W
XXXXX--- XXXXXXXXB
001A57H
001A58H
001A59H
001A5AH
XXXXXXXX XXXXXXXXB
ID register 14
IDR14
R/W
XXXXX--- XXXXXXXXB
001A5BH
001A5CH
001A5DH
001A5EH
Initial Value
XXXXXXXX XXXXXXXXB
ID register 15
001A5FH
DS07-13705-7E
IDR15
R/W
XXXXX--- XXXXXXXXB
27
MB90595G Series
• List of Message Buffers (DLC Registers and Data Registers)
Address
Register
Abbreviation
001A60H
001A61H
001A62H
001A63H
001A64H
001A65H
001A66H
001A67H
001A68H
001A69H
001A6AH
001A6BH
001A6CH
001A6DH
001A6EH
001A6FH
001A70H
001A71H
001A72H
001A73H
001A74H
001A75H
001A76H
001A77H
001A78H
001A79H
001A7AH
001A7BH
001A7CH
001A7DH
001A7EH
001A7FH
Access
Initial Value
DLC register 0
DLCR0
R/W
----XXXXB
DLC register 1
DLCR1
R/W
----XXXXB
DLC register 2
DLCR2
R/W
----XXXXB
DLC register 3
DLCR3
R/W
----XXXXB
DLC register 4
DLCR4
R/W
----XXXXB
DLC register 5
DLCR5
R/W
----XXXXB
DLC register 6
DLCR6
R/W
----XXXXB
DLC register 7
DLCR7
R/W
----XXXXB
DLC register 8
DLCR8
R/W
----XXXX
DLC register 9
DLCR9
R/W
----XXXXB
DLC register 10
DLCR10
R/W
----XXXXB
DLC register 11
DLCR11
R/W
----XXXXB
DLC register 12
DLCR12
R/W
----XXXXB
DLC register 13
DLCR13
R/W
----XXXXB
DLC register 14
DLCR14
R/W
----XXXXB
DLC register 15
DLCR15
R/W
----XXXXB
DTR0
R/W
XXXXXXXXB
to
XXXXXXXXB
001A80H
to
Data register 0 (8 bytes)
001A87H
(Continued)
28
DS07-13705-7E
MB90595G Series
(Continued)
Address
Abbreviation
Access
Initial Value
001A88H
to
Data register 1 (8 bytes)
001A8FH
DTR1
R/W
XXXXXXXXB
to
XXXXXXXXB
001A90H
to
Data register 2 (8 bytes)
001A97H
DTR2
R/W
XXXXXXXXB
to
XXXXXXXXB
001A98H
to
Data register 3 (8 bytes)
001A9FH
DTR3
R/W
XXXXXXXXB
to
XXXXXXXXB
001AA0H
to
Data register 4 (8 bytes)
001AA7H
DTR4
R/W
XXXXXXXXB
to
XXXXXXXXB
001AA8H
to
Data register 5 (8 bytes)
001AAFH
DTR5
R/W
XXXXXXXXB
to
XXXXXXXXB
001AB0H
to
Data register 6 (8 bytes)
001AB7H
DTR6
R/W
XXXXXXXXB
to
XXXXXXXXB
001AB8H
to
Data register 7 (8 bytes)
001ABFH
DTR7
R/W
XXXXXXXXB
to
XXXXXXXXB
001AC0H
to
Data register 8 (8 bytes)
001AC7H
DTR8
R/W
XXXXXXXXB
to
XXXXXXXXB
001AC8H
to
Data register 9 (8 bytes)
001ACFH
DTR9
R/W
XXXXXXXXB
to
XXXXXXXXB
001AD0H
to
Data register 10 (8 bytes)
001AD7H
DTR10
R/W
XXXXXXXXB
to
XXXXXXXXB
001AD8H
to
Data register 11 (8 bytes)
001ADFH
DTR11
R/W
XXXXXXXXB
to
XXXXXXXXB
001AE0H
to
Data register 12 (8 bytes)
001AE7H
DTR12
R/W
XXXXXXXXB
to
XXXXXXXXB
001AE8H
to
Data register 13 (8 bytes)
001AEFH
DTR13
R/W
XXXXXXXXB
to
XXXXXXXXB
001AF0H
to
Data register 14 (8 bytes)
001AF7H
DTR14
R/W
XXXXXXXXB
to
XXXXXXXXB
001AF8H
to
Data register 15 (8 bytes)
001AFFH
DTR15
R/W
XXXXXXXXB
to
XXXXXXXXB
DS07-13705-7E
Register
29
MB90595G Series
■ INTERRUPT SOURCE, INTERRUPT VECTOR, AND INTERRUPT CONTROL REGISTER
Interrupt vector
Interrupt control register
EI2OS
clear
Number
Address
Number
Address
Reset
N/A
# 08
FFFFDCH
——
——
INT9 instruction
N/A
# 09
FFFFD8H
——
——
Exception
N/A
# 10
FFFFD4H
——
——
CAN RX
N/A
# 11
FFFFD0H
CAN TX/NS
N/A
# 12
FFFFCCH
ICR00
0000B0H
*1
# 13
FFFFC8H
N/A
# 14
FFFFC4H
ICR01
0000B1H
16-bit Reload Timer 0
*1
# 15
FFFFC0H
8/10-bit A/D Converter
*1
# 16
FFFFBCH
ICR02
0000B2H
16-bit Free-run Timer
N/A
# 17
FFFFB8H
External Interrupt (INT2/INT3)
*1
# 18
FFFFB4H
ICR03
0000B3H
Serial I/O
*1
# 19
FFFFB0H
External Interrupt (INT4/INT5)
*1
# 20
FFFFACH
ICR04
0000B4H
Input Capture 0
*1
# 21
FFFFA8H
8/16-bit PPG 0/1
N/A
# 22
FFFFA4H
ICR05
0000B5H
*1
# 23
FFFFA0H
N/A
# 24
FFFF9CH
ICR06
0000B6H
External Interrupt (INT6/INT7)
*1
# 25
FFFF98H
Input Capture 1
*1
# 26
FFFF94H
ICR07
0000B7H
8/16-bit PPG 4/5
N/A
# 27
FFFF90H
*1
# 28
FFFF8CH
ICR08
0000B8H
8/16-bit PPG 6/7
N/A
# 29
FFFF88H
Input Capture 2
*1
# 30
FFFF84H
ICR09
0000B9H
8/16-bit PPG 8/9
N/A
# 31
FFFF80H
Output Compare 2
*1
# 32
FFFF7CH
ICR10
0000BAH
Input Capture 3
*1
# 33
FFFF78H
N/A
# 34
FFFF74H
ICR11
0000BBH
Output Compare 3
*1
# 35
FFFF70H
16-bit Reload Timer 1
*1
# 36
FFFF6CH
ICR12
0000BCH
UART 0 RX
*2
# 37
FFFF68H
UART 0 TX
*1
# 38
FFFF64H
ICR13
0000BDH
UART 1 RX
*2
# 39
FFFF60H
UART 1 TX
*1
# 40
FFFF5CH
ICR14
0000BEH
Flash Memory
N/A
# 41
FFFF58H
Delayed interrupt
N/A
# 42
FFFF54H
ICR15
0000BFH
Interrupt source
External Interrupt (INT0/INT1)
Time Base Timer
Output Compare 0
8/16-bit PPG 2/3
Output Compare 1
8/16-bit PPG A/B
30
DS07-13705-7E
MB90595G Series
*1: The interrupt request flag is cleared by the EI2OS interrupt clear signal.
*2: The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available.
N/A:The interrupt request flag is not cleared by the EI2OS interrupt clear signal.
Notes: • For a peripheral module with two interrupt for a single interrupt number, both interrupt request flags
are cleared by the EI2OS interrupt clear signal.
• At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same
interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by
hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the
first event. So it is recommended not to use the EI2OS for this interrupt number.
• If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control
register (ICR) is asserted. This means that different interrupt sources share the same EI2OS Descriptor
which should be unique for each interrupt source. For this reason, when one interrupt source uses the
EI2OS, the other interrupt should be disabled.
DS07-13705-7E
31
MB90595G Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Power supply voltage
Input voltage
Output voltage
Maximum Clamp Current
Maximum Total Clamp Current
“L” level Max. output current
“L” level Avg. output current
“L” level Max. output current
“L” level Avg. output current
“L” level Max. overall output current
“L” level Max. overall output current
“L” level Avg. overall output current
“L” level Avg. overall output current
“H” level Max. output current
“H” level Avg. output current
“H” level Max. output current
“H” level Avg. output current
“H” level Max. overall output current
“H” level Max. overall output current
“H” level Avg. overall output current
“H” level Avg. overall output current
Power consumption
Operating temperature
Storage temperature
(VSS = AVSS = 0.0 V)
Rating
Symbol
Unit
Remarks
Min
Max
VCC
VSS − 0.3 VSS + 6.0 V
AVCC VSS − 0.3 VSS + 6.0 V VCC = AVCC
*1
AVRH,
AVCC ≥ AVRH/L,
VSS − 0.3 VSS + 6.0 V
AVRL
AVRH ≥ AVRL
*1
DVCC VSS − 0.3 VSS + 6.0 V VCC ≥ DVCC
VI
VSS − 0.3 VSS + 6.0 V
*2
VO
VSS − 0.3 VSS + 6.0 V
*2
ICLAMP
−2.0
2.0
mA *6
∑⎜ICLAMP⎜
⎯
20
mA *6
IOL1
—
15
mA Normal output
*3
IOLAV1
—
4
mA Normal output, average value
*4
IOL2
—
40
mA High current output
*3
IOLAV2
—
30
mA High current output, average value *4
∑IOL1
—
100
mA Total normal output
∑IOL2
—
330
mA Total high current output
*5
∑IOLAV1
—
50
mA Total normal output, average value
Total high current output, average
∑IOLAV2
—
250
mA
value
*5
IOH1
—
−15
mA Normal output
*3
IOHAV1
—
−4
mA Normal output, average value
*4
IOH2
—
−40
mA High current output
*3
IOHAV2
—
−30
mA High current output, average value *4
∑IOH1
—
−100
mA Total normal output
∑IOH2
—
−330
mA Total high current output
*5
∑IOHAV1
—
−50
mA Total normal output, average value
Total high current output, average
∑IOHAV2
—
−250
mA
value
*5
—
500
mW MB90F598G
PD
—
400
mW MB90598G
TA
−40
+85
°C
TSTG
−55
+150
°C
*1: AVCC, AVRH, AVRL and DVCC shall not exceed VCC. AVRH and AVRL shall not exceed AVCC.
Also, AVRL shall never exceed AVRH.
*2: VI and VO should not exceed VCC + 0.3V. VI should not exceed the specified ratings. However if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI
rating.
*3: The maximum output current is a peak value for a corresponding pin.
*4: Average output current is an average current value observed for a 100 ms period for a corresponding pin.
*5: Total average current is an average current value observed for a 100 ms period for all corresponding pins.
(Continued)
32
DS07-13705-7E
MB90595G Series
(Continued)
*6: • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P77,
P80 to P87, P90 to P95
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is
provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on result.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input
pins, etc.) cannot accept +B signal input.
• Sample recommended circuits :
• Input/Output Equivalent circuits
Protective diode
VCC
+B input (0 V to 16 V)
Limiting
resistance
P-ch
N-ch
R
Note: Average output current = operating current × operating efficiency
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS07-13705-7E
33
MB90595G Series
2. Recommended Conditions
(VSS = AVSS = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min
Typ
Max
VCC
AVCC
4.5
5.0
5.5
V
Under normal operation
3.0
⎯
5.5
V
Maintains RAM data in stop mode
Smooth capacitor
CS
0.022
0.1
1.0
µF
*
Operating temperature
TA
–40
⎯
+85
°C
Power supply voltage
*: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to
be connected to the VCC pin must have a capacitance value higher than CS.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
• C Pin Connection Diagram
C
CS
34
DS07-13705-7E
MB90595G Series
3. DC Characteristics
Parameter
Symbol
VIHS
CMOS hysteresis
input pin
—
0.8 VCC
⎯
VCC
+0.3
V
VIHM
MD input pin
—
VCC –
0.3
⎯
VCC
+0.3
V
VILS
CMOS hysteresis
input pin
—
VSS –
0.3
⎯
0.2 VCC
V
VILM
MD input pin
—
VSS –
0.3
⎯
VSS
+0.3
V
Input H voltage
Input L voltage
Output H
voltage
Output L
voltage
Input leak
current
Pin name
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Condition
Unit Remarks
Min
Typ
Max
VOH1
Output pins except
P70 to P87
VCC = 4.5 V,
IOH1 = –4.0 mA
VCC –
0.5
—
—
V
VOH2
P70 to P87
VCC = 4.5 V,
IOH2 = –30.0 mA
VCC –
0.5
—
—
V
VOL1
Output pins except
P70 to P87
VCC = 4.5 V,
IOL1 = 4.0 mA
—
—
0.4
V
VOL2
P70 to P87
VCC = 4.5 V,
IOL2 = 30.0 mA
—
—
0.5
V
IIL
VCC = 5.5 V,
VSS < VI < VCC
–5
—
5
µA
—
35
60
mA MB90598G
ICC
VCC = 5.0 V±10%,
Internal frequency:
16 MHz,
At normal operating
—
40
60
mA MB90F598G
—
11
18
mA
—
0.3
0.6
mA
—
—
20
µA
—
—
20
µA
MB90598G
—
50
100
µA
MB90F598G
VCC = 5.0 V±10%,
Internal frequency:
ICCS
Power supply
current *
16 MHz,
At sleep
VCC
ICTS
VCC = 5.0 V±1%,
Internal frequency:
2 MHz,
At timer mode
ICCH
VCC = 5.0 V±10%,
At stop, TA = 25°C
ICCH2
VCC = 5.0 V±10%,
At Hardware standby mode,
TA = 25°C
(Continued)
DS07-13705-7E
35
MB90595G Series
(Continued)
Parameter
Input capacity
Symbol
CIN
Pin name
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Condition
Unit Remarks
Min
Typ
Max
Other than C, AVCC,
AVSS, AVRH, AVRL,
VCC, VSS, DVCC,
DVSS, P70 to P87
—
—
5
15
pF
P70 to P87
—
—
15
30
pF
Pull-up
resistance
RUP
RST
—
25
50
100
kΩ
Pull-down
resistance
RDOWN
MD2
—
25
50
100
kΩ
* : The power supply current testing conditions are when using the external clock.
36
DS07-13705-7E
MB90595G Series
4. AC Characteristics
(1) Clock Timing
Parameter
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name
Unit
Remarks
Min
Typ
Max
Oscillation frequency
fC
X0, X1
3
—
5
Oscillation cycle time
tCYL
X0, X1
200
—
333
External clock frequency
fC
X0, X1
3
—
16
External clock cycle time
tCYL
X0, X1
62.5
—
333
ns
Frequency deviation with
PLL *
∆f
—
—
—
5
%
PWH, PWL
X0
10
—
—
ns
Duty ratio is about 30 to 70%.
tCR, tCF
X0
—
—
5
ns
When using external clock
Machine clock frequency
fCP
—
1.5
—
16
MHz
Machine clock cycle time
tCP
—
62.5
—
666
ns
Flash Read cycle time
tCYL
—
—
2*tCP
—
ns
Input clock pulse width
Input clock rise and fall time
MHz When using oscillation circuit
ns
When using oscillation circuit
MHz When using external clock
When using external clock
When Flash is accessed via CPU
*: Frequency deviation indicates the maximum frequency difference from the target frequency when using a multiplied clock.
α
∆f = ------ × 100%
fo
+α
Central frequency fO
−α
• Clock Timing
tCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tCF
tCR
• Example of Oscillation circuit
X0
X1
R
C1
DS07-13705-7E
C2
37
MB90595G Series
• Guaranteed operation range
Guaranteed operation range
5.5
4.5
Power supply voltage
VCC (V)
Guaranteed PLL operation range
3.0
1.5
8
Machine clock fCP (MHz)
16
• Oscillation frequency and machine clock frequency
×4
16
×3
×1
×2
12
Machine clock
fCP (MHz)
9
8
×1/2
(PLL off)
4
3
4
8
Oscillation frequency fC (MHz)
16
AC characteristics are set to the measured reference voltage values below.
• Input signal waveform
Hysteresis Input Pin
0.8 VCC
0.2 VCC
38
• Output signal waveform
Output Pin
2.4 V
0.8 V
DS07-13705-7E
MB90595G Series
(2) Reset and Hardware Standby Input
Parameter
Symbol Pin name
Reset input time
tRSTL
Hardware standby input time
tHSTL
RST
HST
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Unit
Remarks
Min
Max
16 tCP*1
—
ns
Under normal operation
Oscillation time of
oscillator*2 + 16 tCP*1
—
ms
In stop mode
16 tCP*1
—
ns
Under normal operation
Oscillation time of
oscillator*2 + 16 tCP*1
—
ms
In stop mode
*1: “tcp” represents one cycle time of the machine clock.
No reset can fully initialize the Flash Memory if it is performing the automatic algorithm.
*2: Oscillation time of oscillator is time that the amplitude reached the 90%.
In the crystal oscillator, the oscillation time is between several ms to tens of ms. In ceramic oscillator, the oscillation
time is between hundreds of µs to several ms. In the external clock, the oscillation time is 0 ms.
Under Normal Operation
tRSTL, tHSTL
RST
HST
0.2 VCC
0.2 VCC
In Stop Mode
tRSTL, tHSTL
RST
HST
0.2VCC
0.2VCC
90% of
amplitude
X0
Internal operation clock
16 tCP
Oscillation time of
oscillator
Oscillation setting time
Instruction execution
Internal reset
DS07-13705-7E
39
MB90595G Series
(3)Power On Reset
Parameter
Power on rise time
Power off time
Symbol
Pin name
tR
VCC
tOFF
VCC
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Condition
Unit
Remarks
Min Max
—
0.05
30
ms
*
50
—
ms
Due to repetitive operation
*: VCC must be kept lower than 0.2 V before power-on.
Notes: • The above values are used for creating a power-on reset.
• Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn on
the power supply using the above values.
tR
2.7 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to
raise the voltage smoothly to suppress fluctuations as shown below.
In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1
V or less per second, however, you can use the PLL clock.
VCC
3V
RAM data being held
It is recommended to keep the
rising speed of the supply voltage
at 50 mV/ms or slower.
VSS
40
DS07-13705-7E
MB90595G Series
(4) UART0/1, Serial I/O Timing
Parameter
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Pin name
Condition
Unit Remarks
Min Max
Symbol
Serial clock cycle time
tSCYC
SCK ↓ ⇒ SOT delay time
tSLOV
Valid SIN ⇒ SCK ↑
tIVSH
SCK ↑ ⇒ Valid SIN hold time
tSHIX
Serial clock “H” pulse width
8 tCP
—
ns
–80
80
ns
100
—
ns
SCK0 to SCK2,
SIN0 to SIN2
60
—
ns
tSHSL
SCK0 to SCK2
4 tCP
—
ns
Serial clock “L” pulse width
tSLSH
SCK0 to SCK2
4 tCP
—
ns
SCK ↓ ⇒ SOT delay time
tSLOV
—
150
ns
Valid SIN ⇒ SCK ↑
tIVSH
60
—
ns
SCK ↑ ⇒ Valid SIN hold time
tSHIX
60
—
ns
SCK0 to SCK2
SCK0 to SCK2,
SOT0 to SOT2 Internal clock operSCK0 to SCK2, ation output pins are
SIN0 to SIN2 CL = 80 pF + 1 TTL.
SCK0 to SCK2,
External clock operSOT0 to SOT2
ation output pins are
SCK0 to SCK2, CL = 80 pF + 1 TTL.
SIN0 to SIN2
SCK0 to SCK2,
SIN0 to SIN2
Notes: • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
• tcp (external operation clock cycle time) : see (1) Clock timing.
• Internal Shift Clock Mode
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
SOT
2.4 V
0.8 V
tIVSH
SIN
DS07-13705-7E
0.8 VCC
0.2 VCC
tSHIX
0.8 VCC
0.2 VCC
41
MB90595G Series
• External Shift Clock Mode
tSLSH
tSHSL
0.8 VCC
SCK
0.8 VCC
0.2 VCC 0.2 VCC
tSLOV
2.4 V
0.8 V
SOT
tIVSH
tSHIX
0.8 VCC
0.2 VCC
SIN
0.8 VCC
0.2 VCC
(5) Timer Input Timing
Parameter
Input pulse width
Symbol
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Pin name
Condition
Unit
Remarks
Min
Max
tTIWH
TIN0, TIN1
tTIWL
IN0 to IN3
—
4 tCP
—
ns
• Timer Input Timing
0.8 VCC
0.8 VCC
0.2 VCC
tTIWH
42
0.2 VCC
tTIWL
DS07-13705-7E
MB90595G Series
(6) Trigger Input Timing
Parameter
Symbol
Pin name
tTRGH
tTRGL
INT0 to
INT7, ADTG
Input pulse width
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Condition
Unit
Remarks
Min
Max
—
5 tCP
—
ns
Under normal operation
1
—
µs
In stop mode
• Trigger Input Timing
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tTRGH
tTRGL
(7) Slew Rate High Current Outputs (MB90598G, MB90F598G only)
(VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter
Symbol
Pin name
Condition
Unit
Remarks
Min
Typ
Max
Output Rise/Fall time
Port P70 to P77,
Port P80 to P87
tR2
tF2
—
15
40
150
ns
• Slew Rate Output Timing
VH
VH
VL
VL
tR2
DS07-13705-7E
VH = VOL2 + 0.1 × (VOH2 − VOL2)
VL = VOL2 + 0.9 × (VOH2 − VOL2)
tF2
43
MB90595G Series
5. A/D Converter
(VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V,3.0 V ≤ AVRH − AVRL, TA = −40 °C to +85 °C)
Value
SymRemarks
Pin name
Unit
Parameter
bol
Min
Typ
Max
Resolution
—
—
—
10
bit
Conversion error
—
—
—
—
±5.0
LSB
Nonlinearity error
—
—
—
—
±2.5
LSB
Differential linearity error
—
—
—
—
±1.9
LSB
Zero transition voltage
VOT
AN0 to AN7
AVRL −
3.5 LSB
AVRL +
0.5 LSB
AVRL +
4.5 LSB
V
Full scale transition voltage
VFST
AN0 to AN7
AVRH −
6.5 LSB
AVRH −
1.5 LSB
AVRH +
1.5 LSB
V
Conversion time
—
—
—
352tCP
—
ns
Sampling time
—
—
—
64tCP
—
ns
Analog port input current
IAIN
AN0 to AN7
−10
—
10
µA
Analog input voltage range
VAIN
AN0 to AN7
AVRL
—
AVRH
V
—
AVRH
AVRL + 3.0
—
AVCC
V
—
AVRL
0
—
AVRH − 3.0
V
IA
AVCC
—
5
—
mA
IAH
AVCC
—
—
5
µA
*
—
400
600
µA
MB90V595G,
MB90F598G
—
140
600
µA
MB90598G
*
Reference voltage range
Power supply current
Reference voltage current
Offset between input channels
IR
AVRH
IRH
AVRH
—
—
5
µA
—
AN0 to AN7
—
—
4
LSB
* : When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) when the CPU is stopped.
44
DS07-13705-7E
MB90595G Series
6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter
Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00
0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual
conversion characteristics
Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Total error: The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error/full-scale transition error and linearity error.
Total error
3FF
3FE
0.5 LSB
Actual conversion
value
Digital output
3FD
{1 LSB × (N – 1) + 0.5 LSB}
004
VNT
(measured value)
003
Actual conversion
characteristics
002
Theoretical
characteristics
001
0.5 LSB
AVRL
1 LSB = (Theoretical value)
AVRH – AVRL
1024
VOT (Theoretical value) = AVRL + 0.5 LSB[V]
Analog input
[V]
AVRH
Total error for digital output N =
VNT – {1 LSB × (N – 1) + 0.5 LSB}
[LSB]
1 LSB
VNT: Voltage at a transition of digital output from (N – 1) to N
VFST (Theoretical value) = AVRH – 1.5 LSB[V]
(Continued)
DS07-13705-7E
45
MB90595G Series
(Continued)
Linearity error
Differential linearity error
Theoretical characteristics
3FF
Actual conversion
value
{1 LSB × (N – 1)+ VOT}
3FE
N+1
Actual conversion value
VFST
(measured value)
Digital output
Digital output
3FD
VNT
004
Actual conversion
characteristics
003
N
V(N + 1)T
(measured value)
N–1
VNT (measured value)
002
Theoretical
characteristics
001
Actual conversion
value
N–2
VOT (measured value)
AVRL
Analog input
AVRH
AVRL
Analog input
AVRH
Linearity error of
VNT – {1 LSB × (N – 1) + VOT}
[LSB]
digital output N =
1 LSB
Differential linearity error
=
of digital N
1 LSB =
V(N + 1)T – VNT
– 1 LSB [LSB]
1 LSB
VFST – VOT
[V]
1022
VOT: Voltage at transition of digital output from “000H” to “001H”
VFST: Voltage at transition of digital output from “3FEH” to “3FFH”
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions,:
• Output impedance values of the external circuit of 15 kΩ or lower are recommended.
• When capacitors are connected to external pins, the capacitance of several thousand times the internal
capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor
and internal capacitor.
When the output impedance of the external circuit is too high, the sampling period for analog voltages may not
be sufficient (sampling period = 4.00 µs @machine clock of 16 MHz).
• Equipment of analog input circuit model
Analog input
Comparator
3.2 kΩ Max
30 pF Max
• Error
The smaller the | AVRH − AVRL |, the greater the error would become relatively.
46
DS07-13705-7E
MB90595G Series
8. Flash memory
• Erase and programming performance
Parameter
Condition
Sector erase time
Chip erase time
TA = +25 °C,
VCC = 5.0 V
Word (16-bit)
programming time
Erase/Program cycle
DS07-13705-7E
⎯
Value
Unit
Remarks
Min
Typ
Max
⎯
1
15
s
MB90F598G
Excludes 00H
programming prior erasure
⎯
5
⎯
s
MB90F598G
Excludes 00H
programming prior
⎯
16
3600
µs
MB90F598G
Excludes system-level
overhead
10000
⎯
⎯
cycle
47
MB90595G Series
■ EXAMPLE CHARACTERISTICS
• “H” Level Output Voltage
VOH1 – IOH1
5
(Vcc = 4.5 V, TA = +25˚C)
5
4.5
4.5
4
4
3.5
3.5
VOH2 [V]
VOH1 [V]
VOH2 – IOH2
(Vcc = 4.5 V, TA = +25˚C)
3
2.5
3
2.5
2
2
1.5
1.5
1
1
0.5
0.5
0
0
0.0
-2.0
-4.0
-6.0
-8.0
-10.0
0
-10
IOH1 [mA]
• “L” Level Input Voltage
500
VOL2 [mV]
VOL1 [mV]
-40
(Vcc = 4.5 V, TA = +25˚C)
600
(Vcc = 4.5 V, TA = +25˚C)
500
400
300
400
300
200
200
100
100
0
0.0
-30
VOL2 – IOL2
VOL1 – IOL1
600
-20
IOH2 [mA]
2.0
4.0
8.0
6.0
0
10.0
IOL1 [mA]
0
10
20
30
40
IOL2 [mA]
• “H” Level Input Voltage/“L” Level Input Voltage
(Hysteresis Input)
VIN – VCC
(TA = +25˚C)
5
4
VIN [V]
VIH
3
VIL
2
1
0
3
4
5
6
Vcc [V]
48
DS07-13705-7E
MB90595G Series
• Supply Current
ICCS – VCC
ICC – VCC
(TA = +25˚C)
45
fcp = 16 MHz
40
fcp = 16 MHz
fcp = 12 MHz
30
25
fcp = 8 MHz
ICCS [mA]
14
35
ICC [mA]
(TA = +25˚C)
16
12
fcp = 12 MHz
10
8
fcp = 8 MHz
20
6
15
fcp = 4 MHz
4
fcp = 2 MHz
2
10
5
0
fcp = 4 MHz
fcp = 2 MHz
0
2.0
3.0
4.0
5.0
6.0
2.0
7.0
4.0
5.0
6.0
VCC [V]
ICTS – VCC
ICCH – VCC
(fcp = f2 MHz, TA = +25˚C)
600
3.0
VCC [V]
7.0
(TA = +25˚C)
20
18
500
400
ICCT [µA]
ICTS [µA]
16
300
14
12
10
8
200
6
100
4
2
0
2.0
3.0
4.0
5.0
6.0
7.0
VCC [V]
0
2.0
3.0
4.0
5.0
6.0
7.0
VCC [V]
ICCT2 – VCC
(MB90F598G only, TA = 25˚C)
100
90
ICCT2 [µA]
80
70
60
50
40
30
20
10
0
2.0
3.0
4.0
5.0
6.0
7.0
Vcc [V]
DS07-13705-7E
49
MB90595G Series
■ ORDERING INFORMATION
Part number
Package
MB90598GPF
MB90F598GPF
100-pin Plastic QFP
(FPT-100P-M06)
MB90V595GCR
256-pin Ceramic PGA
(PGA-256C-A01)
50
Remarks
For evaluation
DS07-13705-7E
MB90595G Series
■ PACKAGE DIMENSIONS
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP100-14×20-0.65
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
50
81
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8˚
31
100
1
30
0.65(.026)
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
"A"
©2002-2008
FUJITSU MICROELECTRONICS LIMITED F100008S-c-5-6
C
2002 FUJITSU LIMITED F100008S-c-5-5
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-13705-7E
51
MB90595G Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
Change Results
⎯
⎯
Deleted the old products, MB90598, MB90F598, and
MB90V595.
⎯
⎯
Changed the series name;
MB90595/595G series → MB90595G series
⎯
⎯
Changed the following erroneous name.
I/O timer → 16-bit Free-run Timer
5
■ PRODUCT LINEUP
One of Standby mode name is changed.
Clock mode → Watch mode
11
■ I/O CIRCUIT TYPE
Changed Pull-down resistor value of circuit type H.
50 Ω → 50 kΩ
37
39
44
■ ELECTRICAL CHARACTERISTICS Add the “External clock input” and “Flash Read cycle time” in
4. AC Characteristics
(1) Clock Timing
Figure in (2) Reset and Hardware Standby Input
RST/HST input level of “In Stop Mode” is changed.
0.6 VCC → 0.2 VCC
■ ELECTRICAL CHARACTERISTICS Changed the items of “Zero transition voltage” and “Full scale
5. A/D Converter
transition voltage”.
The vertical lines marked in the left side of the page show the changes.
52
DS07-13705-7E
MB90595G Series
MEMO
DS07-13705-7E
53
MB90595G Series
MEMO
54
DS07-13705-7E
MB90595G Series
MEMO
DS07-13705-7E
55
MB90595G Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
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property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
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system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
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The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
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