ICS853001 Integrated Circuit Systems, Inc. 1:1, DIFFERENTIAL LVPECL-TO2.5V, 3.3V, 5V LVPECL/ECL BUFFER GENERAL DESCRIPTION FEATURES The ICS853001 is a 1:1 Differential LVPECLto-LVPE C L B u f fe r a n d a m e m b e r o f t h e HiPerClockS™ HiPerClock S ™ family of High Perfor mance Clock Solutions from ICS. The ICS853001 may be used to regenerate LVPECL clocks which may have been attenuated, across a long trace, or may also be used as a differential-to-LVPECL translator. The differential input can accept the following differential input types: LVPECL, LVDS and CML. The device also has an output enable pin for debug/test purposes. When the output is disabled, it drives differential LOW (Q = LOW, nQ = HIGH). The ICS853001 is packaged in either a 3mm x 3mm 8-pin TSSOP or 3.9mm x 4.9mm 8-pin SOIC, making it ideal for use on space-constrained boards. • 1:1 Differential LVPECL-to-LVPECL / ECL buffer ICS • 1 LVPECL clock output pair • 1 Differential LVPECL PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output frequency: >2.5GHz • Part-to-part skew: 100ps (maximum) • Propagation delay: 500ps (maximum) • Additive phase jitter, RMS: 0.03ps (typical) • LVPECL mode operating voltage supply range: VCC = 2.375V to 5.25V, VEE = 0V • ECL mode operating voltage supply range: VCC = 0V, VEE = -5.25V to -2.375V • -40°C to 85°C ambient operating temperature • Lead-Free package RoHS compliant BLOCK DIAGRAM OE PIN ASSIGNMENT D Q VCC Q nQ VEE LE Q nPCLK 8 7 6 5 OE PCLK nPCLK VBB ICS853001 PCLK nQ 1 2 3 4 8-Lead TSSOP, 118 mil 3mm x 3mm x 0.95mm package body G Package Top View V BB ICS853001 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View 853001AG www.icst.com/products/hiperclocks.html 1 REV. A JANUARY 29, 2005 ICS853001 Integrated Circuit Systems, Inc. 1:1, DIFFERENTIAL LVPECL-TO2.5V, 3.3V, 5V LVPECL/ECL BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VCC Power Positive supply pin. 2, 3 Q, nQ Output Differential output pair. LVPECL interface levels. 4 VEE Power Negative supply pin. 5 6 7 8 NOTE: Type Description Nominal bias voltage at VCC - 1.38V. Pullup/ Inver ting differential LVPECL clock input. VCC/2 default when left nPCLK Input Pulldown floating. Can accept LVPECL, LVDS, CML interface levels. Non-inver ting differential LVPECL clock input. PCLK Input Pulldown Can accept LVPECL, LVDS, CML interface levels. Active HIGH output enable. When logic HIGH, the output is enabled and follows the input clock. When logic LOW, the output drives logic OE Input Pullup low (Q=LOW, nQ=HIGH). LVCMOS/LVTTL interface levels. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. VBB Output TABLE 2. PIN CHARACTERISTICS Symbol Parameter RPULLDOWN Input Pulldown Resistor 37.5 KΩ RPULLUP Input Pullup Resistor 37.5 KΩ 853001AG Test Conditions www.icst.com/products/hiperclocks.html 2 Minimum Typical Maximum Units REV. A JANUARY 29, 2005 ICS853001 Integrated Circuit Systems, Inc. 1:1, DIFFERENTIAL LVPECL-TO2.5V, 3.3V, 5V LVPECL/ECL BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 6V (LVPECL mode, VEE = 0) Negative Supply Voltage, VEE -6V (ECL mode, VCC = 0) Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5 V Inputs, VI (ECL mode) 0.5V to VEE - 0.5V Outputs, IO Continuous Current Surge Current VBB Sink/Source, IBB NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those 50mA 100mA listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maxi- ± 0.5mA mum rating conditions for extended periods may affect product reliability. Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 8 Lead TSSOP 8 Lead SOIC 101.7°C/W (0 m/s) 112.7°C/W (0 lfpm) (Junction-to-Ambient) TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 5.25V; VEE = 0V, TA = -40°C TO 85°C Symbol Parameter VCC Positive Supply Voltage Test Conditions I EE Power Supply Current Minimum Typical Maximum Units 2.375 3.3 5.25 V 27 mA Maximum Units TABLE 3B. LVCMOS DC CHARACTERISTICS, VCC = 2.375V TO 5.25V; VEE = 0V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage OE 0.7VCC VCC + 0.3 V VIL Input Low Voltage OE -0.3 0.3VCC V IIH Input High Current OE VCC = VIN 150 µA IIL Input Low Current OE VCC = VIN -150 µA TABLE 3C. LVCMOS DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V, TA = -40°C TO 85°C Symbol Parameter Maximum Units VIH Input High Voltage OE 0.3VEE 0.3 V VIL Input Low Voltage OE VEE - 0.3 0.7VEE V IIH Input High Current OE VCC = VIN 150 µA IIL Input Low Current OE VCC = VIN 853001AG Test Conditions Minimum www.icst.com/products/hiperclocks.html 3 -150 Typical µA REV. A JANUARY 29, 2005 ICS853001 Integrated Circuit Systems, Inc. 1:1, DIFFERENTIAL LVPECL-TO2.5V, 3.3V, 5V LVPECL/ECL BUFFER TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 5.25V; VEE = 0V, TA = -40°C TO 85°C Symbol Parameter Maximum Units PCLK Test Conditions VCC = VIN 200 µA nPCLK VCC = VIN 200 µA IIH Input High Current IIL Input Low Current V PP Peak-to-Peak Input Voltage Minimum Typical PCLK VCC = 5.25, VIN = 0V -200 µA nPCLK VCC = 5.25V, VIN = 0V -200 µA 0.15 1.2 1.2 V VCC V VCMR Common Mode Input Voltage; NOTE 1, 2 VOH Output High Voltage; NOTE 3 VCC - 1.005 V VOL Output Low Voltage; NOTE 3 VCC - 1.78 V VSWING Peak-to-Peak Output Voltage Swing 0.6 Bias Voltage VCC - 1.44 VCC - 1.38 V BB NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. NOTE 3: Outputs terminated with 50Ω to VCC - 2V. TABLE 4. AC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V Symbol Parameter Output Frequency t PD Propagation Delay; NOTE 1 tsk(pp) Par t-to-Par t Skew; NOTE 2, 3 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time t R / tF odc Output Duty Cycle V VCC - 1.32 V VCC = 2.375 TO 5.25V; VEE = 0V, TA = -40°C TO 85°C Test Conditions fMAX tjit OR 1. 0 Minimum Typical Maximum Units >2.5 GHz 500 ps 100 ps 250 155.52MHz, Integration Range: 12KHz - 20MHz 20% to 80% 50 250 ps VCC = 2.375V to 3.6V, VEE = 0 48 52 % 54 % ƒ≤ 1GHz 0.03 ps VCC > 3.6V to 5.25V, VEE = 0 or 46 VEE = -5.25V to -3.6V,VCC = 0 All parameters are measured at ƒ ≤ 1.7GHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 853001AG www.icst.com/products/hiperclocks.html 4 REV. A JANUARY 29, 2005 ICS853001 Integrated Circuit Systems, Inc. 1:1, DIFFERENTIAL LVPECL-TO2.5V, 3.3V, 5V LVPECL/ECL BUFFER ADDITIVE PHASE JITTER the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 Additive Phase Jitter, RMS -20 @ 155.52MHz (12KHz to 20MHz) = 0.03ps typical -30 -40 -50 SSB PHASE NOISE dBc/HZ -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- 853001AG vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. www.icst.com/products/hiperclocks.html 5 REV. A JANUARY 29, 2005 ICS853001 Integrated Circuit Systems, Inc. 1:1, DIFFERENTIAL LVPECL-TO2.5V, 3.3V, 5V LVPECL/ECL BUFFER PARAMETER MEASUREMENT INFORMATION 2V VCC Qx VCC SCOPE nPCLK LVPECL V V Cross Points PP CMR PCLK nQx VEE V EE -3.25V to -0.375V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 Qx nPCLK nQy nQ PCLK PART 2 Qy Q tPD t sk(pp) PART-TO-PART SKEW PROPAGATION DELAY nQ 80% 80% Q VSW I N G Clock Outputs Pulse Width 20% 20% tR t PERIOD tF odc = t PW t PERIOD OUTPUT RISE/FALL TIME 853001AG OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD www.icst.com/products/hiperclocks.html 6 REV. A JANUARY 29, 2005 ICS853001 Integrated Circuit Systems, Inc. 1:1, DIFFERENTIAL LVPECL-TO2.5V, 3.3V, 5V LVPECL/ECL BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS Figure 1A shows an example of the differential input that can be wired to accept single ended LVCMOS levels. The reference voltage level VBB generated from the device is connected to the negative input. The C1 capacitor should be located as close as possible to the input pin. VCC R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 1A. SINGLE ENDED LVCMOS SIGNAL DRIVING DIFFERENTIAL INPUT WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS Figure 1B shows an example of the differential input that can be wired to accept single ended LVPECL levels. The reference voltage level VBB generated from the device is connected to the negative input. VCC C1 0.1u CLK_IN PCLK VBB nPCLK FIGURE 1B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT 853001AG www.icst.com/products/hiperclocks.html 7 REV. A JANUARY 29, 2005 ICS853001 Integrated Circuit Systems, Inc. 1:1, DIFFERENTIAL LVPECL-TO2.5V, 3.3V, 5V LVPECL/ECL BUFFER TERMINATION FOR 2.5V LVPECL OUTPUT Figure 2A and Figure 2B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 2B can be eliminated and the termination is shown in Figure 2C. 2.5V VCC=2.5V 2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm R3 250 + Zo = 50 Ohm + Zo = 50 Ohm - Zo = 50 Ohm 2,5V LVPECL Driv er - R1 50 2,5V LVPECL Driv er R2 62.5 R2 50 R4 62.5 R3 18 FIGURE 2B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 2A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm - 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 2C. 2.5V LVPECL TERMINATION EXAMPLE 853001AG www.icst.com/products/hiperclocks.html 8 REV. A JANUARY 29, 2005 ICS853001 Integrated Circuit Systems, Inc. 1:1, DIFFERENTIAL LVPECL-TO2.5V, 3.3V, 5V LVPECL/ECL BUFFER TERMINATION FOR 3.3V LVPECL OUTPUTS 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT FIN 125Ω Zo = 50Ω Zo = 50Ω FOUT 50Ω FIN 50Ω Zo = 50Ω VCC - 2V 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION TERMINATION FOR 5V LVPECL OUTPUT This section shows examples of 5V LVPECL output termination. Figure 4A shows standard termination for 5V LVPECL. The termination requires matched load of 50Ω resistors pull down to VCC - 2V = 3V at the receiver. Figure 4B shows Thevenin equivalence of Figure 4A. In actual application where the 3V DC power supply is not available, this approached is normally used. 5V 5V 5V 5V R3 84 PECL PECL Zo = 50 Ohm R4 84 Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - R1 50 - PECL R1 125 R2 50 PECL R2 125 3V FIGURE 4A. STANDARD 5V PECL OUTPUT TERMINATION 853001AG FIGURE 4B. 5V PECL OUTPUT TERMINATION EXAMPLE www.icst.com/products/hiperclocks.html 9 REV. A JANUARY 29, 2005 ICS853001 Integrated Circuit Systems, Inc. 1:1, DIFFERENTIAL LVPECL-TO2.5V, 3.3V, 5V LVPECL/ECL BUFFER LVPECL CLOCK INPUT INTERFACE here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested 3.3V 3.3V 3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm R2 50 Zo = 50 Ohm PCLK R1 100 Zo = 50 Ohm nPCLK PCLK nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK HiPerClockS PCLK/nPCLK CML Built-In Pullup FIGURE 5A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER FIGURE 5B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 PCLK PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 VBB nPCLK HiPerClockS Input PC L K/n PC LK R5 100 - 200 R2 84 FIGURE 5C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER R2 50 R1 50 R6 100 - 200 FIGURE 5D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 2.5V 3.3V 3.3V 3.3V 2.5V R3 120 SSTL Zo = 50 Ohm R4 120 C1 LVDS Zo = 60 Ohm PCLK PCLK R5 100 Zo = 60 Ohm nPCLK R1 120 nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK PC L K/n PC L K R1 1K R2 120 FIGURE 5E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER 853001AG VBB C2 FIGURE 5F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER www.icst.com/products/hiperclocks.html 10 R2 1K REV. A JANUARY 29, 2005 ICS853001 Integrated Circuit Systems, Inc. 1:1, DIFFERENTIAL LVPECL-TO2.5V, 3.3V, 5V LVPECL/ECL BUFFER APPLICATION SCHEMATIC EXAMPLE one termination example is shown in this schematic. For more termination approaches, please refer to the LVPECL Termination Application Note. Figure 6 shows an example of ICS853001 application schematic. In this example, the device is operated at VCC = 3.3V. The decoupling capacitor should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver. Only VCC VCC VCC R7 133 R5 133 U1 R3 133 ICS853001 Zo = 50 Ohm 5 6 7 8 Zo = 50 Ohm VEE nQ Q VCC VBB nPCLK PCLK OE 4 3 2 1 - VCC Zo = 50 Ohm + C5 0.1u LVPECL R8 82.5 R1 133 Zo = 50 Ohm R6 82.5 R4 82.5 R2 82.5 VCC=3.3V FIGURE 6. APPLICATION SCHEMATIC EXAMPLE 853001AG www.icst.com/products/hiperclocks.html 11 REV. A JANUARY 29, 2005 ICS853001 Integrated Circuit Systems, Inc. 1:1, DIFFERENTIAL LVPECL-TO2.5V, 3.3V, 5V LVPECL/ECL BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS853001. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853001 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 5V + 5% = 5.25V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * ICC_MAX = 5.25V * 27mA = 141.75mW Power (outputs)MAX = 27.83mW/Loaded Output pair Total Power_MAX (3.465V) = 141.75mW + 27.83mW = 169.58mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 5A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.170W * 90.5°C/W = 100.4°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 5A. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 101.7°C/W 90.5°C/W 2 89.8°C/W TABLE 5B. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 853001AG www.icst.com/products/hiperclocks.html 12 REV. A JANUARY 29, 2005 ICS853001 Integrated Circuit Systems, Inc. 1:1, DIFFERENTIAL LVPECL-TO2.5V, 3.3V, 5V LVPECL/ECL BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CC_MAX • – 1.005V OH_MAX OL_MAX CC_MAX CC_MAX ) = 1.005 -V For logic low, VOUT = V (V =V -V OL_MAX =V CC_MAX – 1.78V ) = 1.78V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CC_MAX - 2V))/R ] * (V CC_MAX L -V OH_MAX ) = [(2V - (V CC_MAX -V OH_MAX ))/R ] * (V CC_MAX L -V OH_MAX )= [(2V - 1.005V)/50Ω] * 1.005V = 20mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.78V)/50Ω] * 1.78V = 7.83mW Total Power Dissipation per output pair = Pd_H + Pd_L = 27.83mW 853001AG www.icst.com/products/hiperclocks.html 13 REV. A JANUARY 29, 2005 ICS853001 Integrated Circuit Systems, Inc. 1:1, DIFFERENTIAL LVPECL-TO2.5V, 3.3V, 5V LVPECL/ECL BUFFER RELIABILITY INFORMATION TABLE 6A θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 101.7°C/W 90.5°C/W 2 89.8°C/W TABLE 6B. θJAVS. AIR FLOW TABLE 8 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS853001 is: 141 853001AG www.icst.com/products/hiperclocks.html 14 REV. A JANUARY 29, 2005 ICS853001 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX 1:1, DIFFERENTIAL LVPECL-TO2.5V, 3.3V, 5V LVPECL/ECL BUFFER FOR 8 LEAD TSSOP PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC TABLE 7A. PACKAGE DIMENSIONS SYMBOL TABLE 7B. PACKAGE DIMENSIONS Minimum N SYMBOL Maximum 8 -- 1.10 A A1 0 0.15 A2 0.79 0.97 b 0.22 0.38 c 0.08 0.23 D 3.00 BASIC E 4.90 BASIC E1 3.00 BASIC e 0.65 BASIC e1 1.95 BASIC α aaa 0.40 0° -- MINIMUN N A L Millimeters Millimeters MAXIMUM 8 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BASIC H 5.80 6.20 h 0.25 0.50 0.80 L 0.40 1.27 8° α 0° 8° Reference Document: JEDEC Publication 95, MS-012 0.10 Reference Document: JEDEC Publication 95, MO-187 853001AG www.icst.com/products/hiperclocks.html 15 REV. A JANUARY 29, 2005 ICS853001 Integrated Circuit Systems, Inc. 1:1, DIFFERENTIAL LVPECL-TO2.5V, 3.3V, 5V LVPECL/ECL BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS853001AG 001A 8 lead TSSOP tube -40°C to 85°C ICS853001AGT 001A 8 lead TSSOP 2500 tape & reel -40°C to 85°C ICS853001AGLF 01AL 8 lead "Lead-Free" TSSOP tube -40°C to 85°C ICS853001AGLFT 01AL 8 lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C ICS853001AM 853001A 8 lead SOIC tube -40°C to 85°C ICS853001AMT 853001A 8 lead SOIC 2500 tape & reel -40°C to 85°C ICS853001AMLF 853001AL 8 lead "Lead-Free" SOIC tube -40°C to 85°C ICS853001AMLFT 853001AL 8 lead "Lead-Free" SOIC 2500 tape & reel -40°C to 85°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853001AG www.icst.com/products/hiperclocks.html 16 REV. A JANUARY 29, 2005