INFINEON TLE4946-2L

June 2008
TLE4946-2L
High Precision Hall Effect Latch
TLE4946-2L
Datasheet
Rev 1.0
Sensors
Edition 2008-06
Published by
Infineon Technologies AG
81726 München, Germany
© 2007 Infineon Technologies AG
All Rights Reserved.
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TLE4946-2L
TLE4946-2L High Precision Hall Effect Latch
Revision History: 2008-06, Rev 1.0
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Datasheet
3
Rev 1.0, 2008-06
TLE4946-2L
1
1.1
1.2
1.3
Product Description 5
Overview 5
Features 5
Target Applications 5
2
2.1
2.2
2.3
2.4
2.5
2.6
Functional Description 5
General 5
Pin Configuration 6
Pin Description 6
Block Diagram 6
Operating Modes and States 7
Functional Block Description 7
3
3.1
3.2
3.3
3.4
Specification 8
Application Circuit 8
Absolute Maximum Ratings 8
Operating Range 9
Characteristics 9
4
4.1
Package Information 10
Package Outline 10
Datasheet
4
Rev 1.0, 2008-06
High Precision Hall Effect Latch
1
Product Description
1.1
Overview
TLE4946-2L
The TLE4946-2L is a high precision Hall effect latch
with highly accurate switching thresholds for operating
temperatures up to 150°C.
1.2
•
•
•
•
•
•
•
•
•
•
Features
2.7 V to 18 V supply voltage operation
Operation from unregulated power supply
High sensitivity and high stability of the magnetic switching points
High resistance to mechanical stress by active error compensation
Reverse battery protection (Vs = -18V)
Superior temperature stability
Peak temperatures up to 195°C without damage
Low jitter (typ. 1µs)
High ESD performance (± 4 kV HBM)
Digital output signal
1.3
Target Applications
The TLE4946-2L is an integrated circuit Hall-effect sensor with low switching thresholds and low hysteresis. It is
specially designed for high sensitivity applications and is ideally suited to detect the rotor position in a BLDC motor.
Also for index counting with small pole wheels and large air gaps the sensor provides a reliable switching
information.
2
Functional Description
2.1
General
Precise magnetic switching thresholds and high temperature stability are achieved by active compensation circuits
and chopper techniques on chip. Offset voltages, generated by temperature induced stress or overmolding are
canceled and high accuracy is achieved. The IC has an open collector output stage with 20mA current sink
capability. A wide operating voltage range form 2.7V to 18V with reverse polarity protection up to -18V makes the
device suitable for a wide range of applications. A magnetic south pole with field strength above Bop turns the
output on and a magnetic north pole exceeding Brp turns it off.
Product Name
Product Type
Ordering Code
Package
Hall Effect Latch
TLE4946-2L
SP000398352
PG-SSO-3-2
Datasheet
5
Rev 1.0, 2008-06
TLE4946-2L
Functional Description
2.2
Pin Configuration
Center of
Sensitive Area
2.08 ± 0.1
1.35 ± 0.1
1 2 3
PG-SSO-3-2
Figure 1
Pin Configuration and sensitive area (Top View, Figure not to Scale)
2.3
Pin Description
Table 1
Pin Description
Pin or Ball
No.
Name
Pin
Type
Function
1
Vs
I
Supply voltage
2
GND
O
Ground
3
Q
O
Output
2.4
Comments
Block Diagram
VS
Voltage Regulator
reverse polarity protected
Bias and
Compensation
Circuits
Oscillator
and
Sequencer
Q
Ref
Amplifier
Chopped
Hall Probe
Figure 2
Datasheet
Low
Pass
Filter
Comparator
with
Hysteresis
GND
TLE4946-2L Block Diagram
6
Rev 1.0, 2008-06
TLE4946-2L
Functional Description
2.5
Operating Modes and States
Field Direction Definition:
Positive magnetic fields are related with the south pole of the magnet to the branded side of package.
B OP
Applied
Magnetic
Field
B RP
td
td
tf
VQ
tr
90%
10%
Figure 3
Timing diagram
VQ
B
B rp
0
Figure 4
Output Signal
2.6
Functional Block Description
Bop
The chopped Hall IC switch comprises a Hall probe, bias generator, compensation circuits, oscillator and output
transistor.
The bias generator provides currents for the Hall probe and the active circuits. Compensation circuits stabilize the
temperature behavior and reduce technology variations.
The Active Error Compensation rejects offsets in signal stages and the influence of mechanical stress to the Hall
probe caused by molding and soldering processes and other thermal stresses in the package.
This chopper technique together with the threshold generator and the comparator ensure high accurate magnetic
switching points
Datasheet
7
Rev 1.0, 2008-06
TLE4946-2L
Specification
Figure 5
Q
Q
GND
VS
GND
1.2kΩ
Application Circuit
4.7nF
3.1
4.7nF
Specification
TLE4946-2L
3
200Ω
VS
Application circuit
It is recommended to use a serial resistor of 200Ω in the supply line for current limitation in the case of a
overvoltage pulse. Two capacitors of 4.7nF enhance the EMC performance. The pull-up resistor of 1.2kΩ limits
the current through the output transistor.
3.2
Absolute Maximum Ratings
Table 2
Absolute Maximum Ratings
Parameter
Symbol
Values
Unit
Note/Test Condition
Min.
Typ.
Max.
-40
–
150
–
–
155
for 2000 h (not
additive)
–
–
165
for 1000 h (not additive
–
–
175
for 168 h (not additive)
–
–
195
for 3 x 1 h (additive)
VDD
-18
-18
-18
–
–
–
18
24
26
V
Supply current through
protection device
IS
– 50
–
+ 50
mA
Output voltage
VQ
-0.7
–
18
V
-0.7
–
26
– 40
–
150
°C
–
unlimited
mT
Max. junction temperature
Supply voltage
TJ
Storage temperature
TS
Magnetic flux density
B
ESD robustness
HBM: 1.5 kΩ, 100 pF
VESD,HBM
Datasheet
4
°C
for 1h, Rs ≥ 200Ω
for 5min, Rs ≥ 200Ω
for 5min @ 1.2kΩ pull
up
kV
8
According to
EIA/JESD22-A114-B
Rev 1.0, 2008-06
TLE4946-2L
Specification
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
3.3
Operating Range
The following operating conditions must not be exceeded in order to ensure correct operation of the TLE4946-2L.
All parameters specified in the following sections refer to these operating conditions unless otherwise mentioned.
Table 3
Operating Range
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Supply voltage
VS
2.7
–
18
V
Output voltage
VQ
– 0.7
–
18
V
Junction temperature
Tj
– 40
–
150
°C
Output current
IQ
0
–
20
mA
3.4
Note/ Test Condition
Characteristics
Product characteristics involve the spread of values guaranteed within the specified voltage and ambient
temperature range. Typical characteristics are the median of the production (at Vs = 12V and TA= 25°C).
Table 4
Electrical Characteristics
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note/ Test Condition
Supply current
IS
2
4
6
mA
VS = 2.7 V ... 18 V
Reverse current
ISR
0
0.2
1
mA
VS = – 18 V
Output saturation voltage
VQSAT
–
0.3
0.6
V
IQ = 20 mA
Output leakage current
IQLEAK
–
0.05
10
µA
for VQ = 18 V
Output fall time
tf
–
0.02
1
µs
Output rise time
tr
–
0.4
1
µs
RL = 1.2 kΩ;
CL = 50 pF
Chopper frequency
fOSC
–
320
–
Switching frequency
Delay time
2)
Output jitter
3)
Power-on time 4)
Thermal resistance
5)
kHz
1)
fSW
0
–
15
kHz
td
–
13
–
µs
tQJ
–
1
–
µsRMS Typ. value for square
wave signal 1 kHz
tPON
–
13
–
µs
VS ≥ 2.7 V
RthJA
–
190
K/W
PG-SSO-3-2
1) To operate the sensor at the max. switching frequency, the value of the magnetic signal amplitude must be 1.4 times higher
than for static fields.
This is due to the - 3 dB corner frequency of the low pass filter in the signal path.
2) Systematic delay between magnetic threshold reached and output switching
3) Jitter is the unpredictable deviation of the output switching delay
4) Time from applying VS ≥ 2.7 V to the sensor until the output state is valid
5) Thermal resistance from junction to ambient
Datasheet
9
Rev 1.0, 2008-06
TLE4946-2L
Package Information
Table 5
Magnetic Characteristics
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Operate point
BOP
0.5
2.0
3.5
mT
Release point
BRP
BHYS
-3.5
-2.0
-0.5
mT
1.0
4
6.0
mT
BOFF
-1.5
0
1.5
mT
Hysteresis
1)
Magnetic Offset
Temperature compensation of
magn. thresholds
TC
-350
ppm/°C
Repeatability of magnetic
thresholds 2)
BREP
20
µTRMS
Note/ Test Condition
1) Boff = (Bop + Brp)/2
2) BREP is equivalent to the noise constant
4
Package Information
4.1
Package Outline
46 2
yww S
d
Year (y) = 0...9
Calendar Week (ww) = 01...52
Branded Side
Hall-Probe
d : Distance chip to upper side of IC
PG-SSO-3-2 : 0.57 ±0.08 mm
AEA03644
AEA02510-1
Figure 6
Datasheet
Marking of TLE4946-2L and Distance of chip to upper side of IC
10
Rev 1.0, 2008-06
TLE4946-2L
Package Information
0.8 ±0.1 x 45˚
7˚
0.2
2 A
1.52 ±0.05
1 MAX.1)
7˚
0.35 ±0.1 x 45˚
3.29 ±0.08
3 ±0.06
4.06 ±0.08
1.9 MAX.
(0.25)
0.15 MAX.
4.16 ±0.05
(0.79)
0.6 MAX.
0.2 +0.1
0.4 ±0.05
1.27±0.25
1
2
3
1.27±0.25
18 ±0.5
6 ±0.5
1-1
38 MAX.
9 +0.75
-0.5
23.8 ±0.5
12.7 ±1
A
Adhesive
Tape
Tape
6.35 ±0.4
1) No solder function area
Figure 7
Datasheet
4 ±0.3
12.7 ±0.3
Total tolerance at 10 pitches ±1
0.25 -0.15
0.39 ±0.1
GPO05358
Package outline
11
Rev 1.0, 2008-06
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