LTC3626 20V, 2.5A Synchronous Monolithic Step-Down Regulator with Current and Temperature Monitoring FEATURES DESCRIPTION 3.6V to 20V Input Voltage Range Wide Output Voltage Range of 0.6V to 97% VIN Optimized for 0.6V to 6V n Low R DS(ON) Integrated Switches Provide Up to 95% Efficiency n Up to 2.5A of Output Current n Average Input and Output Current Monitoring n Programmable Average Input/Output Current Limit n Die Temperature Monitor and Programmable Limit n Adjustable Switching Frequency: 500kHz to 3MHz n External Frequency Synchronization n Current Mode Operation for Excellent Line and Load Transient Response n0.6V Reference with 1% Accuracy Over Temperature n User Selectable Burst Mode® or Forced Continuous Operation n Short-Circuit Protected n Output Voltage Tracking Capability n Power Good Status Output n Available in Small, Thermally Enhanced, 20-Lead (3mm × 4mm) QFN Package The LTC®3626 is a high efficiency, monolithic synchronous buck regulator using a phase-lockable controlled on-time, current mode architecture capable of supplying up to 2.5A of output current. The operating supply voltage range is 3.6V to 20V, making it suitable for a wide range of power supply applications. n n APPLICATIONS Distributed Power Systems n Battery-Powered Instruments n Point-of-Load Power Supply The operating frequency is programmable from 500kHz to 3MHz with an external resistor allowing the use of small surface mount inductors. For applications sensitive to switching noise, the LTC3626 can be externally synchronized over the same frequency range. An internal phaselocked loop aligns the on-time of the top power MOSFET to the internal or external clock. This unique controlled on-time architecture is ideal for high step-down ratio applications that demand high switching frequencies and fast transient response. An internal phase lock loop servos the on-time of the internal one-shot timer to match the frequency of the internal clock or an applied external clock. The LTC3626 offers two operational modes: Burst Mode and forced continuous mode to allow the user to optimize output voltage ripple, noise and light load efficiency for a given application. L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 5994885. n TYPICAL APPLICATION 47µF 10 80 0.1µF 2.2µH VOUT 3.3V 47µF 2.5A 115k 22pF 25.5k 324k 3626 TA01 70 1 60 50 0.1 40 30 20 10 0 1 POWER LOSS (W) BOOST LTC3626 PGOOD INTVCC TRACK/SS SW 2.2µF ITH MODE/SYNC VON TSET IMONIN FB TMON RT IMONOUT SGND PGND 1µF 5.1k VOUT = 3.3V 90 PVIN SVIN RUN EFFICIENCY (%) VIN 3.6V TO 20V Efficiency vs Load Current 100 Burst Mode 0.01 OPERATION VIN = 12V VIN = 5V 0.001 10 100 1000 10000 3626 TA01b LOAD CURRENT (mA) 3626f 1 LTC3626 MODE/SYNC PGOOD SW TOP VIEW 20 19 18 17 BOOST 1 16 PVIN 15 PVIN INTVCC 2 VON 3 14 SVIN 21 PGND TSET 4 13 RUN TMON 5 12 RT SGND 6 11 ITH 9 10 FB 8 TRACK/SS 7 IMONOUT PVIN............................................................ –0.3V to 22V SVIN............................................................ –0.3V to 22V BOOST..................................................... –0.3V to 25.6V BOOST-SW................................................. –0.3V to 3.6V INTVCC....................................................... –0.3V to 3.6V ITH, RT, FB..................................–0.3V to INTVCC + 0.3V MODE/SYNC...............................–0.3V to INTVCC + 0.3V TRACK/SS, IMONIN, IMONOUT....–0.3V to INTVCC + 0.3V TSET, TMON...............................–0.3V to INTVCC + 0.3V SW, RUN........................................... –0.3V to VIN + 0.3V PGOOD........................................................ –0.3V to 22V VON............................................................. –0.3V to 18V SW Source Current (DC, Note 2)...............................2.5A Operating Junction Temperature Range (Notes 3, 4) ............................................ –40°C to 125°C Storage Temperature Range................... –65°C to 150°C PIN CONFIGURATION SW (Note 1) IMONIN ABSOLUTE MAXIMUM RATINGS UDC PACKAGE 20-LEAD (3mm × 4mm) PLASTIC QFN TJMAX = 125°C, θJA = 47°C/W EXPOSED PAD (PIN 21) IS PGND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3626EUDC#PBF LTC3626EUDC#TRPBF LGCC 20-Lead (3mm × 4mm) Plastic QFN –40°C to 125°C LTC3626IUDC#PBF LTC3626IUDC#TRPBF LGCC 20-Lead (3mm × 4mm) Plastic QFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3626f 2 LTC3626 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 3). PVIN = SVIN = 12V unless otherwise specified. SYMBOL PARAMETER PVIN Input Supply Range CONDITIONS l 3.0 20 V SVIN Input Supply Range l 3.6 20 V VVOUT Output Voltage Range (Note 5) VON = VOUT 0.6 6 V IQ Input DC Supply Current Forced Continuous Operation PVIN SVIN MODE = 0, RRT = 158k, IIN, IOUT, TMON, TSET = INTVCC 30 900 39 1200 µA µA 30 270 39 350 µA µA 0.01 13 2 17 µA µA 0.600 0.606 Sleep Current PVIN SVIN VFB > 0.6V, IIN, IOUT, TMON, TSET, MODE = INTVCC Shutdown PVIN SVIN ILOAD = 0A, VRUN = 0V MIN TYP MAX UNITS VFB Feedback Reference Voltage ∆VLINE(REG) VFB Line Regulation VVIN = 3.6V to 20V 0.01 %/V ∆VLOAD(REG) VFB Load Regulation ITH = 0.6V to 1.5V 0.1 % l 0.594 ±30 V Feedback Pin Input Current VFB = 0.6V Error Amplifier Transconductance ITH = 1.2V 1.5 tON(MIN) Minimum On-Time VVON =1V, VVIN = 3.6V 20 tOFF(MIN) Minimum Off-Time PVIN = SVIN = 6V 40 60 ns 2.4 2.9 3.6 A 1.4 1.7 2.5 2 2 3 2.6 2.3 3.5 MHz MHz MHz Valley Switch Current Limit fOSC Oscillator Frequency RDS(ON) Top Switch On-Resistance Bottom Switch On-Resistance IMONOUT Current (Note 6) VRT = INTVCC RRT = 158k RRT = 105k IOUT Limit Regulation Voltage IMONIN Current (Note 6) l ISW = 2.5A, 20% Duty Cycle ISW = 1.5A, 20% Duty Cycle ISW = 0.5A, 20% Duty Cycle IIN Limit Regulation Voltage VRUN l mΩ mΩ 148.5 89.1 29.7 156.25 93.75 31.25 164.0 98.4 33.5 µA µA µA 1.15 1.22 1.28 V 29.7 17.8 5.9 31.25 18.75 6.25 32.8 19.7 6.7 µA µA µA 1.15 1.22 1.28 V 1.5 V Internal Temperature Monitor Slope (Note 7) 200 °C/V Temperature Limit Hysteresis 50 mV Internal Temperature Monitor VINTVCC ns 115 70 ISW = 2.5A ISW = 1.5A ISW = 0.5A nA mS TA = 25°C PVIN Overvoltage Lockout Threshold PVIN Rising PVIN Falling 20 3.1 INTVCC Voltage 3.6V < VIN < 20V INTVCC Load Regulation (Note 8) IINTVCC = 0mA to 20mA RUN Threshold RUN Rising RUN Falling RUN Leakage Current PGOOD Good-to-Bad Threshold 21.5 20.5 3.3 V V 3.5 0.6 1.23 1.0 1.27 1.03 V V VVIN = 20V 0 ±1 μA FB Rising FB Falling 8 –8 10 –10 % % l l 1.19 0.97 V % 3626f 3 LTC3626 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 3). PVIN = SVIN = 12V unless otherwise specified. SYMBOL PARAMETER CONDITIONS PGOOD Bad-to-Good Threshold FB Rising FB Falling Power Good Filter Time MIN TYP MAX –3 3 –5 5 % % 20 40 μs PGOOD Pull-Down Resistance 10mA Load 20 Switch Leakage Current VRUN = 0V 0.01 1 tSS Internal Soft-Start Time VFB from 10% to 90% Full Scale 400 700 ITRACK/SS TRACK/SS Pull-Up Current RPGOOD Ω 1.4 MODE Threshold Voltage MODE VIH MODE VIL l l 1.0 SYNC Threshold Voltage SYNC VIH l 1.4 MODE Input Current MODE = 0V MODE = INTVCC Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Guaranteed by long term current density limitations. Note 3: The LTC3626 is tested under pulsed load conditions such that TJ ≈ TA. The LTC3626E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization, and correlation with statistical process controls. The LTC3626I is guaranteed over the –40°C to 125°C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance, and other environmental factors. UNITS μA μs μA 0.4 V V V –1.5 1.5 μA µA Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this protection is active. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. Note 5: Output voltages above 6V are not optimized for controlled on-time operation. Refer to the Applications Information section for further discussions related to the output voltage range. Verified at test by comparison of measured on-time to VON voltage. Note 6: Tested in a proprietary test mode, where ISW flows through the synchronous switch only. Note 7: Guaranteed by design. Note 8: Maximum allowed current draw when used as a regulated output is 5mA. This supply is only intended to supply additional DC load currents as needed and not intended to regulate large transient or AC behavior as these waveforms may impact LTC3626 operation. 3626f 4 LTC3626 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, PVIN = SVIN = 12V, f = 1MHz unless otherwise noted. Efficiency vs Load Current (Burst Mode Operation) 100 100 VOUT = 1.8V 90 100 80 70 70 50 40 30 VIN = 4V VIN = 8V VIN = 12V VIN = 20V 10 0 1 100 1000 10 LOAD CURRENT (mA) EFFICIENCY (%) 80 70 60 60 50 40 30 VIN = 4V VIN = 8V VIN = 12V VIN = 20V 20 10 0 10000 1 100 1000 10 LOAD CURRENT (mA) 3626 G01 100 0 10000 80 75 ILOAD = 1A ILOAD = 2.5A ILOAD = 100mA ILOAD = 10mA 8 0.602 60 50 40 0 f = 500kHz f = 1MHz f = 2MHz f = 3MHz 1 10 100 1000 LOAD CURRENT (mA) Internal MOSFET RDS(ON) vs Temperature 100 80 BOTTOM SWITCH 40 20 0 –50 –25 75 50 25 TEMPERATURE (°C) 0 50 25 75 0 TEMPERATURE (°C) 100 125 3626 G06 100 125 3626 G07 125 2.0 100 1.9 75 1.7 50 1.6 25 1.5 0 1.4 –25 1.2 –50 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 TEMPERATURE MONITOR VOLTAGE (V) TOP SWITCH 60 0.594 –50 –25 Temperature Monitor vs Temperature 160 120 10000 0.596 3626 G05 3626 G04 140 0.600 0.598 30 22 10000 Reference Voltage vs Temperature 70 10 20 100 1000 10 LOAD CURRENT (mA) 0.604 20 10 12 14 16 18 INPUT VOLTAGE (V) 1 0.606 MEASURED TEMPERATURE (°C) 6 RDS(ON) (mΩ) 4 VOUT = 5V VOUT = 3.3V 3626 G02 VFB (V) EFFICIENCY (%) 85 60 30 10 80 65 40 20 VOUT = 3.3V 90 90 70 50 Efficiency vs Frequency (Forced Continuous Mode Operation) VOUT = 1.8V 95 FORCED CONTINUOUS MODE OPERATION 60 3626 G02 Efficiency vs Input Voltage (Burst Mode Operation) 100 Burst Mode OPERATION 90 80 20 EFFICIENCY (%) Efficiency vs Load Current (Burst and Forced Continuous) VOUT = 1.8V 90 EFFICIENCY (%) EFFICIENCY (%) Efficiency vs Load Current (Forced Continuous Mode Operation) 1.1 125 3626 G08 3626f 5 LTC3626 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, PVIN = SVIN = 12V, f = 1MHz unless otherwise noted. Output Current Monitor vs Output Current Output Current Monitor Error vs Output Current 2.25 125 2.00 1.75 94 1.50 1.25 1.00 TA = 85°C TA = 25°C TA = –40°C 0.75 63 0.50 31 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 OUTPUT CURRENT (A) MEASURED OUTPUT CURRENT ERROR (%) 156 IMONOUT CURRENT (µA) CALCULATED OUTPUT CURRENT, IMONOUT • 16000 (A) 2.50 5 4 3 2 1 0 –1 –2 –3 TA = 85°C TA = 25°C TA = –40°C –4 –5 1.25 1 1.75 2 2.25 1.5 OUTPUT CURRENT (A) 3626 G09 Input Current Monitor vs Input Current 25 0.35 22 0.30 19 16 0.25 TA = 85°C TA = 25°C TA = –40°C 0.15 13 9 0.10 6 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 INPUT CURRENT (A) 500 8 450 6 400 4 350 2 IQ (µA) 0.40 MEASURED INPUT CURRENT ERROR (%) 28 IMONIN CURRENT (µA) CALCULATED INPUT CURRENT, IMONIN • 16000 (A) 0.45 Quiescent Current vs VIN (Burst Mode Operation) 10 31 0.20 3626 G10 Input Current Monitor Error vs Input Current 0.50 0 –2 200 –6 TA = 85°C TA = 25°C TA = –40°C –8 2.6 FREQUENCY (MHz) –2 –4 –6 100 125 3626 G14 18 1.6 2.2 2.0 1.8 1.4 –50 –25 20 1.8 1.4 1.2 1.0 1.6 50 25 0 75 TEMPERATURE (°C) 10 12 14 16 INPUT VOLTAGE (V) 2.0 RT = INTVCC 0.8 –8 –25 8 TRACK/SS Pull-Up Current vs Temperature ITRACK/SS (µA) FREQUENCY VARIATION (%) 0 6 3626 G13 2.4 6 2 4 3626 G12 RT = 158kΩ –10 –50 100 Oscillator Internal Set Frequency vs Temperature 4 TA = 85°C TA = 25°C TA = –40°C 150 –10 0.16 0.20 0.24 0.28 0.32 0.36 0.40 0.44 0.48 INPUT CURRENT (A) Oscillator Frequency vs Temperature 8 300 250 –4 3626 G11 10 2.5 50 25 75 0 TEMPERATURE (°C) 100 125 3626 G15 0.6 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 3626 G16 3626f 6 LTC3626 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, PVIN = SVIN = 12V, f = 1MHz unless otherwise noted. Output Voltage vs Time (Burst Mode Operation) Load Regulation Output Voltage vs Time (Forced Continuous Mode Operation) 1.0 0.8 VSW 5V/DIV VSW 5V/DIV VOUT 20mV/DIV VOUT 20mV/DIV IL 1A/DIV IL 1A/DIV ∆VOUT/VOUT (%) 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –1.0 VOUT = 1.8V ILOAD = 100mA Burst Mode OPERATION FORCED CONTINUOUS –0.8 0 0.5 1.5 1 ILOAD (A) 2 3626 G18 4µs/DIV VOUT = 1.8V ILOAD = 100mA 2µs/DIV 3626 G19 2.5 3626 G17 Start-Up from Shutdown (Burst Mode Operation) Output Tracking VOUT 1V/DIV TRACK/SS VFB 500mV/DIV VOUT = 1.8V ILOAD = 200mA 2ms/DIV Start-Up from Shutdown (Forced Continuous Mode Operation) RUN 2V/DIV RUN 2V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 1A/DIV IL 1A/DIV 3626 G20 VOUT = 1.8V ILOAD = 200mA CSS = 2.2nF 200µs/DIV 3626 G21 Load Step (Burst Mode Operation) VOUT 100mV/DIV AC-COUPLED VOUT = 1.8V ILOAD = 200mA CSS = 2.2nF 200µs/DIV 3626 G22 Load Step (Forced Continuous Mode Operation) ITH = INTVCC VOUT 100mV/DIV AC-COUPLED ITH = INTVCC IL 2.5A/DIV IL 2.5A/DIV VOUT = 1.8V 20µs/DIV COUT = 47µF ILOAD = 100mA TO 2.5A 3626 G23 VOUT = 1.8V 20µs/DIV COUT = 47µF ILOAD = 100mA TO 2.5A 3626 G24 3626f 7 LTC3626 PIN FUNCTIONS BOOST (Pin 1): Boosted Floating Driver Supply Pin. The (+) terminal of the external bootstrap capacitor connects to this pin while the (–) terminal connects to the SW pin. The normal operation voltage swing of this pin ranges from INTVCC to PVIN + INTVCC. INTVCC (Pin 2): Internal 3.3V Regulator Output Pin. This pin should be decoupled to PGND with a low ESR ceramic capacitor of value 1µF or greater. The 3.3V regulator is disabled when the RUN pin is low. VON (Pin 3): On-Time Voltage Input. This pin sets the voltage trip point for the on-time comparator. Tying this pin to the output voltage makes the on-time proportional to VOUT when VOUT < 6V. When VOUT > 6V, the switching frequency may become higher than the set frequency. The impedance of this pin is nominally 160kΩ. TSET (Pin 4): Temperature Limit Set Pin. The voltage at this pin determines the threshold for internal temperature shutdown. When the voltage at TMON reaches the voltage at TSET, the LTC3626 will trigger an overtemperature fault. An overtemperature fault will initiate part shutdown, reset soft-start and an attempt to restart once the internal temperature falls 10°C (typical) from the threshold given at TSET. The voltage at TSET has no impact on a secondary overtemperature shutdown threshold within the LTC3626 as described in Note 4 of the Electrical Characteristics section. TMON (Pin 5): Temperature Monitor Output. A voltage proportional to the measured on-die temperature will appear at this pin. The voltage-to-temperature scaling factor is 200°K/V. See the Applications Information section for detailed information on the TMON function. Tie this pin to INTVCC to disable the temperature monitor circuit. SGND (Pin 6): Signal Ground Pin. This pin should have a low noise connection to reference ground. The feedback resistor network, external compensation network, current monitor components, and RT resistor should be connected to this ground. IMONIN (Pin 7): Average Input Current Monitor. A current proportional to the average input current flows out of this pin. Pull this pin to INTVCC to defeat the input current monitor function. An error amplifier compares the voltage on this pin to 1.2V (typical) and throttles the average current as required based on the external resistor value from this pin to SGND. Selecting the external resistor value allows the user to control the maximum average input current. See the Applications Information section for more details. IMONOUT (Pin 8): Average Output Current Monitor Pin. A current proportional to the average output current flows out of this pin. Pull this pin to INTVCC to defeat the output current monitor function. An error amplifier compares the voltage on this pin to 1.2V (typical) and throttles the average current as required based on the external resistor value from this pin to SGND. Selecting the external resistor value allows the user to control the maximum average output current. See the Applications Information section for more details. TRACK/SS (Pin 9): Output Voltage Tracking and Soft-Start Input. Forcing a voltage below 0.6V on this pin overrides the internal reference input to the error amplifier. The LTC3626 will servo the FB pin to the TRACK/SS voltage under this condition. Above 0.6V, the tracking function stops and the internal reference resumes control of the error amplifier. An internal 1.4µA (typical) pull-up current from INTVCC allows a soft-start function to be implemented by connecting an external capacitor between this pin and ground. See the Applications Information section for more details. FB (Pin 10): Output Voltage Feedback. This pin is the input to the error amplifier that compares the feedback voltage to the internal 0.6V reference voltage. Connect this pin to the appropriate resistor divider network to program the desired output voltage. 3626f 8 LTC3626 PIN FUNCTIONS ITH (Pin 11): Error Amplifier Output and Switching Regulator Compensation Point. Connect this pin to appropriate external components to compensate the regulator loop frequency response. Connect this pin to INTVCC to use the default internal compensation. RT (Pin 12): Oscillator Frequency Program Pin. Connect an external resistor, between 640k to 105k, from this pin to SGND to program the LTC3626 switching frequency from 500kHz to 3MHz. When RT is tied to INTVCC, the switching frequency will default to 2MHz (typical). RUN (Pin 13): Regulator Enable Pin. Enables chip operation by applying a voltage above 1.25V. A voltage below 1.0V on this pin places the part into shutdown. Do not float this pin. SVIN (Pin 14): Signal Power Supply Input. This pin supplies current to the internal 3.3V regulator. PGOOD (Pin 18): Open-Drain Power Good Output Pin. PGOOD is pulled to ground when the voltage at the FB pin is not within ±8% (typical) of the internal 0.6V reference. PGOOD becomes high impedance once the voltage at the FB pin returns to within ±5% (typical) of the internal reference. SW (Pins 19, 20): Switch Node Connection to Inductor. Connect this pin to the SW side of the external inductor. The normal operation voltage swing of this pin ranges from ground to PVIN. PGND (Exposed Pad Pin 21): Power Ground Pin. The (–) terminal of the input bypass capacitor, CIN, and the (–) of the output capacitor, COUT, should be tied to this pin with a low impedance connection. This pin must be soldered to the PCB to provide low impedance electrical contact to ground and good thermal contact to the PCB. PVIN (Pins 15, 16): Main Power Supply Input. These pins should be closely decoupled to PGND with a low ESR capacitor of value 10µF or more. MODE/SYNC (Pin 17): Mode Selection and External Synchronization Input. This pin places the LTC3626 into forced continuous operation when tied to ground. High efficiency Burst Mode operation is enabled by either floating this pin or tying this pin to INTVCC. When driven with an external clock, an internal phase-locked loop will synchronize the phase and frequency of the internal oscillator to that of incoming clock signal. During external clock synchronization, the LTC3626 will default to forced continuous operation. 3626f 9 LTC3626 FUNCTIONAL DIAGRAM RIN CIN2 VON RUN 160k SVIN 1.25V + AV = 1 – RT OSC RRT MODE/SYNC ION 0.72V 6V ION CONTROLLER tON = PVIN 3.3V REG RUN PVIN CIN RUN VVON IION CINTVCC R S ON Q BOOST SWITCH LOGIC AND ANTISHOOTTHROUGH OSC PLL-SYNC ICMP INTVCC IREV – TG CBST M1 L SW COUT BG M2 PGND + – + SENSE– COMP SELECT SENSE+ ITH RCOMP R1 FB CCOMP IDEAL DIODES R2 0.6V REF + EA + – – – + INTERNAL SOFT-START 1.2V IMONOUT – 0.648V OV PGOOD INTVCC OUTPUT CURRENT MONITOR IMONIN 1.4µA TRACK/SS DUTY CYCLE SGND + – TRACK – UV BURST FC SS + 0.552V CSS + MODE SELECT MODE/SYNC 0.48V AT START-UP 0.10V AFTER START-UP + TJ + 1V/200k – – TMON TEMP FAULT CONTROL TSET 3626 BD 3626f 10 LTC3626 OPERATION The LTC3626 is a current mode, monolithic, step-down regulator capable of providing up to 2.5A of output current from an input supply as high as 20V. Its unique controlled on-time architecture allows extremely low step-down ratios while maintaining a constant switching frequency. The part is enabled by raising the RUN pin above 1.25V (typical). Main Control Loop In normal operation the internal top power MOSFET is turned on for a fixed interval determined by an internal one-shot timer (“ON” signal in the Functional Diagram). When the top power MOSFET turns off, the bottom power MOSFET turns on until the current comparator, ICMP, trips, thus restarting the one-shot timer and initiating the next cycle. The inductor current is monitored by sensing the voltage drop across the bottom power MOSFET. The voltage at the ITH node sets the ICMP comparator threshold corresponding to the inductor valley current. The error amplifier, EA, adjusts the ITH voltage by comparing an internal 0.6V reference voltage to the feedback signal, VFB, derived from the output voltage. If, for example, the load current increases, the output voltage will decrease relative to the 0.6V reference. The ITH voltage then rises until the average inductor current matches that of the load current. At light load currents the inductor current can drop to zero or become negative. If the LTC3626 is configured for Burst Mode operation, this inductor current condition is detected by the current reversal comparator, IREV, which in turn shuts off the bottom power MOSFET and places the part into a low quiescent current sleep state resulting in discontinuous operation and increased efficiency at low load currents. Both power MOSFETs remain off with the part in sleep and the output capacitor supplying the load current until the ITH voltage rises sufficiently to initiate another cycle. Discontinuous operation is disabled by tying the MODE/SYNC pin to ground, placing the LTC3626 into forced continuous mode. In forced continuous mode, continuous synchronous operation occurs regardless of the output load current. The operating frequency is determined by the value of the RT resistor, which programs the current for the internal oscillator. An internal phase-locked loop adjusts the switching regulator on-time to track the internal oscillator edge and force a constant switching frequency, subject to tON and tOFF time constraints as shown in the Electrical Characteristics table. Alternatively, the RT pin can be connected to the INTVCC pin which causes the internal oscillator to run at the default frequency of 2MHz. Finally, a clock signal can be applied to the MODE/SYNC pin to synchronize the switching frequency to an external source. The regulator defaults to forced continuous operation when an external clock signal is applied. Output/Input Current Monitor and Limit The LTC3626 provides a scaled replica of the average output current and a scaled replica of the average input current at the IMONOUT and IMONIN pins respectively. The average current at each of these pins will be 1/16,000th of the measured average current. Further, the voltage at each pin is continuously fed to independent current limit amplifiers that have a voltage reference at 1.2V. Thus, a programmable average current limit for the output current and/or input current may be obtained by placing a resistor of suitable value at the pin of interest so as to produce 1.2V at the desired current limit. When the current limit feature is used, a compensation capacitor (1µF typical) should be placed in parallel with the chosen resistor. The output or input current monitor and limit circuits may be individually disabled by pulling IMONOUT or IMONIN to INTVCC as appropriate. 3626f 11 LTC3626 OPERATION Temperature Monitor and Limit The LTC3626 produces a voltage at the TMON pin proportional to the measured on-die temperature. The on-die temperature-to-voltage scaling factor is 200°K/V. Thus, to obtain the on-die temperature in degrees Kelvin, simply multiply the voltage provided at the TMON pin by the scaling factor. To obtain the on-die temperature in degrees Celsius, subtract 273 from the value obtained in degrees Kelvin. The voltage produced at TMON is continuously fed to a limit comparator that has the voltage at the TSET pin as its reference input. When triggered, this comparator generates an overtemperature fault that will initiate part shutdown and reset of soft-start. Thus, a maximum junction temperature limit may be set by providing a voltage at the TSET pin that corresponds to the temperature limit of interest. The voltage at the TSET pin may be derived from a resistor divider from INTVCC, subject to the current constraints listed in the Electrical Characteristics section, or may be driven externally. The LTC3626 will clear the overtemperature fault and restart once the internal temperature falls 10°C (typical) from the threshold given at TSET. The voltage at the TSET pin has no impact on the secondary overtemperature shutdown threshold within the LTC3626 as described in Note 4 of the Electrical Characteristics. “Power Good” Status Output The PGOOD open-drain output will be pulled low if the regulator output exits a ±8% window around the regulation point. This condition is released once regulation within a ±5% window is achieved. To prevent unwanted PGOOD glitches during transients or dynamic VOUT changes, the LTC3626 PGOOD falling edge includes a filter time of approximately 40μs. PVIN Overvoltage Protection To protect the internal power MOSFET devices against transient voltage spikes, the LTC3626 continuously monitors the PVIN pin for an overvoltage condition. When PVIN rises above 21.5V (typical), the regulator suspends operation by shutting off both power MOSFETs and resets soft-start. Once PVIN drops below 20.5V (typical), the regulator restarts normal operation by executing a soft-start. 3626f 12 LTC3626 APPLICATIONS INFORMATION A general LTC3626 application circuit is shown on the first page of this data sheet. External component selection is largely driven by the load requirement and begins with the selection of the inductor L. Once the inductor is chosen, the input capacitor, CIN, the output capacitor, COUT, the internal regulator capacitor, CINTVCC, and the boost capacitor, CBST, can be selected. Next, the feedback resistors are selected to set the desired output voltage. Finally, the remaining optional external components can be selected for functions such as external loop compensation, PGOOD, average output current monitor and limit, average input current monitor and limit, and on-die temperature monitor and limit. Operating Frequency Selection of the operating frequency is a trade-off between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. The operating frequency, f, of the LTC3626 is determined by an external resistor that is connected between the RT pin and ground. The value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: 3.2E11 f 3500 FREQUENCY (kHz) 3000 2500 2000 1500 1000 500 0 0 100 200 300 400 RT (kΩ) 500 600 700 3626 F01 Figure 1. Switching Frequency vs RT this condition, it is possible the operating frequency may be higher than the programmed value. As a result, for output voltages greater than 6V, the value of the RT resistor may need adjustment to obtain the desired operating frequency. Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the inductor ripple current. More specifically, the inductor ripple current decreases with higher inductor value or higher operating frequency according to the following equation: V V ∆IL = OUT 1– OUT f •L VIN Connecting the RT pin to INTVCC will assert the internal default frequency f = 2MHz; however, this switching frequency will be more sensitive to process and temperature variations than using a resistor on RT (see Typical Performance Characteristics). where ΔIL = inductor ripple current, VIN = PVIN, f = operating frequency and L = inductor value. A trade-off between component size, efficiency and operating frequency can be seen from this equation. Accepting larger values of ΔIL allows the use of lower value inductors but results in greater core loss in the inductor, greater ESR loss in the output capacitor, and larger output ripple. Generally, highest efficiency operation is obtained at low operating frequency with small ripple current. The LTC3626 is not optimized for constant on-time operation when configured to generate output voltages greater than 6V. Though output regulation will be maintained under A reasonable starting point for setting the ripple current is approximately 1AP-P. Note that the largest ripple current occurs at the highest VIN. To guarantee the ripple current RRT = where RRT is in Ω and f is in Hz. 3626f 13 LTC3626 APPLICATIONS INFORMATION does not exceed a specified maximum the inductance should be chosen according to: V VOUT OUT L= 1– f • ∆IL(MAX) VIN(MAX) Once the value for L is known, the type of inductor must be selected. Actual core loss is independent of core size for a fixed inductor value but is very dependent on the inductance selected. As the inductance increases, core loss decreases. Unfortunately, increased inductance requires more turns of wire leading to increased copper loss. Ferrite designs exhibit very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core materials saturate “hard,” meaning the inductance collapses abruptly when the peak design current is exceeded. This collapse will result in an abrupt increase in inductor ripple current, so it is important to ensure the core will not saturate. Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroidal or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/EMI requirements. New designs for surface mount inductors are available from Toko, Vishay, NEC/Tokin, Cooper, Coilcraft, TDK and Würth Electronik. Table 1 gives a sampling of available surface mount inductors. The input capacitance, CIN, is needed to filter the trapezoidal wave current at the drain of the top power MOSFET. To prevent large voltage transients from occurring, a low ESR input capacitor sized for the maximum RMS current is recommended. The maximum RMS current is given by: INDUCTANCE VOUT ( VIN – VOUT ) VIN DCR MAX CURRENT DIMENSIONS HEIGHT 6.5mm × 7mm 3mm 7mm × 7.7mm 2.0mm 6.9mm × 7.7mm 3.0mm 7mm × 7.3mm 3.0mm 6.9mm × 7.3mm 3.2mm 7mm × 7.7mm 3.8mm Vishay IHLP-2525CZ-01 Series 0.33µH 3.5mW 20A 0.47µH 4.0mW 17.5A 0.68µH 5.0mW 15.5A 0.82µH 6.7mW 13A 1.0µH 9.0mW 11A 1.5µH 14mΩ 9A 2.2µH 18mΩ 8A 3.3µH 28mΩ 6A 4.7µH 37mΩ 5.5A 6.8µH 54mΩ 4.5A Toko FDV0620 Series 0.47µH 8.3mW 9A 1µH 18.3mW 5.7A NEC/Tokin MLC0730L Series 0.47µH 4.5mW 16.6A 0.75µH 7.5mW 12.2A 1µH 9mW 10.6A Cooper HCP0703 Series 0.47µH 4.2mW 17A 0.68µH 5.5mW 15A 0.82µH 8mW 13A 1µH 10mW 11A 1.5µH 14mW 9A TDK RLF7030 Series 8.8mW 6.4A 1.5µH 1µH 9.6mW 6.1A 2.2µH 12mW 5.4A Würth Electronik WE-HC 744312 Series 0.47µH CIN and COUT Selection IRMS = IOUT(MAX) Table 1. Inductor Selection Table 3.4mW 16A 0.72µH 7.5mW 12A 1µH 9.5mW 11A 1.5µH 10.5mW 9A This formula has a maximum at VIN = 2VOUT, where IRMS ≅ IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings 3626f 14 LTC3626 APPLICATIONS INFORMATION from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Thus, a good place to start is with the output capacitor size of approximately: Several capacitors may also be paralleled to meet size or height requirements in the design. For low input voltage applications, sufficient bulk input capacitance is needed to minimize transient effects during output load changes. Even though the LTC3626 design includes an overvoltage protection circuit, care must always be taken to ensure input voltage transients do not pose an overvoltage hazard to the part. Additional input voltage filtering to the SVIN pin (signal VIN) is made possible by adding optional components RIN and CIN2 as shown in the Functional Diagram. Generally, the inherent supply rejection of the LTC3626 makes the addition of these components unnecessary, however, users with large, asynchronous noise on the input supply may choose to populate these components. Typical values for RIN and CIN2 are 5Ω and 0.33µF respectively. The selection of COUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response. The output ripple, ∆VOUT, is approximated by: 1 ∆VOUT < ∆IL ESR + 8 • f • COUT When using low ESR ceramic capacitors, it is more useful to choose the output capacitor value to fulfill a charge storage requirement. During a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. Typically, 3 to 4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. The output droop, VDROOP, is usually about 3 times the linear drop of the first cycle. COUT ≈ 3 • ∆IOUT f • VDROOP Though this equation provides a good approximation, more capacitance may be required depending on the duty cycle and load step requirements. The actual VDROOP should be verified by applying a load step to the output. Using Ceramic Input and Output Capacitors Higher value, lower cost ceramic capacitors are now available in small case sizes. Their high voltage rating and low ESR make them ideal for switching regulator applications. However, due to the self-resonant and high-Q characteristics of some types of ceramic capacitors, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input, and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the VIN input. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. For a more detailed discussion, refer to Application Note 88. When choosing the input and output ceramic capacitors choose the X5R or X7R dielectric formulations. These dielectrics provide the best temperature and voltage characteristics for a given value and size. INTVCC Regulator An internal low dropout (LDO) regulator produces a 3.3V supply voltage used to power much of the internal LTC3626 circuitry including the power MOSFET gate drivers. The INTVCC pin connects to the output of this regulator and should have a minimum 1μF of decoupling capacitance to ground. The decoupling capacitor should have low impedance electrical connections to the INTVCC and PGND pins to provide the transient currents required by the LTC3626. The user may connect a maximum load current of 5mA to this pin but must take into account the increased power dissipation and die temperature that 3626f 15 LTC3626 APPLICATIONS INFORMATION results. Furthermore, this supply is intended only to supply additional DC load currents as desired and not intended to regulate large transient or AC behavior as this may impact LTC3626 operation. Boost Capacitor The boost capacitor, CBST, on the Functional Diagram is used to create a voltage rail above the applied input voltage, VIN. Specifically, the boost capacitor is charged to a voltage equal to approximately INTVCC each time the bottom power MOSFET is turned on. The charge on this capacitor is then used to supply the required transient current during the remainder of the switching cycle. When the top MOSFET is turned on, the BOOST pin voltage will be equal to approximately VIN + 3.3V. For most applications a 0.1μF ceramic capacitor will provide adequate performance. Output Voltage Programming The LTC3626 will adjust the output voltage such that VFB equals the reference voltage of 0.6V according to: R1 VOUT = 0.6V 1+ R2 The desired output voltage is set by the appropriate selection of resistors R1 and R2 as shown in Figure 2. Choosing large values for R1 and R2 will result in improved efficiency but may lead to undesired noise coupling or phase margin reduction due to stray capacitance at the FB node. Care should be taken to route the FB line away from any noise source, such as the SW or BOOST lines. To improve the frequency response of the main control loop a feedforward capacitor, CF, may be used as shown in Figure 2. VOUT R1 CF FB LTC3626 R2 SGND 3626 F02 Figure 2. Optional Feedforward Capacitor Minimum Off-Time/On-Time Considerations The minimum off-time is the smallest amount of time that the LTC3626 requires to turn on the bottom power MOSFET, trip the current comparator and turn off the power MOSFET. This time is typically 40ns. For the controlled on-time current mode control architecture, the minimum off-time limit imposes a maximum duty cycle of: DCMAX = 1 – (f • tOFF(MIN)) where f is the switching frequency and tOFF(MIN) is the minimum off-time. If the maximum duty cycle is surpassed, due to a dropping input voltage for example, the output will drop out of regulation. The minimum input voltage to avoid this dropout condition is: VIN(MIN) = ( VOUT 1– f • tOFF(MIN) ) Users should consider reducing the LTC3626 operating frequency for applications that may violate the minimum off-time if constant regulation is required. Conversely, the minimum on-time is the smallest duration of time in which the top power MOSFET can be in its “on” state. This time is typically 20ns. In continuous mode operation, the minimum on-time limit imposes a minimum duty cycle of: DCMIN = (f • tON(MIN)) where tON(MIN) is the minimum on-time. As the equation shows, reducing the operating frequency will alleviate the minimum duty cycle constraint. In rare cases in which the LTC3626’s minimum duty cycle is surpassed, the output voltage will still remain in regulation, however the switching frequency will be lower than its programmed value. This is an acceptable result in many applications, so high switching frequencies may be used in the design without fear of severe consequences. As the sections on Inductor and Capacitor Selection show, high switching frequencies allow the use of smaller board components, thus reducing the footprint of the application circuit. 3626f 16 LTC3626 APPLICATIONS INFORMATION Internal/External Loop Compensation Checking Transient Response The LTC3626 provides the option to use a fixed internal loop compensation network to reduce both the required external component count and design time. The internal loop compensation network can be selected by connecting the ITH pin to the INTVCC pin. To ensure stability, it is recommended that the internal compensation be used at operating frequencies of 1MHz or greater. When using internal compensation, a reasonable starting point for the minimum amount of output capacitance necessary for stability can be found as the greater of either 22µF or COUT defined by the equation: The regulator loop response can be checked by observing the response of the system to a load step. When configured for external compensation, the availability of the ITH pin not only allows optimization of the control loop behavior but also provides a DC-coupled and AC-filtered closed-loop response test point. The DC step, rise time, and settling behavior at this test point reflect the system’s closedloop response. Assuming a predominantly second order system, the phase margin and/or damping factor can be estimated by observing the percentage of overshoot seen at this pin with a high impedance, low capacitance probe. COUT > 70e-6 VOUT Alternatively, the user may choose specific external loop compensation components to optimize the main control loop transient response as desired. External loop compensation is chosen by simply connecting the desired network to the ITH pin. Suggested compensation component values are shown in Figure 3. For a 2MHz application, an R-C (RCOMP and CCOMP in Figure 3) network of 220pF and 13kΩ provides a good starting point. The bandwidth of the loop increases with decreasing C. If R is increased by the same factor that C is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. A 10pF bypass capacitor (CBYP in Figure 3) the ITH pin is recommended to filter out high frequency coupling from stray board capacitance. In addition, a feedforward capacitor, CF, can be added to improve the high frequency response, as previously shown in Figure 2. Capacitor CF provides phase lead by creating a high frequency zero with R1 which improves the phase margin. ITH LTC3626 SGND RCOMP 13k CCOMP 220pF CBYP The ITH external components shown in Figure 3 will provide an adequate starting point for most applications. The series R-C filter sets the pole-zero loop compensation. The values can be modified slightly, from approximately 0.5 to 2 times their suggested values, to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The specific output capacitors must be selected because their various types and values determine the loop feedback factor, gain, and phase. An output current pulse of 20% to 100% of full load current, with a rise time of 1μs to 10μs, will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. When observing the response of VOUT to a load step, the initial output voltage step may not be within the bandwidth of the feedback loop. As a result, the standard second order overshoot/DC ratio cannot be used to estimate phase margin. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Linear Technology Application Note 76. As shown in Figure 2 a feed-forward capacitor, CF, may be added across feedback resistor R1 to improve the high frequency response of the system. Capacitor CF provides phase lead by creating a high frequency zero with R1. 3626 F03 Figure 3. Compensation Components 3626f 17 LTC3626 APPLICATIONS INFORMATION In some applications severe transients can be caused by switching in loads with large (>10μF) input capacitors. The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this output droop if the switch connecting the load has low resistance and is driven quickly. The solution is to limit the turn-on speed of the load switch driver. A Hot Swap™ controller is designed specifically for this purpose and usually incorporates current limit, short-circuit protection and soft-start functions. Input/Output Current Monitor and Limit The LTC3626 senses the average current through the synchronous switch during the on state and outputs a scaled replica of this current (which corresponds to the regulator’s load current) to the IMONOUT pin. A mirrored version of this signal is modulated with the buck regulator’s duty cycle to provide a scaled replica of the buck regulator’s input current to the IMONIN pin. The average current at each of the monitor pins is 1/16000th the measured average current. The output current at either pin may be measured directly or converted to a voltage with an external resistor. The average input and output current monitor circuits both use a chopping technique to achieve high accuracy. As a result, a small periodic ripple may be seen at either of these outputs, the average of which is the measured value of interest. The ripple frequency will be the operating frequency divided by 256. In addition, the average input current is measured by modulating the duty cycle of the average output current leading to an additional ripple at the operating frequency. If required, a capacitor may be placed on either output pin to reduce the magnitude of the ripple. The voltages at the IMONOUT and IMONIN pins are continuously fed to independent current limit amplifiers that have a voltage reference of 1.2V (typical). A programmable average current limit for either average output current or average input current may be obtained by placing a resistor, RLIM, from the monitor pin to SGND according to the following equation: RLIM = 1.2V •16000 ILIM where ILIM is the programmed current limit. When active, the current limit amplifiers form a feedback loop that controls the maximum average current produced by the LTC3626. Thus, when using the current limit feature, a compensation capacitor should be placed between SGND and the monitor pin of interest. This capacitor, combined with the RLIM resistor, is intended to create a dominant pole for compensation purposes. For most applications, a capacitor with a minimum value of 1µF will provide adequate loop stability. However, given the wide variation in loop parameters that depend on specific application requirements, loop stability should be confirmed by stepping the load current to a level that triggers the programmed current limit. The resultant transient response should provide a sense of the overall loop stability without breaking the feedback loop. The transient response that results from releasing the current limit should also be checked. If the transient response waveforms exhibit excessive ringing, indicating inadequate loop stability, increase the compensation capacitor value until adequate stability has been achieved. The simple dominant pole compensation scheme discussed previously is intended to provide loop stability by limiting the bandwidth of the current limit feedback loop. As a result, the average current may momentarily exceed the programmed limit until the current limit feedback loop can respond. More advanced compensation networks may be used to potentially reduce the loop response time but generally require more caution and design expertise. For example, one technique is to add a low value resistor in 3626f 18 LTC3626 APPLICATIONS INFORMATION series with the compensation capacitor. The resistor in series with the capacitor creates a zero in the current limit loop transfer function given by: fZ = 1 2 • π •R Z •C while minimally impacting the frequency of the compensation pole. Given the current limit loop frequency response contains several moderate frequency poles: one at approximately 10kHz (typical) and two at approximately 100kHz (typical), the placement of the zero in frequency can be used to provide additional phase margin, which in turn, may allow a higher loop bandwidth without sacrificing loop stability. For example, choosing C = 0.33µF and RZ = 50 creates a zero at approximately 10kHz thereby reducing the impact of the internal pole located at that same frequency. With this compensation scheme, the LTC3626 current limit loop will have a dominant pole frequency, and overall loop bandwidth, roughly three times higher than that provided with a 1µF capacitor, while likely providing adequate loop stability. As previously described, the LTC3626 senses the average output current through the synchronous FET during the off time. As a result, it is recommended the LTC3626 be operated with an off time of greater than 150ns for best current monitor accuracy. For many applications, this is of little concern unless operating at or near regulator dropout conditions (extremely high duty-cycle operation) and high switching frequencies. Overall, best current monitor accuracy is achieved with output currents above approximately 200mA in forced continuous mode with switching frequencies of 1MHz or lower. On-Die Temperature Monitor and Limit The LTC3626 produces a voltage at the TMON pin proportional to the measured junction temperature. The junction temperature-to-voltage scaling factor is 200°K/V. Thus, to obtain the junction temperature in degrees Kelvin, simply multiply the voltage provided at the TMON pin by the scaling factor. To obtain the junction temperature in degrees Celsius, subtract 273 from the value obtained in degrees Kelvin. The temperature monitor function uses a chopping technique to achieve high precision. As a result, a small periodic ripple may be seen at the TMON pin, the average of which is the measured value of interest. The ripple frequency will be the operating frequency divided by 32. If required, a 1µF or greater capacitor to SGND may be placed on the output to reduce the magnitude of the ripple. The temperature monitor output is driven from a flexible, internally compensated on-chip buffer capable of sourcing or sinking small amounts of continuous currents (<20µA typical). The buffer internal compensation is intended for capacitive loads up to approximately 150pF (typical). This configuration allows direct connection of TMON to convenient test equipment, such as a multimeter, for temperature measurement. The internal compensation may be overridden by connecting a capacitor of value 1µF or greater between TMON and SGND. This configuration allows for a wide range of applications requiring stability with higher load capacitance, such as some ADC inputs. The voltage produced at TMON is continuously fed to a limit comparator that has the voltage at the TSET pin as its reference input. When triggered, this comparator generates an overtemperature fault that will initiate part shutdown and reset of soft-start. Thus, a programmable temperature limit may be obtained by providing a voltage at the TSET pin that corresponds to the temperature limit of interest. The voltage at the TSET pin may be derived from a resistor divider from INTVCC, subject to the current constraints listed in the Electrical Characteristics section, or may be driven externally. The LTC3626 will clear the overtemperature fault and attempt to restart once the internal temperature falls 10°C (typical) from the threshold given at TSET. As an example, to set a temperature limit at approximately 125°C, the voltage at TSET should be: VTSET = 125°C + 273 ≈ 2V 200°K/V 3626f 19 LTC3626 APPLICATIONS INFORMATION MODE/SYNC Operation The MODE/SYNC pin is a multipurpose pin allowing both mode selection and operating frequency synchronization. Connecting this pin to INTVCC enables Burst Mode operation for superior efficiency at low load currents at the expense of slightly higher output voltage ripple. When the MODE/ SYNC pin is pulled to ground, forced continuous mode operation is selected creating the lowest output voltage ripple at the expense of light load efficiency. The LTC3626 will detect the presence of an external clock signal on the MODE/SYNC pin and synchronize the internal oscillator to the phase and frequency of the incoming clock. The presence of an external clock will place the LTC3626 into forced continuous mode operation. Output Voltage Tracking and Soft-Start The LTC3626 allows the user to control the output voltage ramp rate by means of the TRACK/SS pin. From 0V to 0.6V the TRACK/SS pin will override the internal reference input to the error amplifier forcing regulation of the feedback voltage to that seen at the TRACK/SS pin. When the voltage at the TRACK/SS pin rises above 0.6V, tracking is disabled and the feedback voltage will be regulated to the internal reference voltage. The voltage at the TRACK/SS pin may be driven from an external source, or alternatively, the user may leverage the internal 1.4µA (typical) pull-up current on TRACK/SS to implement a soft-start function by connecting a capacitor from the TRACK/SS pin to ground. The relationship between output rise time and TRACK/SS capacitance is given by: tSS = 430,000 • CTRACK/SS A default internal soft-start timer forces a minimum softstart time of 400µs (typical) by overriding the TRACK/ SS pin input during this time period. Hence, capacitance values less than approximately 1000pF will not significantly affect soft-start behavior. When using the TRACK/SS pin, the regulator defaults to Burst Mode operation until the output exceeds 80% of its final value (VFB > 0.48V). Once the output reaches this voltage, the operating mode of the regulator switches to the mode selected by the MODE/SYNC pin as described above. During normal operation, if the output drops below 10% of its final value, as it may when tracking down for instance, the regulator will automatically switch to Burst Mode operation to prevent inductor saturation and improve TRACK/SS pin accuracy. Output Power Good The PGOOD output of the LTC3626 is driven by a 20Ω (typical) open-drain pull-down device. This pin will become high impedance once the output voltage is within 5% (typical) of the target regulation point allowing the voltage at PGOOD to rise via an external pull-up resistor. If the output voltage exits a 8% (typical) regulation window around the target regulation point, the open-drain output will pull down to ground, thereby dropping the PGOOD pin voltage. A filter time of 40μs (typical) acts to prevent unwanted PGOOD output changes during VOUT transient events. As a result, the output voltage must be within the target regulation window of 5% for 40μs before the PGOOD pin is pulled high. Conversely, the output voltage must exit the 8% regulation window for 40μs before the PGOOD pin pulls to ground (see Figure 4). NOMINAL OUTPUT PGOOD VOLTAGE VOUT –8% –5% 0% 5% 8% 3626 F04 Figure 4. PGOOD Pin Behavior Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: % Efficiency = 100% – (L1 + L2 + L3 +…) where L1, L2, etc. are the individual loss terms as a percentage of input power. 3626f 20 LTC3626 APPLICATIONS INFORMATION Although all dissipative elements in the circuit produce losses, three main sources account for the majority of the losses in the LTC3626: 1) I2R loss, 2) switching losses and quiescent current loss, 3) transition losses and other system losses. Other losses, including diode conduction losses during dead time and inductor core losses, generally account for less than 2% total additional loss. 1.I2R loss is calculated from the DC resistance of the internal switches, RSW, and external inductor, RL. In continuous mode, the average output current will flow through inductor L but is “chopped” between the internal top and bottom power MOSFETs. Thus, the series resistance looking into the SW pin is a function of both the top and bottom MOSFET’s RDS(ON) and the duty cycle (DC) as follows: The LTC3626 requires the exposed package backplane metal (PGND) to be well soldered to the PC board to provide good thermal contact. This gives the QFN package exceptional thermal properties, compared to other packages of similar size, making it difficult in normal operation to exceed the maximum junction temperature of the part. In many applications, the LTC3626 does not generate much heat due to its high efficiency and low thermal resistance package backplane. However, in applications in which the LTC3626 is running at a high ambient temperature, high input voltage, high switching frequency, and maximum output current, the generated heat may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 175°C, both power switches will be turned off until temperature decreases approximately 10°C. RSW = (RDS(ON)TOP )(DC) +(RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus to obtain I2R loss: “I2R Loss” = IOUT2 • (RSW + RL) 2.The internal LDO supplies the power to the INTVCC rail. The total power loss here is the sum of the switching losses and quiescent current losses from the control circuitry. Each time a power MOSFET gate is switched from low to high to low again, a packet of charge, dQ, moves from SVIN to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the DC control bias current. In continuous mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the internal top and bottom power MOSFETs and f is the switching frequency. For estimation purposes, (QT + QB) on the LTC3626 is approximately 2.5nC. To calculate the total power loss from the LDO load, simply add the gate charge current and quiescent current and multiply by SVIN: PLDO = (IGATECHG + IQ) • VIN 3. Other “hidden” losses such as transition loss, copper trace resistances, and internal load currents can account for additional efficiency degradations in the overall power system. Transition loss arises from the brief amount of time the top power MOSFET spends in the saturated region during switch node transitions. Thermal Considerations Thermal analysis should always be performed by the user to ensure the LTC3626 does not exceed the maximum junction temperature. The temperature rise is given by: TRISE = PD • θJA where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. Consider the example in which an LTC3626EUDC is operating with IOUT = 2.5A, PVIN = SVIN = 12V, f = 2MHz, VOUT = 1.8V, and an ambient temperature of 70°C. From the Typical Performance Characteristics section the RDS(ON) of the top switch is found to be nominally 130mΩ while that of the bottom switch is nominally 85mΩ yielding an equivalent power MOSFET resistance RSW of: RDS(ON)TOP • 1.8 10.2 +RDS(ON)BOT • =92mW 12 12 3626f 21 LTC3626 APPLICATIONS INFORMATION From the previous section, IGATECHG is approximately 5mA when f = 2MHz, and the spec table lists the typical IQ to be approximately 1mA. Therefore, the total power dissipation due to resistive losses and LDO losses is: PD = IOUT2 • RSW + VIN • (IGATECHG + IQ) PD = (2.5A)2 • (0.092Ω) + 12V • 5mA = 635mW The QFN 3mm × 4mm package junction-to-ambient thermal resistance, θJA, is approximately 47°C/W. Therefore, the junction temperature of the regulator operating in a 70°C ambient temperature is approximately: TJ = 0.63W • 47°C/W + 70°C = 100°C which is below the maximum junction temperature of 125°C. Board Layout Considerations 4. Keep sensitive components away from the SW and BOOST pins. The RRT resistor, the feedback resistors, the compensation components, the current monitor components, and the INTVCC bypass capacitor should all be routed away from the SW trace and the inductor. 5. A ground plane is preferred, but if not available the signal and power grounds should be segregated with both connecting to a common, low noise reference point. The point at which the ground terminals of the VIN and VOUT bypass capacitors are connected makes a good, low noise reference point. The connection to the PGND pin should be made with a minimal resistance trace from the reference point. 6. Flood all unused areas on all layers with copper in order to reduce the temperature rise of power components. These copper areas should be connected to the exposed backside connection of the IC. When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3626. Design Example 1. Does the capacitor CIN connect to PVIN and PGND as close to the pins as possible? These capacitors provide the AC current to the internal power MOSFETs. The (–) plate of CIN should be closely connected to PGND and the (–) plate of COUT. VIN = 12V, VOUT = 1.8V, IOUT(MAX) = 2.5A, IOUT(MIN) = 50mA 2. The output capacitor, COUT, and inductor L1 should be closely connected to minimize loss. The (–) plate of COUT should be closely connected to PGND and the (–) plate of CIN. 3. The resistive divider, R1 and R2, must be connected between the (+) plate of COUT and a ground line terminated near SGND. The feedback signal, VFB, should be routed away from noisy components and traces such as the SW and BOOST lines, and its trace length should be minimized. In addition, RT, compensation components, and current and temperature monitor/limit components should be terminated to SGND. As a design example, consider using the LTC3626 in an application with the following specifications: Further, the ability to continuously monitor the average output current (IOUT) and the internal temperature is desired. Finally, an average IOUT limit of 2.5A and an internal temperature limit of approximately 125°C are desired. Because efficiency is important at both high and low load currents, Burst Mode operation and 1MHz operation is chosen. First, the correct RRT resistor value for 1MHz switching frequency must be chosen. Based on the equation in the Applications Information section, RRT is calculated to be 320k. A standard 324k resistor is selected for RRT. 3626f 22 LTC3626 APPLICATIONS INFORMATION Next, determine the inductor value for approximately 40% ripple current using: The PGOOD pin is connected to VIN through a 100k resistor to INTVCC. 1.8V 1.8V L= 1– = 1.53µH 1MHz •1A 12V A standard 1.5µH inductor will work well for this application. Next, COUT is selected based on the required output transient performance and the required ESR to satisfy the output voltage ripple. For this design, two 22µF ceramic capacitors will be used. CIN should be sized for a maximum current rating of: IRMS = 2.5A • 1.8V (12V – 1.8V ) = 0.89A 12V CIN1 47µF CINTVCC 2.2µF CIN2 1µF RTSET1 432k RTSET2 665k R3 5Ω C3 0.33µF RPGD 100k CIOUT 1µF To program the IOUT limit at 2.5A, a resistor is connected between IMONOUT and SGND with a desired value equal to: RIOUT = 16,000 •1.2V = 7.68kW 2.5A Thus, a standard 7.68kΩ will be selected for RIOUT. A 1µF capacitor placed in parallel with RIOUT for IOUT limit loop compensation should be adequate for most applications. The 125°C temperature limit is programmed by setting a voltage at the TSET pin equal to: Decoupling the PVIN pin with a 47µF ceramic capacitor should be adequate for most applications. An additional 1µF capacitor on the PVIN can be used to help reduce ringing as required. A 0.33µF capacitor on the SVIN pin is optional and will be tied to PVIN through a 5Ω resistor for additional filtering at the SVIN pin. Finally, a 0.1µF boost capacitor should work for most applications. VIN 12V To save board space, the ITH pin is connected to INTVCC to select the internal compensation network. PVIN SVIN RUN VTSET = 125°C + 273 ≈ 2V 200°K/V In this example, the TSET voltage will be derived by dividing the available INTVCC voltage using RTSET1 = 432k and RTSET2 = 665k. BOOST LTC3626 INTVCC TRACK/SS SW ITH MODE/SYNC VON IMONIN PGOOD FB TMON TSET RT IMONOUT SGND PGND RIOUT 7.68k CBST 0.1µF L1 1.5µH R1 40.2k CF 22pF VOUT 1.8V COUT 2.5A 47µF R2 20k RT 324k 3626 F07 Figure 7. 12V Input to 1.8V Output, 2.5A Regulator at 1MHz in Burst Mode Operation with Output Current Monitor and 2.5A Limit, On-Die Temperature Monitor and 125°C Limit 3626f 23 LTC3626 TYPICAL APPLICATIONS 12V Input to ±5V Output at 2MHz VIN 12V C1 47µF C3A 0.33µF R3A 5Ω C4A 2.2µF RCOMPA 13k CCOMPA 220pF R3B 5Ω C3B 0.33µF C4B 2.2µF RCOMPB 13k CCOMPB 220pF PVIN SVIN RUN BOOST LTC3626 PGOOD INTVCC RT SW TSET TMON VON IMONIN IMONOUT FB TRACK/SS ITH MODE/SYNC SGND PVIN SVIN RUN L1A 1.5µH R1A 294k CFA 22pF VOUT 5V COUTA 2.5A 47µF CFB 22pF COUTB 47µF R2A 40.2k PGND BOOST LTC3626 PGOOD INTVCC RT SW TSET TMON VON IMONIN IMONOUT FB TRACK/SS ITH MODE/SYNC SGND CBSTA 0.1µF CBSTB 0.1µF L1B 1.5µH R1B 294k R2B 40.2k PGND VOUT –5V 1.2A 3626f 24 LTC3626 TYPICAL APPLICATIONS 5V Input to 2.5V Output at 1MHz Synchronized Frequency with Input Current Monitor and 475mA Input Current Limit VIN 5V C4 2.2µF RCOMP 13k CCOMP 220pF RIIN 40.2k C1 47µF RPGD 100k CIIN 1µF PVIN SVIN RUN BOOST LTC3626 TRACK/SS INTVCC RT SW TSET IMONOUT VON TMON PGOOD FB ITH IMONIN MODE/SYNC SGND PGND CBST 0.1µF L1 2.2µH R1 127k CF 22pF COUT 47µF VOUT 2.5V 2.5A R2 40.2k EXTERNAL CLOCK 3626 TA03 3626f 25 LTC3626 TYPICAL APPLICATIONS 12V Input to 5V Output and 500mA Charger for Battery Backup System VIN 12V TO 20V CIN1 47µF PVIN SVIN RUN BOOST LTC3626 CVCC1 2.2µF RPG1 100k INTVCC TRACK/SS TMON TSET RT ITH MODE/SYNC IIN IOUT SW VON CBST1 0.1µF L1 1µH 5V RON 0Ω CF1 22pF FB RFB1 110k COUT1 47µF 4.2V RFB3 15k D1 GRN R1 1k PGOOD SGND PGND D5 CIN2 47µF CHARGE CONTROL CVCC2 2.2µF RPG2 100k PVIN SVIN BOOST LTC3626 RUN VON INTVCC TRACK/SS TMON TSET RT ITH MODE/SYNC IIN SW CBST2 0.1µF RD1 200Ω L2 1µH FB IOUT RD2 1k LTC4415 STAT1 IN1 WARN1 EN1 CLIM1 WARN2 CLIM2 STAT2 OUT1 EN2 CF2 220pF PGOOD SGND D2 D3 RED GRN RFB2 1.15M COUT2 47µF + Li-Ion BATTERY 4.2V IN2 OUT2 GND R3 1k D4 RED R2 1k R4 1k 14 13 12 11 COUT3 10µF SYSTEM LOAD 3626 TA05 COUT4 10µF RFB4 191k RIOUT 38.3k CIOUT 1µF PGND 3626f 26 LTC3626 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UDC Package 20-Lead Plastic QFN (3mm × 4mm) (Reference LTC DWG # 05-08-1742 Rev Ø) 0.70 ±0.05 3.50 ± 0.05 2.10 ± 0.05 1.50 REF 2.65 ± 0.05 1.65 ± 0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.50 REF 3.10 ± 0.05 4.50 ± 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 3.00 ± 0.10 0.75 ± 0.05 1.50 REF 19 R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.25 × 45° CHAMFER 20 0.40 ± 0.10 1 PIN 1 TOP MARK (NOTE 6) 4.00 ± 0.10 2 2.65 ± 0.10 2.50 REF 1.65 ± 0.10 (UDC20) QFN 1106 REV Ø 0.200 REF 0.00 – 0.05 R = 0.115 TYP 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3626f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC3626 TYPICAL APPLICATION 12V Input to 1.8V Output, 2.5A Regulator with Digital Output Current Monitoring VIN 12V C1 47µF 0.1µF C4 2.2µF 0.1µF 0.1µF REFOUT COMP VCC SCK SDO CS RPGD 200k IN CIOUT 1µF LTC2460 GND C2 1µF RIOUT 5.1k PVIN SVIN RUN BOOST LTC3626 INTVCC SW ITH TRACK/SS VON TSET TMON FB IMONIN RT PGOOD IMONOUT MODE/SYNC SGND PGND CBST 0.1µF L1 1.5µH CF 22pF R1 40.2k RT 324k COUT 47µF VOUT 1.8V 2.5A R2 20k 3626 TA04 REF– RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3601 15V, 1.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 4.5V to 15V, VOUT(MIN) = 0.6V, IQ = 300µA, ISD < 1µA, 4mm × 4mm QFN-20, MSOP-16E LTC3603 15V, 2.5A (IOUT), 3MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 4.5V to 15V, VOUT(MIN) = 0.6V, IQ = 75µA, ISD < 1µA, 4mm × 4mm QFN-20, MSOP-16E LTC3633 15V, Dual 3A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 3.6V to 15V, VOUT(MIN) = 0.6V, IQ = 500µA, ISD < 15µA, 4mm × 5mm QFN-28, MSOP-28E LTC3605A 20V, 5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 4V to 20V, VOUT(MIN) = 0.6V, IQ = 2mA, ISD < 15µA, 4mm × 4mm QFN-24 LTC3604 15V, 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 3.6V to 15V, VOUT(MIN) = 0.6V, IQ = 300µA, ISD < 15µA, 3mm × 3mm QFN-16, MSOP-16E 3626f 28 Linear Technology Corporation LT 0712 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2012