NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems General Description Features The NM95MS16 is the smaller of a family of devices designed to provide complete Plug and Play Capability for ISA bus systems. The NM95MS16 includes the necessary state machine logic to manage the Plug and Play protocol in addition to switches for steering Interrupt and DMA requests. It also features a built-in 2 kbits of serial EEPROM for storing the resource data specified in the Plug and Play Standard. In addition, 4 kbits of EEPROM is available for use by other on-board logic. This device provides a “truly complete” single-chip solution for implementing Plug and Play on ISA-Bus Adapter cards. The NM95MS16 supports one logical device with a flexible choice of DMA/IRQ selection and I/O Chipselect generation as well as offering 16-bit addressing in Mode 1. ■ Complete Implementation of Plug and Play Standard — Direct interface to ISA bus ■ Two modes of operation — DMA mode — Extended Interrupt mode (Windows® 95 logo compatible) ■ 6 or 8 ISA bus interrupt lines and 2 DRQ/DACK lines supported ■ On-chip EEPROM for resource request table ■ Additional 4 kbits of on-chip EEPROM available for external access ■ 24 mA Drivers for Data outputs NM95MS16 is implemented using Fairchild’s Advanced CMOS process and operates single power supply. The NM95MS16 is available in a 48-pin TQFP package and 52-pin PLCC package. ■ Complete compliance to ISA PnP specification (Ver. 1.0A) ■ 48-Pin TQFP, and 52-Pin PLCC Packages Block Diagram Osc. Rstdrv State Machine EEPROM MICROWIRE Port Decoder & Control Register Block Data Buffer From ISA Bus Address Control SD<0:7> ISA Bus Address From ISA Bus Control Function Module Support Logic DACKx* LIRQx LDRQx IOCS<0:2>* LDACKx* IRQx DRQx To ISA Bus DS012601-1 Windows® 95 is a registered trademark of Microsoft Corporation. © 1998 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems July 1998 4 RSTDRV 5 IOCS0* 6 IOCS1* 7 IORD* 8 VCC 9 IOWR* 10 DRQIN/SA15 IRQIN1/SA14 11 GND IRQIN0 12 DACKOUT*/IOCS2* IRQOUT5 Commercial Temperature Range (0°C to +70°C) 3 2 1 SD7 IRQOUT4 13 48 IRQOUT3 14 47 SD6 IRQOUT2 15 46 SD5 IRQOUT1 16 45 SD4 IRQOUT0 17 44 SD3 ISADRQ0/IRQOUT6 18 43 SD2 ISADRQ1/IRQOUT7 19 42 SD1 ISADACK0*/SA12 20 41 SD0 ISADACK1*/SA13 21 40 OSC CS 22 39 AEN SK 23 38 DO SA0 24 37 DI 30 31 32 33 34 35 36 SA7 SA8 SA9 SA10 SA11 SA3 29 SA6 SA2 28 SA5 27 SA4 26 GND 25 SA1 NM95MS16 (TQFP) DS012601-2 DRQIN/ISA15 NC VCC 3 2 1 52 51 RSTDRV DACKOUT*/IOCS2* 4 IOCS1* GND 5 IOCS0* IRQIN1/SA14 6 IORD* IRQIN0 7 IOWR* IRQOUT5 Order Number NM95MS16VBH IRQOUT4 8 50 49 48 47 46 SD7 IRQOUT3 9 45 SD6 IRQOUT2 10 44 SD5 IRQOUT1 11 43 SD4 IRQOUT0 12 ISADRQ0/IRQOUT6 13 NM95MS16 (PLCC) 42 SD3 41 SD2 40 NC SD1 ISADACK0*/SA12 16 38 SD0 ISADACK1*/SA13 17 37 OSC CS 18 36 AEN SK 19 35 DO SA11 SA10 34 30 31 32 33 SA9 28 29 SA7 NC SA5 24 25 26 27 GND 22 23 SA3 20 21 SA1 SA0 SA8 39 SA6 15 SA4 14 SA2 NC ISADRQ1/IRQOUT7 DI DS012601-3 Order Number NM95MS16V 2 www.fairchildsemi.com NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems Connection Diagrams Signals Type Description SA<11:0> I Address inputs from the ISA bus. IORD* I I/O read strobe from the ISA bus. IOWR* I I/O write strobe from the ISA bus. AEN I Address Enable from ISA Bus —used in conjunction with DMA. SD<7:0> I/O Data bus —lower byte —from/to the ISA bus. OSC (Note 1) I “OSC” clock from the ISA bus —used for internal state machines. RSTDRV I Reset input from the ISA bus. CS I Chip select for Microwire port. There should be a pull down resistor of 4.7k on CS pin if unused externally, or directly connected to GND. SK, DI I Clock and Data input lines for Microwire bus connection to access a portion (4k) on chip EEPROM. DO O Data output line for the Microwire interface detailed above. IRQOUT<5:0> O Connection to ISA bus interrupt request pins. On-chip interrupt request(s) may be connected to any 6 of the ISA IRQ lines. IRQIN<1:0> I Interrupt request from on-board logic DRQin/SA<15> I DMA request from on-board logic, or Address input from ISA bus depending on mode selected. DACKOUT* /IOCS2* O DMA Acknowledge for on-board logic or Programmable chipselect (2) depending on mode selected. ISADRQ<1:0>/IRQOUT<7:6> O Connection for two ISA bus DMA Request lines, or additional interrupt request lines depending on the mode selected. ISADACK<1:0>*/SA<13:12> I DMA Acknowledge from the ISA bus or additional address lines depending on the mode selected. IOCS<1:0>* O Programmable chip selects to address on-board peripheral. IRQIN<1>/SA<14> I Interrupt request from on board logic or Address input from ISA bus depending on mode selected. *Signal name with a “*” means its an active low signal. Note 1: “OSC” clock from ISA Bus is fixed at a standard frequency of 14.318 MHz. NM95MS16 is designed and tested for 14.318 MHz. However NM95MS16 can handle frequencies up to 24 MHz though it is not 100% tested. 3 www.fairchildsemi.com NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems Connection Diagrams (Continued) Mode 00 = DMA Mode; Mode 01 = Extended Interrupt Mode TQFP Pin DMA Mode Ext.Intr.Mode TQFP Pin DMA Mode Ext.Intr.Mode 1 RSTDRV RSTDRV 25 SA1 SA1 2 IOCS1* IOCS1* 26 SA2 SA2 3 IOCS0* IOCS0* 27 SA3 SA3 4 IORD* IORD* 28 SA4 SA4 5 IOWR* IOWR* 29 GND GND Note: 6 VCC VCC 30 SA5 SA5 7 DRQIN SA15 31 SA6 SA6 8 DACKOUT* IOCS2* 32 SA7 SA7 9 GND GND 33 SA8 SA8 10 IRQIN1 SA14 34 SA9 SA9 11 IRQIN0 IRQIN0 35 SA10 SA10 12 IRQOUT5 IRQOUT5 36 SA11 SA11 13 IRQOUT4 IRQOUT4 37 DI DI 14 IRQOUT3 IRQOUT3 38 DO DO 15 IRQOUT2 IRQOUT2 39 AEN AEN 16 IRQOUT1 IRQOUT1 40 OSC OSC 17 IRQOUT0 IRQOUT0 41 SD0 SD0 18 ISADRQ0 IRQOUT6 42 SD1 SD1 19 ISADRQ1 IRQOUT7 43 SD2 SD2 20 ISADACK0* SA12 44 SD3 SD3 21 ISADACK1* SA13 45 SD4 SD4 22 CS CS 46 SD5 SD5 23 SK SK 47 SD6 SD6 24 SA0 SA0 48 SD7 SD7 Mode selection (00 or 01) is done by setting MS bits in the EEPROM configuration register. Detailed information about this is described in User’s Guide. 4 www.fairchildsemi.com NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems Pinout Details for the NM95MS16 Operating Conditions Ambient Storage Temperature Ambient Operating Temperature NM95MS16 -65°C to +150°C All Input or Output Voltages with Respect to Ground VCC + 1V to -0.3V Lead Temperature (Soldering, 10 seconds) +300°C ESD Rating 0°C to +70°C Positive Power Supply (VCC) 4.5V to 5.5V 2000V Min DC Electrical Characteristics Symbol Parameter Test Conditions Min ICCA Active Power Supply Current fSCL = 100 kHz ILI Input Leakage Current VIN = GND or VCC ILO Output Leakage Current VOUT = GND to VCC Limits Typ (Note 3) 0.2 VIL Input Low Voltage -0.1 VIH Input High Voltage 2.0 VOL Output Low Voltage IOL = 24 mA (Note 5) IOL = 2.1 mA (Note 6) VOH Output High Voltage IOH = -3 mA (Note 5) IOH = -400 µA (Note 6) 0.8 Units Max 15 mA 15 µA 15 µA V VCC + 1.0 V 0.4 V 2.4 2.4 V V Capacitance TA = +25°C, f = 1.0 MHz, VCC = 5V Symbol Test Conditions Max Units CI/O (Note 4) Input/Output Capacitance VI/O = 0V 8 pF CIN (Note 4) Input Capacitance VIN = 0V 6 pF COUT (Note 4) Output Capacitance VOUT = 0V 6 pF Note 2: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 3: Typical values are for TA = 25°C and nominal supply voltage (5V). Note 4: This parameter is periodically sampled and not 100% tested. Note 5: These values are for ISA signals like SD[0:7], IRQx, DRQx. Note 6: These values are for card signal like IOCS[0:3]*, DO(EEPROM). AC Electrical Characteristics Symbol Parameter Min Max Unit tAEN AEN Valid to Command Active 100 ns tAC Address Valid to Command Active 88 ns tRVD Active Read to Valid Data tAH Address, AEN Hold from Inactive Command tRDH Read Data Hold from Inactive Read tWD Write Data Valid before Write Active 22 ns tWDH Write Data Hold after Write Inactive 25 ns tCSA Chip Selects Valid from Address Valid 5 25 ns tCSC Chip Selects Valid from Command Active 5 25 ns tIDD Propagation Delay for IRQ/DRQ/DACK 5 25 ns 200 30 5 5 ns ns ns www.fairchildsemi.com NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems Absolute Maximum Ratings (Note 2) Timings for ISA Read/Write Cycle AEN tAH tAEN SA[0:11] VALID ADDRESS tAC IORD* IOWR* READ DATA SD[0:7] tRDH tRVD VALID tWD WRITE DATA SD[0:7] tWDH DS012601-4 Decode Delay for Chipselect Generation tCSA tCSA SA[0:11] VALID ADDRESS IOCS[0:1]* (addr decode only) tCSC tCSC IORD* IOWR* IOCS[0:1]* (Qualified with CMD) DS012601-5 Propagation Delay for IRQ/DRQ/DACK IRQin DRQin ISADACK tIDD tIDD IRQout DRQout DACKout DS012601-6 (Refer to the NM95MS16 User’s guide for detailed information). Each of these modes are discussed below. INTRODUCTION The NM95MS16 is a single-chip solution for the ISA Plug and Play (PnP) specification. It implements the complete state machine and the necessary logic for supporting configurable Interrrupts and DMA channels on the ISA bus for one logical device. Apart from providing “PnP” capability, it has built-in EEPROM that eliminates external EEPROM. This device is available in a space saving 48-pin Thin Quad Flat Pack (TQFP) package. DMA Mode In the DMA mode, support is provided for 1. One on-board DMA request that is switchable to any two DMA channels on the ISA bus. 2. Two on-board interrupt request lines switchable to any six IRQ lines on the ISA bus. Functional Description 3. Two programmable I/O chip selects for on-board logic. NM95MS16 has two modes of operation, viz, “DMA mode” and “Extended Interrupt mode”. These modes are programmed using the mode select (MS) bits in one of the configuration registers Figure 1 shows a Block Diagram of NM95MS16 configured for DMA Mode. 6 www.fairchildsemi.com NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems Timing Diagrams FUNCTION MODULE SCSI/MODEM/ETHERNET CONTROLLERS IRQIN0 IRQIN1 2 DRQIN DACKOUT* 2 IOCS[0:1] CS,SK,DI 3 NM95MS16 2 EEPROM (DMA Mode) DO RSTDRV OSC SA[0:11] 12 SD[0:7] 8 IORD* IOWR* 3 AEN IRQOUT 6 [0:5] DRQ 2 [0:1] DACK 2 [0:1] ISA BUS DS012601-7 FIGURE 1. Extended Interrupt Mode In the Ext.Int. mode, support is provided for: 1. Two on-board interrupt request lines switchable to any eight IRQ lines on the ISA bus. 2. Three programmable I/O chip selects for on-board logic. 3. ISA address SA12–SA15 are also included for extended decode. Figure 2 shows a Block Diagram of NM95MS16 configured for Extended Interrupt Mode. FUNCTION MODULE SERIAL I/O /MULTI-MEDIA CONTROLLERS IRQIN0 1 4 IOCS[0:2] CS,SK,DI NM95MS16 2 (Extended Interrupt Mode) 3 EEPROM DO RSTDRV OSC SA[0:15] 16 SD[0:7] 8 IORD* IOWR* 3 AEN IRQOUT 8 [0:7] ISA BUS DS012601-8 FIGURE 2. NM95MS16 has 6 kbits of EEPROM on chip. All the PnP resource data structure for the logical device is stored in this EEPROM. Of the 6 kbits, 4 kbits are available for the logical device’s external usage. The logical device can access the EEPROM through a microwire port, which is essentially a 4-wire serial bus. The pins CS, SK, DI and DO follow the exact timing as the standard microwire bus and are compatible to the NM93Cxx family of EEPROMs. Chipselect Generation Individual I/O chipselect can be generated in the following two ways: A) Address Decode only B) Address Decode qualified by Command (IORD*, IOWR*). On-Chip EEPROM 7 www.fairchildsemi.com NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems INTRODUCTION (Continued) 0xF1. The Ninth bit of address for 6 kbits of memory is provided through the register at address 0xF0. Both read write are possible. The actual operation does not begin until Go Ahead (GA) bit is set. Programming a word takes approximately 10 ms. The status of the operation can be polled by the Status bit. This bit is set when the operation is in progress and will be reset when complete. The register at address 0xF0 is COMMAND register. This is the handshake register in programming the EEPROM and is explained below in a tabular format. EEPROM Programming The entire 6 kbits of EEPROM can be programmed through the ISA bus. The EEPROM can be programmed by putting the device (NM95MS16) in the Config. state (as defined in the PnP standard). Under this state 4 registers at address 0xF0–0xF3 are accessible to program the EEPROM. The data to be programmed is loaded in register at address 0xF3 and 0xF2 (LSB and MSB respectively). The address to be programmed is loaded in register at address COMMAND Register Address Register 0xF0 0xF1 Bit[1:0] —OP Code bits 10 - Read operation 01 - Write operation 11 - Erase operation Bit[2] —GA(Go ahead bits) Bit[6:3] Bit[7] If set to 1 the programming will continue. —Reserved, should be 0. —It provides A8 of the address. A[0:7] is provided by 0xF1 reg. (Note 7) AddressRegister [A0–A7] Data Register 0xF2 Data Byte [MSB] Data Register 0xF3 Data Byte [LSB] STATUS Register 0x05 Bit[0] —Status/Busy bit. “0” if busy, “1” is done. Note 7: The PNP resource data portion of the internal memory is at high address. Hence to program that portion, bit [7] of register 0xF0 (Address A8) should be set to “1”. 8 www.fairchildsemi.com NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems INTRODUCTION (Continued) 0.750 - 0.756 [19.05 - 19.20] 0.013–0.021 TYP [0.33–0.53] Pin 1 IDENT 7 1 52 45° X 0.045 [1.14] 45°X0.045 [1.14] 47 46 8 0.026–0.032 TYP [0.66–0.81] 0.690–0.730 TYP [17.53–18.54] 34 20 21 33 0.020 MIN TYP [0.51] 0.050 TYP [1.27] 0.600 [15.24] 0.785 - 0.795 [19.94 - 20.19] 0.090–0.130 TYP [2.29–3.30] TYP 0.165–0.180 TYP [4.19–4.57] 52-Lead Molded Plastic Leaded Chip Carrier Package Number V52A Order Number NM95MS16V 9 www.fairchildsemi.com NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems Physical Dimensions inches (millimeters) unless otherwise noted 9.0 ± 0.25 Typ 12° Top and Bottom 1.0 36 25 37 0° Min R 0.08 – 0.20 Gage plane 24 1.6 MAX 0.25 0°- 7° Seating Plane 0.08 48 13 1 Pin #1 Ident DETAIL A Typical 0.60 ±0.15 0.05 - 0.10 0.20 Min 12 0.5 Typ. Optional: Sharp corners except Pin #1 Ident corner See Detail A 1.40 ±0.05 0.125 Typ 7.0 ±0.1 TQFP Package (VBH) Package Number VBH48A Order Number NM95MS16VBH Life Support Policy Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Français Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1 Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383 Fairchild Semiconductor Japan Ltd. 4F, Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 10 www.fairchildsemi.com NM95MS16 Plug and Play Front-End Devices for ISA-BUS Systems Physical Dimensions inches (millimeters) unless otherwise noted