MICREL MIC94002BLM

MIC94002
Micrel
MIC94002
Dual P-Channel MOSFET
Not Recommended for New Designs
General Description
Features
The MIC94002 contains two silicon gate P-channel MOSFETs
designed for low on-resistance, high-side switch applications.
The MIC94002 has a maximum on-resistance of 0.4Ω at 4.5V
gate-to-source voltage. On-resistance can also be reduced
to half by connecting both MOSFETs in parallel.
Improved ESD protection is provided by the gate protection
network shown in the schematic diagram.
The MIC94002 is supplied in a low-profile version of the
8-lead SOIC package.
The MIC94002 can be assembled with the body not shorted
to the sources for use in analog switch applications. Contact
the factory for more information.
• 15V minimum drain-to-source breakdown
• 0.4Ω maximum on-resistance at
4.5V gate-to-source voltage (each MOSFET)
• Functional at 2.7V gate-to-source voltage
• 0.063" maximum height
Applications
•
•
•
•
High-side switch
Power management
Stepper motor control
1.8" PCMCIA disk drive VCC switch
Ordering Information
Part Number
Temperature Range*
Package
–55°C to +150°C
8-lead SOIC†
MIC94002BLM
* Operating Junction Temperature
† Low Profile Leads, see Package Information
Schematic Information
Pin Configuration
Source
Gate 1
Gate 2
1
S‡
D1 8
2
G1
D1 7
Schematic Symbols
3
S‡
D2 6
S‡
4
G2
D2 5
Drain 1
Drain 2
S‡
G1
G2
D1
6
8-lead Low-Profile
SOIC Package (LM)
D2
Schematic Diagram
Typical Application
Package Information
0.026 (0.65)
MAX)
S‡
D1
G1
On
Off
S‡
D2
G2
On
Off
74HC04
‡
0.050 (1.27) 0.016 (0.40)
TYP
TYP
0.193 (4.90)
45°
3°–6°
0.063 (1.60) MAX
common source
0.057 (1.45)
0.049 (1.25)
Dual Power Switch Application
Patent 5,355,008
August 1998
Pin 1
0.154 (3.90)
Load 2
1/2 MIC94002
Load 1
1/2 MIC94002
+5V
6-39
0.197 (5.0)
0.189 (4.8)
SEATING
PLANE
0.244 (6.20)
0.228 (5.80)
MIC94002
Micrel
Absolute Maximum Ratings
Voltage and current values are negative. Signs not shown for clarity.
Drain-to-Source Voltage ................................................ 15V
Gate-to-Source Voltage ................................................ 15V
Continuous Drain Current (each MOSFET, both on)
TA = 25°C ................................................................. 1.2A
TA = 100°C ............................................................... 0.7A
Operating Juction Temperature ................. –55°C to +150°
Storage Temperature ............................... –55°C to +150°C
Total Power Dissipation
TA = 25°C ................................................................... 1W
TA = 100°C .............................................................. 0.4W
Thermal Resistance
θJA ...................................................................................... 125°C/W
θJC ........................................................................................ 76°C/W
Lead Temperature
1/16" from case, 10s ........................................... +300°C
Electrical Characteristics Note 1 TA = 25°C unless noted.
All values are negative. Signs not shown for clarity.
Symbol
Parameter
Condition
Min
VBDSS
Drain-Source Breakdown Voltage
VGS = 0V, ID = 250µA
15
VGS
Gate Threshold Voltage
VDS = VGS, ID = 250µA
1
IGSS
Gate-Body Leakage
IDSS
Zero Gate Voltage Drain Current
Typ
Units
V
3
V
VDS = 0V, VGS = 15V, Note 3
100
nA
VDS = 15V, VGS = 0V
25
µA
VDS = 15V, VGS = 0V, TJ = 125°C
250
µA
ID(ON)
On-State Drain Current
VDS ≥ 10V, VGS = 10V, Note 2
5.5
RDS(ON)
Drain-Source On-State Resist.
VGS = 4.5V, ID = 50mA
0.35
gFS
Forward Transconductance
VDS = 15V, ID = 1A, Note 2
0.7
Note 1
Max
A
0.40
Ω
S
Values for each MOSFET
Note 2
Pulse Test: Pulse Width ≤ 300µs, Duty Cycle ≤ 2%
Note 3
ESD gate protection diode conducts during positive gate-to-source voltage excursions.
Typical Characteristics
On Resistance vs.
Drain Current
2000
0.40
1800
0.35
1600
VGS = 4.5V
1400
0.30
1200
ID (mA)
RDS(ON) (Ω)
Drain Characteristics
0.45
0.25
0.15
VGS = 3.0
800
400
0.05
200
0.4
0.8
1.2
1.6
ID (A) Notes 1, 2
VGS = 2.5
VGS = 2.0
600
0.10
0.00
0.0
VGS = 3.5
1000
VGS = 10V
0.20
VGS = 4.0
0
0.0
2.0
6-40
VGS = 1.5
2.5
5.0
7.5 10.0 12.5 15.0
VDS (V) Notes 1, 2
August 1998