MICREL SM802123

SM802123
ClockWorks™ 125MHz/25MHz
Ultra-Low Jitter, LVCMOS
Frequency Synthesizer
General Description
Features
The SM802123 is a member of the ClockWorks™ family of
devices from Micrel and provides an extremely low-noise
timing solution. It is based upon a unique patented
RotaryWave® architecture that provides very-low phase
noise.
The device operates from a 2.5V or 3.3V power supply
and synthesizes 16 LVCMOS output clocks, eight at
125MHz and eight at 25MHz. The SM802123 accepts a
25MHz LVCMOS reference input.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
• Generates eight LVCMOS output clocks at 125MHz and
eight LVCMOS output clocks at 25MHz
• 2.5V or 3.3V operating range
• Typical phase jitter @ 125MHz
(1.875MHz to 20MHz): 115fs
• Industrial temperature range
• Green, RoHS, and PFOS compliant
• Available in 44-pin 7mm × 7mm QFN package
Applications
• Gigabit Ethernet – (GbE)
________________________________________________________________________________________________
Block Diagram Top Level Schematic
ClockWorks is a trademark of Micrel, Inc
RotaryWave is a registered trademark of Multigig, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
January 2012
M9999-012312-A
[email protected] or (408) 955-1690
Micrel, Inc.
SM802123
Ordering Information
Part Number
Marking
Shipping
Junction Temperature
Range(1)
Package
SM802123UMG
802123
Tray
–40°C to +85°C
44-Pin QFN
SM802123UMGTR
802123
Tape and Reel
–40°C to +85°C
44-Pin QFN
Note:
1. Devices are Green, RoHS, and PFOS compliant.
Pin Configuration
44-Pin QFN
(Top View)
Pin Description
Pin Number
Pin Name
Pin Type
Pin Level
Pin Function
25, 26
28, 29
32, 33
35, 36
Q1, Q2
Q3, Q4
/Q5, /Q6
/Q7, /Q8
O, (DIF)
LVCMOS
Clock Outputs from Bank 1 (25MHz) .
41, 42
1, 2
4, 5
7, 8
Q9, Q10
/Q11, /Q12
/Q13, /Q14
Q15, Q16
O, (DIF)
LVCMOS
Clock Outputs from Bank 2 (125MHz).
31, 37, 38
VDDO1
PWR
Power Supply for the Outputs on Bank 1.
43, 44, 16
VDDO2
PWR
Power Supply for the Outputs on Bank 2.
24, 39
VSSO1
PWR
Power Supply Ground for the Outputs on Bank 1.
PWR
Power Supply Ground for the Outputs on Bank 2.
3, 6, 40
VSSO2
11, 14, 18, 19,
20, 27, 30, 34
TEST
12, 13
VDD
10, 21, 23
January 2012
VSS (Exposed Pad)
Factory Test Pins. Do not connect anything to these pins.
PWR
Core Power Supply.
PWR
Core Power Supply Ground. The exposed pad must be
connected to the VSS ground plane.
2
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SM802123
Pin Description (Continued)
Pin Number
Pin Name
Pin Type
Pin Level
Pin Function
17
REF_IN
I, (SE)
LVCMOS
Reference Clock Input
9
PLL_BYPASS
I, (SE)
LVCMOS
PLL Bypass, Selects Output Source
0 = Normal PLL Operation
1 = Output from Input Reference Clock
45KΩ Pull-Down
15
OE1
I, (SE)
LVCMOS
Output Enable, Q1-/Q8 disables to tri-state,
0 = Disabled, 1 = Enabled, 45KΩ Pull-Up
22
OE2
I, (SE)
LVCMOS
Output Enable, Q9-Q16 disables to tri-state,
0 = Disabled, 1 = Enabled, 45KΩ Pull-Up
Truth Table
OE1/2
OUTPUTS
0
Tri-State
1
LVCMOS
January 2012
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SM802123
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VDD, VDDO1/2) ..................................... +4.6V
Input Voltage (VIN)……….……… ........... –0.5V to VDD+0.5V
Lead Temperature (soldering, 20s.) ........................... 260°C
Case Temperature ..................................................... 115°C
Storage Temperature (Ts) ......................... –65°C to +150°C
Supply Voltage (VDD, VDDO1/2) ............... +2.375V to +3.465V
Ambient Temperature (TA) .......................... –40°C to +85°C
(3)
Junction Thermal Resistance
QFN (θ JA)
Still-Air ............................................................... 24°C/W
QFN (ψ JB)
Junction-to-Board ................................................ 8°C/W
DC Electrical Characteristics(4)
VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%
VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V ±5%
TA = −40°C to +85°C
Symbol
VDD, VDDO1/2
IDD
Parameter
Condition
Min.
Typ.
Max.
Units
3.3V Operating Voltage
VDDO1 = VDDO2
3.135
3.3
3.465
V
2.5V Operating Voltage
VDDO1 = VDDO2
2.375
2.5
2.625
V
Total supply current
Outputs floating
130
170
mA
Max.
Units
LVCMOS INPUT (OE1, OE2, PLL_BYPASS) DC Electrical Characteristics(4)
VDD = 3.3V ±5%, or 2.5V ±5%, TA = −40°C to +85°C
Symbol
Parameter
Condition
Min.
Typ.
VIH
Input High Voltage
2
VDD + 0.3
V
VIN
Input Low Voltage
−0.3
0.8
V
IIH
Input High Current
VDD = VIN = 3.465V
150
μA
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
−150
μA
LVCMOS OUTPUT DC Electrical Characteristics(4)
VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%
VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V ±5%
TA = −40°C to +85°C. RL = 50Ω to VDDO/2
Symbol
Parameter
Condition
VOH
Output High Voltage
Figure 4
VOL
Output Low Voltage
Figure 4
Min.
Typ.
Max.
VDDO – 0.7
Units
V
0.6
V
Notes:
1.
Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
2.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3.
Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
4.
The circuit is designed to meet the AC and DC specifications shown in the above table after thermal equilibrium has been established.
January 2012
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SM802123
REF_IN DC Electrical Characteristics(4)
VDD = 3.3V ±5%, or 2.5V ±5%, TA = −40°C to +85°C
Symbol
Parameter
Condition
VIH
Input High Voltage
VIL
Input Low Voltage
IIN
Input Current
Min.
VIN = 0V to VDD
Typ.
Max.
Units
1.1
VDD + 0.3
V
−0.3
0.6
V
−5
5
μA
Max
Units
AC Electrical Characteristics(4, 5)
VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%
VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V ±5%
TA = −40°C to +85°C. RL = 50Ω to VDDO/2
Symbol
Parameter
FOUT
Output Frequency
TR/TF
LVCMOS Output Rise/Fall
Time
ODC
Output Duty Cycle
TLOCK
PLL Lock Time
Tjit(∅)
RMS Phase Jitter
(Output = 25MHz)
Condition
(6)
Min
Typ
Q1 – /Q8
25
Q9 – Q16
125
20% – 80%, Fig. 2
MHz
100
200
500
ps
45
50
55
%
20
ms
Integration Range:(12kHz – 5MHz)
5MHz limited by phase-noise system.
315
fs
RMS Phase Jitter (6)
(Output = 125MHz)
Integration Range:(12kHz – 20MHz)
340
fs
Integration Range:(1.875MHz – 20MHz)
115
fs
Spurious Noise Components
25MHz
−64
dBc
Notes:
1.
All phase-noise measurements were taken with an Agilent 5052B phase-noise system.
2.
REF_IN driven with a low-noise source ClockWorks
noise up to about 1MHz offset frequency.
January 2012
TM
SM802001 programmed for a 25MHz CMOS output. Phase noise will track the input phase
5
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SM802123
Phase Noise Plots
125MHz LVCMOS Integrated Jitter 12kHz – 20MHz 339fs
125MHz LVCMOS Integrated Jitter 1.875MHz – 20MHz 114fs
January 2012
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SM802123
Phase Noise Plots (Continued)
25MHz LVCMOS Integrated Jitter 12kHz – 5MHz 315fs
Input Source (25MHz LVCMOS) Programmed from a ClockworksTM Part
January 2012
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SM802123
Phase Noise Plots (Continued)
125MHz LVCMOS Output Waveform
25MHz LVCMOS Output Waveform
January 2012
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SM802123
Figure 2. All Outputs Rise/Fall Time
Figure 1. Duty Cycle TIming
Figure 4. LVCMOS Output Load and Test Circuit
Figure 3. RMS Phase Noise/Jitter
January 2012
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Micrel, Inc.
SM802123
Package Information
44-Pin Package Type (QFN)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical
implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel for any damages resulting from such use or sale.
© 2012 Micrel, Incorporated.
January 2012
10
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Micrel, Inc.
SM802123
Revision Template History
Date
Change Description/Edits by:
8/4/10
Added new paragraph to disclaimer in boiler plate. Per Colin Sturt. M.Galvan
January 2012
Rev.
11
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SM802123
HBW Datasheet Revision History
Part Number:
Initial Release Date:
Rev.
Date
Revisions
Reason
Engineer
A
January 2012
12
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