Micrel, Inc. HEX D FLIP-FLOP FEATURES ■ ■ ■ ■ ■ ■ DESCRIPTION Max. toggle frequency of 700MHz Clock to Q max. of 1200ps IEE min. of –98mA Industry standard 100K ECL levels Extended supply voltage option: VEE = –4.2V to –5.5V Voltage and temperature compensation for improved noise immunity Internal 75kΩ input pull-down resistors 50% faster than Fairchild 300K Better than 20% lower power than Fairchild Function and pinout compatible with Fairchild F100K Available in 28-pin PLCC package ■ ■ ■ ■ ■ SY100S351 SY100S351 The SY100S351 offers six D-type, edge-triggered, master/ slave flip-flops with differential outputs, and is designed for use in high-performance ECL systems. The flip-flops are controlled by the signal from the logical OR operation on a pair of common clock signals (CPa, CPb). Data enters the master when both CPa and CPb are LOW and transfers to the slave when either CPa or CPb (or both) go to a logic HIGH. The Master Reset (MR) input overrides all other inputs and takes the Q outputs to a logic LOW. The inputs on this device have 75kΩ pull-down resistors. BLOCK DIAGRAM PIN NAMES Pin D0 — D5 Function Data Inputs CPa, CPb Common Clock Inputs MR Asynchronous Master Reset Input Q0 — Q5 Data Outputs Q0 — Q5 Complementary Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs M9999-060910 [email protected] or (408) 955-1690 1 Rev.: I Amendment: /0 Issue Date: June 2010 SY100S351 Micrel, Inc. PACKAGE/ORDERING INFORMATION Ordering Information Part Number SY100S351JC SY100S351JCTR (1) Package Type Operating Range Package Marking Lead Finish J28-1 Commercial SY100S351JC Sn-Pb J28-1 Commercial SY100S351JC Sn-Pb SY100S351JZ(2) J28-1 Commercial SY100S351JZ with Matte-Sn Pb-Free bar-line indicator SY100S351JZTR(1, 2) J28-1 Commercial SY100S351JZ with Pb-Free bar-line indicator Matte-Sn Matte-Sn SY100S351JY(1) J28-1 Industrial SY100S351JY with Pb-Free bar-line indicator SY100S351JYTR(1,2) J28-1 Industrial SY100S351JY with Matte-Sn Pb-Free bar-line indicator Notes: 28-Pin PLCC (J28-1) 1.Tape and Reel. 2.Pb-Free package is recommended for new designs. TRUTH TABLES Asynchronous Operation(1) Inputs Synchronous Operation(1) Outputs Inputs Outputs Dn CPa CPb MR Qn (t+1) Dn CPa CPb MR Qn (t+1) X X X H L L u L L L H u L L H L L u L L H L u L H X H u L Qn(t) X u H L Qn(t) X L L L Qn(t) NOTE: 1.H = High Voltage Level L = Low Voltage Level X = Don't Care t = Time before CP Positive Transition t+1 = Time after CP Positive Transition u = LOW-to-HIGH Transition M9999-060910 [email protected] or (408) 955-1690 2 SY100S351 Micrel, Inc. DC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND Symbol Parameter Min. Typ. Max. Unit Condition IIH Input HIGH Current MR — — 270 D0 – D5 — — 200 CPa, CPb — — 300 µA VIN = VIH (Max.) Power Supply Current mA Inputs Open IEE –98 –71 –49 AC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND A = 0°C TA = +25°C TA = +85°C TA T = -40°C Symbol Parameter fMAX 700 Toggle Frequency Min. Max. Min. Max. Min. Max. 700 — 700 — Min. Max. Unit Condition 700 — tPLH tPHL MHz 1200 ps Propagation Delay — 1200 — 1200 — 1200 CPa, CPb to Output tPLH tPHL 1200 Propagation Delay MR to Output — 1200 — 1200 — ps 1200 tTLH tTHL Transition Time 300 900 20% to 80%, 80% to 20% 300 900 300 900 300 ps 900 tS Set-up Time 500 D0–D5 500 — 500 — 500 1000 MR (Release Time) 1000 — 1000 — 1000 tH Hold Time, D0–D5 550 550 — 550 — 550 — ps tPW (H) 1000 Pulse Width HIGH CPa, CPb, MR 1000 — 1000 — 1000 — ps M9999-060910 [email protected] or (408) 955-1690 3 ps — — SY100S351 Micrel, Inc. TIMING DIAGRAMS Propagation Delay (Clock) and Transition Times NOTE: VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND Propagation Delay (Resets) M9999-060910 [email protected] or (408) 955-1690 4 SY100S351 Micrel, Inc. TIMING DIAGRAMS Data Set-up and Hold Time Notes: 1.VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND 2.tS is the minimum time before the transition of the clock that information must be present at the data input. 3.tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. M9999-060910 [email protected] or (408) 955-1690 5 SY100S351 Micrel, Inc. 28-PIN PLCC (J28-1) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 web http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2006 Micrel, Incorporated. M9999-060910 [email protected] or (408) 955-1690 6