MICREL SY56572XRMGTR

SY56572XR
Low Voltage 1.2V/1.8V/2.5V CML
4:1 MUX with 1:2 FANOUT
6.4Gbps with EQUALIZATION
General Description
The SY56572XR is a fully differential, low voltage
1.2V/1.8V/2.5V CML 4:1 Mux, with input equalization,
and integrated 1:2 Fanout Buffer. The SY56572XR can
process clock signals as fast as 4.5GHz or data patterns
up to 6.4Gbps.
The differential input includes Micrel’s unique 3-pin input
termination architecture that interfaces to DC-coupled
2.5V/3.3V LVPECL, 1.2V/1.8V/2.5V CML or LVDS
differential signals. For AC-coupled input applications,
an internal voltage reference is provided for input bias.
Input voltages as small as 200mV (400mVpp) are applied
before the 9, 18 or 27-inch FR4 transmission line.
The SY56572XR operates from a 2.5V ±5% core supply
and a 1.2V, 1.8V or 2.5V ±5% output supply and is
guaranteed over the full industrial temperature range
(–40°C to +85°C). The SY56572XR is part of Micrel’s
®
high-speed, Precision Edge product line.
Data sheets and support documentation can be found
on Micrel’s web site at: www.micrel.com.
®
Precision Edge
Features
• 1.2V/1.8V/2.5V CML 4:2 MUX with input equalization.
• Guaranteed AC performance over temperature and
voltage:
– DC-to > 6.4Gbps throughput
– <360ps propagation delay (IN-to-Q)
– <15ps within-device skew
• Ultra-low jitter design
– <0.8psRMS random jitter
– <10psPP deterministic jitter
• 2.5V ±5% , 1.8/1.2V ±5% power supply operation
• Industrial temperature range: –40°C to +85°C
• Available in 32-pin (5mm x 5mm) QFN package
Functional Block Diagram
Applications
•
•
•
•
Data Distribution
SONET clock and data distribution
Fiber Channel clock and data distribution
Gigabit Ethernet clock and data distribution
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
April 2010
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Micrel, Inc.
SY56572XR
Ordering Information(1)
Part Number
Package
Type
Operating
Range
Package Marking
Lead
Finish
SY56572XRMG
QFN-32
Industrial
SY56572X with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
QFN-32
Industrial
SY56572X with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
(2)
SY56572XRMGTR
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
32-Pin QFN
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Pin Description
Pin Number
Pin Name
Pin Function
1,4
IN0, /IN0
5,8
IN1, /IN1
25,28
IN2, /IN2
29,32
IN3, /IN3
2
VT0
6
VT1
26
VT2
30
VT3
Input Termination Center-Tap: Each side of the differential input pair terminates to
the VT pin. This pin provides a center-tap to a termination network for maximum
interface flexibility. An internal high impedance resistor divider biases VT to allow
input AC coupling. For AC coupling, bypass VT with 0.1µF low ESR capacitor to
VCC. See “Input Interface Applications” subsection and Figure 2a.
19
EQ
Three level input for equalization control.
15
SEL0
18
SEL1
16,17
VCC
Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to
the VCC pin as possible. Supplies the input and core circuitry.
10,13,20,23
VCCO
Output Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the VCCO
pin as possible. Supplies the output buffers.
9,24
GND,
Ground: Exposed pad must be connected to a ground plane that is the same
potential as the ground pins.
Differential Inputs: Accepts differential signals as small as 200mV (400mVPP)
applied to the input of a 9, 18 or 27 inch 6mil FR4 stripline transmission line. See
“Input and Output Stage” section for details of this input.
Single-ended TTL/CMOS compatible input selects the inputs to the multiplexer. This
input is internally connected to a 25kΩ pull-up resistor and will default to a logic
HIGH state if left open. Input logic threshold is VCC/2. See “Truth Table” for select
control.
Exposed pad
12,11
Q0, /Q0
22,21
Q1, /Q1
CML Differential Output Pair: Differential buffered copy of the input signal. The
output swing is typically 390mV. See “Functional Description” subsection for
termination information.
Truth Table
EQ Input
Equalization FR4 6mil Stripline
LOW
9“
FLOAT
18”
HIGH
27”
April 2010
SEL1
SEL0
0
0
IN0 Input Selected
0
1
IN1 Input Selected
1
0
IN2 Input Selected
1
1
IN3 Input Selected
3
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SY56572XR
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VCC) ............................... –0.5V to +3.0V
Supply Voltage (VCCO) ............................. –0.5V to +3.0V
VCC -VCCO ................................................................ <1.8V
VCCO -VCC ............................................................... <0.5 V
Input Voltage (VIN) ............................. –0.5V to VCC+0.4V
CML Output Voltage (VOUT) ............................ 0.6V to 3V
Current (VT)
Source or sink on VT pin ............................. ±100mA
Input Current
Source or sink Current on (IN, /IN) ................ ±50mA
Maximum operating Junction Temperature .......... 125°C
Lead Temperature (soldering, 20sec.) .................. 260°C
Storage Temperature (Ts) .................... –65°C to +150°C
Supply Voltage (Vcc) ........................... 2.375V to 2.625V
(Vcco)………………..….1.14V to 2.625V
Ambient Temperature (TA) ................... –40°C to +85°C
(3)
Package Thermal Resistance
QFN
Still-air (θJA) ............................................ 50°C/W
Junction-to-board (ψJB) ......................... 20°C/W
DC Electrical Characteristics(4)
TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VCC
Power Supply Voltage Range
VCC
2.375
2.5
2.625
V
VCCO
1.14
1.2
1.26
V
VCCO
1.7
1.8
1.9
V
VCCO
2.375
2.5
2.625
V
ICC
Power Supply Current
Max. VCC
110
140
mA
ICCO
Power Supply Current
No Load. VCCO
32
42
mA
RDIFF_IN
Differential Input Resistance
(IN-to-/IN)
100
110
Ω
VIH
Input HIGH Voltage
(IN, /IN)
IN, /IN
1.2
VCC+0.4
V
VIL
Input LOW Voltage
(IN, /IN)
IN, /IN
0
VIH–0.2
V
VIN
Input Voltage Swing
(IN, /IN)
See Figure 3a, Note 5, applied to
input of transmission line.
0.2
1.0
V
VDIFF_IN
Differential Input Voltage Swing
(|IN - /IN|)
See Figure 3b, Note 5, applied to
input of transmission line.
0.4
2.0
V
VT_IN
Voltage from Input to VT
1.28
V
90
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for
extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. ψJB and θJA
values are determined for a 4-layer board in still-air number, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. VIN (max) is specified when VT is floating.
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SY56572XR
CML Outputs DC Electrical Characteristics(6)
VCCO = 1.14V to 1.26V RL = 50Ω to VCCO.
VCCO = 1.7V to 1.9V, 2.375V to 2.625V, RL = 50Ω to VCCO or 100Ω across the outputs.
VCC = 2.375V to 2.625V; TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
VOH
Output HIGH Voltage
RL = 50Ω to VCCO
VOUT
Output Voltage Swing
See Figure 3a
VDIFF_OUT
Differential Output Voltage Swing
See Figure 3b
ROUT
Output Source Impedance
Min
Typ
Max
Units
VCC-0.020
VCC-0.010
VCC
V
300
390
475
mV
600
780
950
mV
45
50
55
Ω
Min
Typ
Max
Units
VCC
V
LVTTL/CMOS DC Electrical Characteristics(6)
VCC = 2.375V to 2.625V; TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIH
Input HIGH Current
-125
IIL
Input LOW Current
-300
2.0
0.8
V
30
µA
µA
Three Level EQ Input DC Electrical Characteristics(6)
VCC = 2.375V to 2.625V; TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Max
Units
VIH
Input HIGH Voltage
Condition
VCC-0.3
VCC
V
VIL
Input LOW Voltage
0
VEE+0.3
V
IIH
Input HIGH Current
VIH = VCC
IIL
Input LOW Current
VIL = GND
Min
Typ
400
-480
µA
µA
Note:
6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
April 2010
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SY56572XR
AC Electrical Characteristics
VCCO = 1.14V to 1.26V RL = 50Ω to VCCO.
VCCO = 1.7V to 1.9V, 2.375V to 2.625V, RL = 50Ω to VCCO or 100Ω across the outputs.
VCC = 2.375V to 2.625V; TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
fMAX
Maximum Frequency
NRZ Data
6.4
Gbps
VOUT > 200mV (Clock)
4.5
GHz
Note 7, Figure 1a
210
tPD
Propagation Delay (IN-to-Q)
(SEL-to-Q)
tSkew
tJitter
tR tF
Min
Typ
280
Figure 1b
3
Max
Units
360
ps
1
ns
Output-to-Output Skew
Note 8
15
ps
Part-to-Part Skew
Note 9
100
ps
Data Random Jitter
Note 10
0.8
psRMS
Data Deterministic Jitter
Note 11
10
psPP
Output Rise/Fall Time
(20% to 80%)
At full output swing.
85
ps
Duty Cycle
Differential I/O
55
%
30
45
55
Notes:
7.
Propagation delay is measured with no attenuating transmission line connected to the input.
8.
Output-to-Output skew is the difference in time between both outputs under identical input transition, temperature and power supply
9.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
10. Random jitter is additive jitter.
11. Deterministic jitter is measured with 223–1 PRBS pattern.
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SY56572XR
Functional Description
CML Output Termination with Vcco 1.2V
For VCCO of 1.2V, Figure 5a, terminate the output with
50Ωto 1.2V, not 100Ω differentially across the outputs. If
AC coupling is used, Figure 5d, terminate into 50Ω to
1.2V before the coupling capacitor and then connect to a
high value resistor to a reference voltage. Any unused
output pair with VCCO at 1.2V needs to be terminated,
do not leave floating.
CML Output Termination with VCCO 1.8V, 2.5V
For VCCO of 1.8V or 2.5V, Figure 5a/b, terminate with
either 50Ω to 1.8V or 100Ω differentially across the
outputs. AC-or DC-coupling is fine. For best signal
integrity, terminate any unused output pairs.
Timing Diagrams
Figure 1a. IN-to-Q Timing Diagram
Figure 1b. SEL-to-Q Timing Diagram
(Qx state can be high or low depending on input data)
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SY56572XR
Input and Output Stage
Figure 2b. Simplified CML Output Buffer
Figure 2a. Simplified Differential Input Buffer
Single-Ended and Differential Swings
Figure 3b. Differential Swing
Figure 3a. Single-Ended Swing
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SY56572XR
Input Interface Applications
Figure 4a. CML Interface
100 Ω Differential
(DC-Coupled, 1.8V, 2.5V)
Figure 4b. CML Interface
50Ω-to-Vcc
(DC-Coupled, 1.2V,1.8V,2.5V)
Figure 4c. CML Interface
(AC-Coupled)
*See note in Functional Description
for 1.2V CML driver with AC-Coupling.
Figure 4d. LVPECL Interface
(AC-Coupled)
Figure 4e. LVPECL Interface
(DC-Coupled 2.5V and 3.3V)
Figure 4f. LVDS Interface
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SY56572XR
CML Output Termination
Figure 5a. 1.2V, 1.8V, 2.5V CML DC-Coupled Termination
Figure 5b. 1.8V, 2.5V CML DC-Coupled Termination
Figure 5c. CML AC-Coupled Termination.
VCCO 1.8V, 2.5V only.
April 2010
Figure 5d. CML AC-Coupled Termination.
VCCO 1.2V only.
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SY56572XR
Package Information
32-Pin QFN
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for
its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a
product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for
surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant
injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk
and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2010 Micrel, Incorporated.
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