5V/3.3V 32-175Mbps AnyRate® SY87700V SY87700V CLOCK AND DATA RECOVERY Use lower-power SY87700AL for 3.3V systems Micrel, Inc. FEATURES ■ 3.3V and 5V power supply options ■ SONET/SDH/ATM compatible ■ Clock and data recovery from 32Mbps up to 175Mbps NRZ data stream, clock generation from 32Mbps to 175Mbps ■ Two on-chip PLLs: one for clock generation and another for clock recovery ■ Selectable reference frequencies ■ Differential PECL high-speed serial I/O ■ Line receiver input: no external buffering needed ■ Link Fault indication ■ 100K ECL compatible I/O ■ Complies with Bellcore, ITU/CCITT and ANSI specifications such as OC-1, OC-3, FDDI, Fast Ethernet, as well as proprietary applications ■ Available in 32-pin EPAD-TQFP and 28-pin SOIC packages (28-pin SOIC is available, but not recommended for new designs, see page 2 for details) AnyRate® DESCRIPTION The SY87700V is a complete Clock Recovery and Data Retiming integrated circuit for data rates from 32Mbps up to 175Mbps NRZ. The device is ideally suited for SONET/SDH/ATM applications and other high-speed data transmission systems. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference. The SY87700V also includes a link fault detection circuit. Datasheets and support documentation can be found on Micrel’s web site at: www.micrel.com. APPLICATIONS ■ SONET/SDH/ATM OC-1/OC-3 ■ Fast Ethernet ■ Proprietary architectures up to 175Mbps BLOCK DIAGRAM PLLR P/N RDINP (PECL) RDINN RDOUTP (PECL) PHASE DETECTOR RDOUTN 0 1 CHARGE PUMP RCLKP (PECL) VCO RCLKN PHASE/ FREQUENCY DETECTOR LINK FAULT DETECTOR CD (PECL) REFCLK (TTL) PHASE/ FREQUENCY DETECTOR CHARGE PUMP VCO 1 LFIN (TTL) TCLKP (PECL) 0 TCLKN VCC VCCA VCCO GND DIVIDER BY 8, 10, 16, 20 SY87700V DIVSEL 1/2 (TTL) FREQSEL 1/2/3 (TTL) PLLS P/N AnyRate is a registered trademark of Micrel, Inc. M9999-073008 [email protected] or (408) 955-1690 CLKSEL (TTL) Rev.: L 1 Amendment: /0 Issue Date: July 2008 Micrel, Inc. SY87700V PACKAGE/ORDERING INFORMATION VCCA 1 28 VCC LFIN 2 Ordering Information(1) 27 CD Package Type Operating Range Package Marking Lead Finish Z28-1 Commercial SY87700VZC Sn-Pb Z28-1 Commercial SY87700VZC Sn-Pb H32-1 Commercial SY87700VHC Sn-Pb H32-1 Commercial SY87700VHC Sn-Pb Z28-1 Commercial SY87700VZH with NiPdAu Pb-Free bar line indicator Pb-Free SY87700VZHTR(2, 3, 4) Z28-1 Commercial SY87700VZH with NiPdAu Pb-Free bar line indicator Pb-Free SY87700VHH(3) H32-1 Commercial SY87700VHH with NiPdAu Pb-Free bar line indicator Pb-Free SY87700VHHTR(2, 3) H32-1 Commercial SY87700VHH with NiPdAu Pb-Free bar line indicator Pb-Free DIVSEL1 3 26 DIVSEL2 Part Number RDINP 4 25 RDOUTP SY87700VZC(3, 4) RDINN 5 24 RDOUTN SY87700VZCTR(2, 3, 4) 22 RCLKP SY87700VHC(3) 21 RCLKN SY87700VHCTR(2, 3) 20 VCCO SY87700VZH(3, 4) FREQSEL1 6 23 VCCO Top View SOIC Z28-1 & S28-1 REFCLK 7 FREQSEL2 8 FREQSEL3 9 N/C 10 19 TCLKP PLLSP 11 18 TCLKN PLLSN 12 17 CLKSEL GND 13 16 PLLRP GND 14 15 PLLRN 28-Pin SOIC (Z28-1) CD DIVSEL2 VCC VCC VCCA LFIN 31 30 29 28 27 26 25 VCCA DIVSEL1 32 Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. 4. For optimum reliability, care should be taken when using the Z28-1 SOIC package to maintain the package case temperature at or below 70°C. NC 1 24 RDOUTP RDINP 2 23 RDOUTN RDINN 3 FREQSEL1 4 22 VCCO REFCLK 5 FREQSEL2 6 FREQSEL3 7 18 TCLKP NC 8 17 TCLKN Top View EPAD-TQFP H32-1 21 RCLKP 20 RCLKN 19 VCCO 9 10 11 12 13 14 15 16 CLKSEL PLLRP GND PLLRN GND GNDA PLLSN PLLSP 32-Pin EPAD TQFP (H32-1) M9999-073008 [email protected] or (408) 955-1690 2 Micrel, Inc. SY87700V PIN DESCRIPTIONS INPUTS OUTPUTS RDINP, RDINN [Serial Data Input] Differential PECL. These built-in line receiver inputs are connected to the differential receive serial data stream. An internal receive PLL recovers the embedded clock (RCLK) and data (RDOUT) information. The incoming data rate can be within one of five frequency ranges depending on the state of the FREQSEL pins. See “Frequency Selection” Table. LFIN [Link Fault Indicator] TTL Output. This output indicates the status of the input data stream RDIN. Active HIGH signal is indicating when the internal clock recovery PLL has locked onto the incoming data stream. LFIN will go HIGH if CD is HIGH and RDIN is within the frequency range of the Receive PLL (1000ppm). LFIN is an asynchronous output. REFCLK [Reference Clock] TTL Inputs. This input is used as the reference for the internal frequency synthesizer and the “training” frequency for the receiver PLL to keep it centered in the absence of data coming in on the RDIN inputs. RDOUTP, RDOUTN [Receive Data Output] Differential PECL. These ECL 100K outputs (+3.3V or +5V referenced) represent the recovered data from the input data stream (RDIN). This recovered data is specified against the rising edge of RCLK. CD [Carrier Detect] PECL Input. This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. When this input is HIGH the input data stream (RDIN) is recovered normally by the Receive PLL. When this input is LOW the data on the inputs RDIN will be internally forced to a constant LOW, the data outputs RDOUT will remain LOW, the Link Fault Indicator output LFIN forced LOW and the clock recovery PLL forced to look onto the clock frequency generated from REFCLK. FREQSEL1, ..., FREQSEL3 [Frequency Select] TTL Inputs. These inputs select the output clock frequency range as shown in the “Frequency Selection” Table. RCLKP, RCLKN [Clock Output] Differential PECL. These ECL 100K outputs (+3.3V or +5V referenced) represent the recovered clock used to sample the recovered data (RDOUT). TCLKP, TCLKN [Clock Output] Differential PECL. These ECL 100K outputs (+3.3V or +5V referenced) represent either the recovered clock (CLKSEL = HIGH) used to sample the recovered data (RDOUT) or the transmit clock of the frequency synthesizer (CLKSEL = LOW). PLLSP, PLLSN [Clock Synthesis PLL Loop Filter] External loop filter pins for the clock synthesis PLL. PLLRP, PLLRN [Clock Recovery PLL Loop Filter] External loop filter pins for the receiver PLL. DIVSEL1, DIVSEL2 [Divider Select] TTL Inputs. These inputs select the ratio between the output clock frequency (RCLK/TCLK) and the REFCLK input frequency as shown in the “Reference Frequency Selection” Table. POWER & GROUND VCC VCCA VCCO GND N/C CLKSEL [Clock Select] TTL Inputs. This input is used to select either the recovered clock of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency synthesizer (CLKSEL = LOW) to the TCLK outputs. M9999-073008 [email protected] or (408) 955-1690 Note 1. 3 Supply Voltage(1) Analog Supply Voltage(1) Output Supply Voltage(1) Ground No Connect VCC, VCCA, VCCO must be the same value. Micrel, Inc. SY87700V FUNCTIONAL DESCRIPTION Lock Detect The SY87700V contains a link fault indication circuit which monitors the integrity of the serial data inputs. If the received serial data fails the frequency test, the PLL will be forced to lock to the local reference clock. This will maintain the correct frequency of the recovered clock output under loss of signal or loss of lock conditions. If the recovered clock frequency deviates from the local reference clock frequency by more than approximately 1000ppm, the PLL will be declared out of lock. The lock detect circuit will poll the input data stream in an attempt to reacquire lock to data. If the recovered clock frequency is determined to be within approximately 1000ppm, the PLL will be declared in lock and the lock detect output will go active. Clock Recovery Clock Recovery, as shown in the block diagram generates a clock that is at the same frequency as the incoming data bit rate at the Serial Data input. The clock is phase aligned by a PLL so that it samples the data in the center of the data eye pattern. The phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency detector. Output pulses from the detector indicate the required direction of phase correction. These pulses are smoothed by an integral loop filter. The output of the loop filter controls the frequency of the Voltage Controlled Oscillator (VCO), which generates the recovered clock. Frequency stability without incoming data is guaranteed by an alternate reference input (REFCLK) that the PLL locks onto when data is lost. If the Frequency of the incoming signal varies by greater than approximately 1000ppm with respect to the synthesizer frequency, the PLL will be declared out of lock, and the PLL will lock to the reference clock. The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET data signal. This transfer function yields a 30µs data stream of continuous 1’s or 0’s for random incoming NRZ data. The total loop dynamics of the clock recovery PLL provides jitter tolerance which is better than the specified tolerance in GR-253-CORE. M9999-073008 [email protected] or (408) 955-1690 4 Micrel, Inc. SY87700V CHARACTERISTICS Performance The SY87700V PLL complies with the jitter specifications proposed for SONET/SDH equipment defined by the Bellcore Specifications: GR-253-CORE, Issue 2, December 1995 and ITU-T Recommendations: G.958 document, when used with differential inputs and outputs. Jitter Transfer Jitter transfer function is defined as the ratio of jitter on the output OC-N/STS-N signal to the jitter applied on the input OC-N/STS-N signal versus frequency. Jitter transfer requirements are shown in Figure 2. Jitter Generation The jitter of the serial clock and serial data outputs shall not exceed .01 U.I. rms when a serial data input with no jitter is presented to the serial data inputs. Input Jitter Tolerance Input jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1dB optical/electrical power penalty. SONET input jitter tolerance requirement condition is the input jitter amplitude which causes an equivalent of 1dB power penalty. A Jitter Transfer (dB) Sinusoidal Input Jitter Amplitude (UI p-p) 0.1 15 -20dB/decade -20dB/decade 1.5 -20dB/decade Acceptable Range -20 0.40 f0 f1 f2 f4 ft fc Frequency Frequency OC/STS-N Level f0 (Hz) f1 (Hz) f2 (Hz) f3 (kHz) ft (kHz) OC/STS-N Level fc (kHz) P (dB) 3 10 30 300 6.5 65 3 130 0.1 Figure 1. Input Jitter Tolerance M9999-073008 [email protected] or (408) 955-1690 Figure 2. Jitter Transfer 5 Micrel, Inc. SY87700V FREQUENCY SELECTION TABLE(1) FREQSEL1 FREQSEL2 FREQSEL3 fVCO/fRCLK fRCLK Data Rates (Mbps) 0 1 1 6 125 –175 1 0 0 8 94 – 157 1 0 1 12 63 – 104 1 1 0 16 47 – 78 1 1 1 24 32 – 52 0 1 0 — undefined 0 X(Note 2) — undefined 0 Note 1. SY87700V operates from 32-175MHz. For higher speed applications, the SY87701V operates from 35-1250MHz. Note 2. X is a DON'T CARE. LOOP FILTER COMPONENTS(1) REFERENCE FREQUENCY SELECTION DIVSEL1 DIVSEL2 fRCLK/fREFCLK 0 0 8 0 1 10 1 0 16 1 1 20 R5 C3 PLLSP PLLSN Wide Range R5 = 350Ω C3 = 1.0µF (X7R Dielectric) R6 PLLRP C4 PLLRN Wide Range R6 = 680Ω C4 = 1.0µF (X7R Dielectric) Note 1. M9999-073008 [email protected] or (408) 955-1690 6 Suggested Values. Values may vary for different applications. Micrel, Inc. SY87700V ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Value Unit VCC Power Supply Voltage –0.5 to +7.0 V VIN Input Voltage –0.5 to VCC V IOUT Output Current mA – Continuous – Surge –65 to +150 °C Operating Temperature 0 to +85 °C Case Temperature 0 to +70 °C Tstore Storage Temperature TA TC Note 1. 50 100 Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to “Absolute Maximum Ratings” conditions for extended periods may affect device reliability. PACKAGE THERMAL DATA(1) θJA (°C/W) by Velocity (LFPM) Package(1, 2) 0 200 500 28-Pin SOIC(1, 2) 80 — — 32-Pin EP-TQFP(3) 27.6 22.6 20.7 Note 1. Case temperature not to exceed 70°C recommended for 28-pin SOIC. Note 2. 28-pin SOIC package is NOT recommended for new designs. Note 3. Using JEDEC standard test boards with die attach pad soldered to PCB. See www.amkor.com for additional package details. M9999-073008 [email protected] or (408) 955-1690 7 Micrel, Inc. SY87700V DC ELECTRICAL CHARACTERISTICS VCC = VCCO = VCCA = 3.3V ±5% or 5.0V ±5%, TA = 0°C to + 85°C for 32-TQFP, TC = 0°C to 70°C for SOIC. Symbol Parameter Min. Typ. Max. Unit VCC Power Supply Voltage 3.15 4.75 3.3 5.0 3.45 5.25 V V ICC Power Supply Current — 170 230 mA Condition PECL 100K DC ELECTRICAL CHARACTERISTICS VCC = VCCO = VCCA = 3.3V ±5% or 5.0V ±5%, TA = 0°C to + 85°C. Symbol Parameter Min. Typ. Max. Unit Condition VIH Input HIGH Voltage VCC –1.165 — VCC –0.880 V VIL Input LOW Voltage VCC –1.810 — VCC –1.475 V VOH Output HIGH Voltage VCC –1.075 — VCC –0.830 V 50Ω to VCC –2V VOL Output LOW Voltage VCC –1.860 — VCC –1.570 V 50Ω to VCC –2V IIL Input LOW Current 0.5 — — µA VIN = VIL(Min.) TTL DC ELECTRICAL CHARACTERISTICS VCC = VCCO = VCCA = 3.3V ±5% or 5.0V ±5%, TA = 0°C to + 85°C for 32-TQFP, TC = 0°C to 70°C for SOIC. Symbol Parameter Min. Typ. Max. Unit Condition VIH Input HIGH Voltage 2.0 — VCC V VIL Input LOW Voltage — — 0.8 V VOH Output HIGH Voltage 2.0 — — V IOH = –0.4mA VOL Output LOW Voltage — — 0.5 V IOL = 4mA IIH Input HIGH Current –125 — — — — +100 µA µA VIN = 2.7V, VCC = Max. VIN = VCC, VCC = Max. IIL Input LOW Current –300 — — µA VIN = 0.5V, VCC = Max. IOS Output Short Circuit Current –15 — –100 mA VOUT = 0V (maximum 1sec) AC ELECTRICAL CHARACTERISTICS VCC = VCCO = VCCA = 3.3V ±5% or 5.0V ±5%, TA = 0°C to + 85°C for 32-TQFP, TC = 0°C to 70°C for SOIC. Symbol Parameter Min. Typ. Max. Unit Condition 750 — 1250 MHz fREFCLK × Byte Rate Nominal fVCO VCO Center Frequency ∆fVCO VCO Center Freq. Tolerance — 5 — % tACQ Acquisition Lock Time — — 15 µs tCPWH REFCLK Pulse Width HIGH 4 — — ns tCPWL REFCLK Pulse Width LOW 4 — — ns tir REFCLK Input Rise Time — 0.5 2 ns tODC Output Duty Cycle (RCLK/TCLK) 45 — 55 % of UI tr tf ECL Output Rise/Fall Time (20% to 80%) 100 — 500 ps tSKEW Recovered Clock Skew –200 — +200 ps tDV Data Valid 1/(2×fRCLK) – 200 — — ps tDH Data Hold 1/(2×fRCLK) – 200 — — ps M9999-073008 [email protected] or (408) 955-1690 8 50Ω to VCC –2V Micrel, Inc. SY87700V TIMING WAVEFORMS tCPWL tCPWH REFCLK tODC tODC RCLK tSKEW tDV tDH RDOUT M9999-073008 [email protected] or (408) 955-1690 9 Micrel, Inc. SY87700V 32-PIN APPLICATION EXAMPLE R13 VCC LED D2 R12 Q1 2N2222A 26 DIVSEL2 27 CD 28 VCC 29 VCC 30 VCCA 31 VCCA 32 LFIN DIVSEL1 VEE DIODE D1 25 VCC NC 1N4148 R8 R9 FREQSEL1 2 REFCLK 3 FREQSEL2 CLKSEL FREQSEL3 DIVSEL1 5 NC 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 DIVSEL2 6 9 CD 7 10 15 VCCA (+2V) L1 C6 0.1 F C7 6.8 F C8 6.8 F C11 0.1 F C9 6.8 F C13 0.1 F C12 0.01 F C15 0.1 F C14 0.01 F C16 0.01 F GND C10 6.8 F C17 0.1 F C18 0.01 F VEE (—3V) VEE C19 1.0 F C21 0.01 F C20 0.1 F VEEA (—3V) Note: C3, C4 are optional C1 = C2 = 1.0µF R1 = 350Ω R2 = 680Ω R3 through R10 = 5kΩ R12 = 12kΩ R13 = 130Ω M9999-073008 [email protected] or (408) 955-1690 10 CLKSEL VCC (+2V) L2 PLLRP VEE C2 VCCO (+2V) L3 16 R2 R1 Ferrite Bead BLM21A102 C5 22 F 14 C4 C1 VCC 13 PLLRN GND VEE C3 12 VEEA SW1 11 PLLSN PLLSP R11 1kΩ RDINN 1 4 VEE R7 R6 R5 R3 R10 R4 RDINP RDOUTP RDOUTN VCCO RCLKP RCLKN VCCO TCLKP TCLKN Micrel, Inc. SY87700V SW1 GND 28-PIN APPLICATION EXAMPLE VCC 1 2 3 4 5 (R17 - R22) 5kΩ x 6 6 R8 130Ω 0.1 F FB1 22 F C9 GND 1 VCC R1 2 LFIN R2 C1 RDIN C2 R3 VCCA R4 See Table 1 GND 80Ω LOOP FILTER NETWORK 1.5 F REFCLK (TTL) 22 F C7 C6 J1 DIVSEL2 26 4 RDINP RDOUTP 25 5 RDINN RDOUTN 24 VCC R7 1kΩ 0.1 F 0.1 F C14 C15 7 REFCLK RCLKP 22 8 FREQSEL2 RCLKN 21 9 FREQSEL3 VCCO 20 10 N/C TCLKP 19 11 PLLSP TCLKN 18 12 PLLSN CLKSEL 17 0.1 F 0.1 F 13 GND PLLRP 16 14 GND PLLRN 15 C16 C17 0.1 F 0.1 F C18 C19 R6 If VCC = +5V: R9 through R14 = 330Ω Ω 50‰ C4 1.0 F If VCC = +3.3V: R9 through R14 = 220Ω VCC GND NC C5 DPDT Slide Switch XTAL Oscillator 14 0.1 F Pin 1 (VCCA) 0.1 F C10 1 Pin 28 (VCC) 0.1 F C13 8 VCC C11 7 Pin 23 (VCCO) 0.1 F C12 120Ω R21 C5 and C10–C12 are decoupling capacitors and should be kept as close to the power pins as possible. For AC-Coupling Only For DC Mode Only when VCC = +3.3V C1 = C2 = 0.1µF C1 = C2 = 0.1µF R1 = R2 = 1.2kΩ R3 = R4 = 3.4kΩ when VCC = +5V when VCC = +3.3V C1 = C2 = Shorted C1 = C2 = Shorted R1 = R2 = 680Ω R1 = R2 = 82Ω R1 = R2 = 130Ω R3 = R4 = 1kΩ R3 = R4 = 130Ω R3 = R4 = 82Ω Table 1. M9999-073008 [email protected] or (408) 955-1690 Pin 20 (VCCO) 0.1 F Note 1. when VCC = +5V Diode D1 1N4148 VCCO 23 R5 C3 C8 CD 27 3 DIVSEL1 6 FREQSEL1 Stand Off 0.1 F VCC 28 R11 R12 R13 R14 R15 R16 Capacitor Pads (1206 format) VCC Ferrite Bead BLM21A102 LED D2 11 Micrel, Inc. SY87700V BILL OF MATERIALS (32-PIN EPAD-TQFP) Item Part Number Manufacturer C1, C2 VJ0603Y105JXJAT Vishay 1.0µF Ceramic Capacitor, Size 1206 X7R Dielectric, Loop Filter, Critical 2 C3, C4 VJ0603Y105JXJAT Vishay 1.0µF Ceramic Capacitor, Size 1206 X7R Dielectric, Loop Filter, Optional 2 C5 ECS-T1ED226R Panasonic 22µF Tantalum Electrolytic Capacitor, Size D 1 C6 ECU-V1H104KBW Panasonic 0.1µF Ceramic Capacitor, Size 1206 X7R Dielectric, Power Supply Decoupling 1 C7, C8, C9, C10 ECS-T1EC685R Panasonic 6.8µF Tantalum Electrolytic Capacitor, Size C 4 C19 ECJ-3YB1E105K Panasonic 1.0µF Ceramic Capacitor, Size 1206 X7R Dielectric, VEEA Decoupling 1 C11, C13 ECU-V1H104KBW Panasonic 0.1µF Ceramic Capacitor, Size 1206 X7R Dielectric, VCCO/VCC Decoupling 1 C15, C17 ECU-V1H104KBW Panasonic 0.1µF Ceramic Capacitor, Size 1206 X7R Dielectric, VCCA/VEEA Decoupling 1 C20 ECU-V1H104KBW Panasonic 0.1µF Ceramic Capacitor, Size 1206 X7R Dielectric, VEEA Decoupling 1 C12, C14 ECU-V1H103KBW Panasonic 0.01µF Ceramic Capacitor, Size 1206 X7R Dielectric, VCCO/VCC Decoupling 1 C16, C18 ECU-V1H103KBW Panasonic 0.01µF Ceramic Capacitor, Size 1206 X7R Dielectric, VCCA/VEEA Decoupling 1 C21 ECU-V1H103KBW Panasonic 0.01µF Ceramic Capacitor, Size 1206 X7R Dielectric, VEEA Decoupling 1 D1 1N4148 Diode 1 D2 P300-ND/P301-ND T-1 3/4 Red LED 1 J1, J2, J3, J4, J5 J6, J7, J8, J9, J10, J11, J12 142-0701-851 Johnson Components Gold Plated, Jack, SMA, PCB Mount 12 L1, L2, L3 BLM21A102F Murata Ferrite Beads, Power Noise Suppression 3 Q1 NTE123A Panasonic Qty. 2N2222A Buffer/Driver Transistor, NPN 1 R1 350Ω Resistor, 2%, Size 0402 Loop Filter Component, Critical 1 R2 680Ω Resistor, 2%, Size 0402 Loop Filter Component, Critical 1 R3, R4, R5, R6 R7, R8, R9, R10 5kΩ Pullup Resistors, 2%, Size 1206 8 R11 1kΩ Pulldown Resistor, 2%, Size 1206 1 R12 12kΩ Resistor, 2%, Size 1206 1 R13 130Ω Pullup Resistor, 2%, Size 1206 1 SPST, Gold Finish, Sealed Dip Switch 1 SW1 206-7 M9999-073008 [email protected] or (408) 955-1690 NTE Description CTS 12 Micrel, Inc. SY87700V 28 LEAD SOIC .300" WIDE (Z28-1) Rev. 02 Note: The 28 Lead SOIC package is NOT recommended for new designs. M9999-073008 [email protected] or (408) 955-1690 13 Micrel, Inc. SY87700V 32 LEAD EPAD TQFP (DIE UP) (H32-1) Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 32-Pin EPAD-TQFP Package M9999-073008 [email protected] or (408) 955-1690 14 Micrel, Inc. SY87700V APPENDIX A Layout and General Suggestions 1. 2. 3. 4. 5. 6. 7. 8. Establish controlled impedance stripline, microstrip, or co-planar construction techniques. Signal paths should have, approximately, the same width as the device pads. All differential paths are critical timing paths, where skew should be matched to within ±10ps. Signal trace impedance should not vary more than ±5%. If in doubt, perform TDR analysis of all high-speed signal traces. Maintain compact filter networks as close to filter pins as possible. Provide ground plane relief under filter path to reduce stray capacitance. Be careful of crosstalk coupling into the filter network. Maintain low jitter on the REFCLK input. Isolate the XTAL oscillator from power supply noise by adequately decoupling. Keep XTAL oscillator close to device, and minimize capacitive coupling from adjacent signals. Higher speed operation may require use of fundamental-tone (third-overtone typically have more jitter) crystal based oscillator for optimum performance. Evaluate and compare candidates by measuring TXCLK jitter. All unused outputs must be terminated. To conserve power, unused PECL outputs can be terminated with a 1kΩ resistor to VEE. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB USA http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2006 Micrel, Incorporated. M9999-073008 [email protected] or (408) 955-1690 15