SY88149HL 3.3V 1.25Gbps Burst-Mode Limiting Amplifier with Ultra-Fast Signal Assert Timing General Description Features The SY88149HL is a high-sensitivity, burst-mode capable limiting post amplifier designed for Optical Line Terminal (OLT) receiver applications. The SY88149HL satisfies the strict timing restrictions of the GPON standards by providing ultra-fast Loss-of-Signal (LOS) or Signal-Detect (SD) output. Auto Reset and Manual Reset options are provided to control LOS/SD output timing. For increased flexibility, this device also includes an option to select between LOS or SD output. The device can be connected to burst-mode capable transimpedance amplifiers (TIAs) using AC or DC coupling. The SY88149HL generates a high-gain LOS or SD LVTTL output. A programmable LOS/SD level pin (LOS/SDLVL) sets the sensitivity of the input amplitude detection. This device also offers the option to choose between a Loss-ofSignal (LOS) and a Signal-Detect (SD) output from the LOS/SD pin based the LOS/SDSEL pin setting. To select SD output, leave LOS/SDSEL pin open or connect to Vcc; to select LOS output, tie LOS/SDSEL-to-ground. If the input signal amplitude falls below the threshold set by LOS/SDLVL, LOS will assert high (or SD will de-assert low). Once the input signal rises above the threshold set by LOS/SDLVL, LOS will de-assert low (or SD output will assert high). The SY88149HL also features a JAM function which, when active, disables the LVPECL outputs. JAM is active LOW when SD is selected and active HIGH when LOS is selected. The LOS/SD output should be fed back to the JAM input to maintain output stability under an invalid signal condition. Typically, 3dB SD hysteresis is provided to prevent chattering. The SY88149HL operates from a single +3.3V power o o supply over temperatures ranging from –40 C to +85 C. With its wide bandwidth and high gain, signals up to 1.25Gbps and as small as 4mVpp can be amplified to drive devices with LVPECL inputs. • Single 3.3V power supply • <5ns SD assert (LOS de-assert) time • Option to AUTORESET or Manual RESET LOS output to HIGH and SD output to LOW • Option to select LOS or SD output • Up to 1.25Gbps operation • Low-noise differential LVPECL data outputs • 4mVpp input sensitivity • High sensitivity LOS/SD detect • Ultra fast LVTTL LOS/SD output • Squelching function to disable output • Programmable LOS/SD level set (LOS/SDLVL) • Available in a 16-pin (3mmx 3mm) QFN package Applications • • • • • • GE-PON/GPON/EPON OLT Gigabit Ethernet Fibre Channel OC-3/12/24 SONET/SDH High-gain line driver and line receiver Low-gain TIA interface Markets • FTTH/FTTP • Datacom/Telecom • Optical transceiver All support documentation can be found on Micrel’s web site at: www.micrel.com. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com June 2010 M9999-061110-I [email protected] or (408) 955-1690 Micrel, Inc. SY88149HL Ordering Information Part Number Package Type Operating Range Package Marking Lead Finish SY88149HLMG QFN-16 Industrial 149H with Pb-Free bar-line indicator NiPdAu Pb-Free QFN-16 Industrial 149H with Pb-Free bar-line indicator NiPdAu Pb-Free (1) SY88149HLMGTR Pin Configuration 16-Pin QFN Truth Tables LOS/SDSEL Function LOS/SD Output (JAM Input) OUTPUTS High SD High Enabled High SD Low Disabled Low LOS Low Enabled Low LOS High Disabled June 2010 2 M9999-061110-I [email protected] or (408) 955-1690 Micrel, Inc. SY88149HL Pin Description Pin Number Pin Name Pin Function 1, 4 DIN, /DIN Data Inputs. If AC-Coupled, terminate each pin to Vref with 50Ω. 2 VREF Reference Voltage Output. Typically Vcc – 1.3V. 3,11,8 GND Device Ground. Exposed pad must be soldered (or equivalent) to the same potential as ground pins. 10 /AUTORESET 5,16 VCC 6 RESET LVTTL Input. Apply a high-level signal (>2V) to this pin to discharge the time constant and reset the signal de-assert time or LOS assert time within 5ns. RESET defaults to Low if left floating. If the /AUTORESET function is not used, this RESET function needs to be used to quickly de-assert the SD or assert LOS. Note that this input is internally connected to a 25kΩ pull-up resistor. 7 LOS/SD LVTTL Output. Signal-Detect (SD) asserts high when the data input amplitude rises above the threshold set by SDLVL. Conversely, Loss-of-Signal (LOS) de-asserts low when the data input amplitude rises above the threshold set by LOSLVL. 12, 9 DOUT, /DOUT 13 LOS/SDSEL LVTTL Input. Connect to VCC or leave open to select SD; set low or connect-to-GND to select LOS. This pin also controls the LOS/SD output and polarity of the JAM function. When SD is selected, JAM is active LOW and LOS/SD (pin 7) operates as signal detect. Conversely, when LOS is selected, JAM is active HIGH and LOS/SD operates as loss-ofsignal. Note that this input is internally connected to a 25Ω pull-down resistor 14 LOS/SDLVL Voltage Input. Sets the Loss of Signal/Signal Detect Level. A resistor from this pin to VCC sets the threshold for the data input amplitude at which LOS/SD will be asserted. 15 JAM LVTTL Input. JAM acts as a squelch function which can disable the LVPECL outputs. The polarity of the input that triggers an active JAM depends upon LOS/SDSEL status. When LOS is selected, this pin is active HIGH. When SD is selected, this pin is active LOW. To create a squelch function, connect JAM to LOS/SD output. When JAM disables the device, output Q is forced to logic LOW and output /Q is forced to logic HIGH. Note that this input is internally connected to a 25kΩ pull-up resistor. June 2010 LVTTL Input. This pin is internally connected to a 25kΩ pull-up resistor and defaults to HIGH. When this pin is LOW or tied to ground, the /AUTORESET function is enabled and SD de-asserts or LOS asserts within 100ns (typical) after the last high to low transition of the burst input. When this pin is left floating or not connected, the AUTORESET function is disabled and the SD de-assert or LOS assert must be forced by using the manual RESET function. Positive power supply. Bypass with 0.1uF | | 0.01uF low ESR capacitors. 0.01uF capacitors should be as close as possible to VCC pins. LVPECL Outputs. When JAM disables the device, output DOUT is forced to logic LOW and output /DOUT is forced to logic HIGH. 3 M9999-061110-I [email protected] or (408) 955-1690 Micrel, Inc. SY88149HL Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) ....................................... 0V to +4.0V Input Voltage (DIN, /DIN) ....................................... 0 to VCC Output Current (IOUT) Continuous ........................................................ ±50mA Surge .............................................................. ±100mA TTL Inputs Voltage ................................................. 0 to VCC VREF Current .......................................... -800μA to +500μA LOS/SDLVL Voltage ............................................VREF to VCC Lead Temperature (soldering, 20sec.) ..................... 260°C Storage Temperature (Ts) ....................... –65°C to +150°C Supply Voltage (VCC)................................. +3.0V to +3.6V Ambient Temperature (TA) ....................... –40°C to +85°C Junction Temperature (TJ) ..................... –40°C to +125°C (3) Junction Thermal Resistance QFN (θJA) Still-air ............................................. 60°C/W QFN (ΨJB) Junction-to-board ........................... 38°C/W DC Electrical Characteristics VCC = 3.0 to 3.6V; TA = –40°C to +85°C, typical values at VCC = 3.3V, TA = 25°C. Symbol Parameter Condition ICC Power Supply Current No output load LOS/SDLVL LOS/SDLVL Voltage Min Typ Max Units 57 78 mA VCC V VREF VOH LVPECL Output HIGH Voltage 50Ω to VCC-2V VCC-1.085 VCC-0.955 VCC-0.880 V VOL LVPECL Output LOW Voltage 50Ω to VCC-2V VCC-1.830 VCC-1.705 VCC-1.555 V IOFFSET Input Offset Voltage 1 mV VIHCMR Common Mode Range GND+2.0 VREF Reference Voltage VCC-1.48 VCC V VCC-1.32 VCC-1.16 V Typ Max Units LVTTL DC Electrical Characteristics VCC = 3.0 to 3.6V; TA = –40°C to +85°C, typical values at VCC = 3.3V, TA = 25°C. Symbol Parameter Condition VIH TTL Input HIGH Voltage VIL TTL Input LOW Voltage IIH TTL Input HIGH Current (/AUTORESET, JAM, LOS/SDSEL) VIN = 2.7V VIN = VCC IIL TTL Input LOW Current (/AUTORESET, JAM, LOS/SDSEL) VIN = 0.5V IIH TTL Input HIGH Current (RESET) VIN = 2.7V VIN = VCC Min 2.0 IIL TTL Input LOW Current (RESET) VIN = 0.5V VOL TTL Output LOW Level IOL = +20mA V 0.8 V 20 µA 100 -0.3 µA mA 200 µA 300 µA -0.05 mA 0.5 V Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Thermal performance assumes the use of a 4-layer PCB. Exposed pad must be soldered (or equivalent) to the device’s most negative potential on the PCB. June 2010 4 M9999-061110-I [email protected] or (408) 955-1690 Micrel, Inc. SY88149HL AC Electrical Characteristics VCC = 3.0V to 3.6V; RLOAD = 50Ω to VCC–2V; TA = –40°C to +85°C. Symbol Parameter Condition Min Max Units tr , tf Output Rise/Fall Time (20% to 80%) Note 4 260 ps tJAM_LH tJAM_HL JAM Low to High Propagation Time Note 12 5 ns JAM High to Low Propagation Time Note 13 2 ns tAUTORESET tRESET SD de-assert or LOS assert with Auto Reset enabled. RESET time constant 150 ns Note 5 5 ns tON SD Assert Time/LOS De-assert time Note 9 tJITTER Deterministic Note 6 15 psPP Random Note 7 5 psRMS 75 Typ 100 5 VID Differential Input Voltage Swing Figure 1 VOD Differential Output Voltage Swing VID > 18mVPP 4 SDAL /LOSDL Low SD Assert/LOS De-assert Level RLOS/SDLVL = 5kΩ, Note 8, 10 SDDL// LOSAL Low SD De-assert/LOS Assert Level HYSL SDAM/ LOSDM 1800 ns mVPP 1500 mVPP 4.2 mVPP RLOS/SDLVL = 5kΩ, Note 10 3 mVPP Low SD/LOS Hysteresis RLOS/SDLVL = 5kΩ, Note 11 2.9 dB Medium SD Assert/LOS De-assert Level RLOS/SDLVL = 2.5kΩ, Note 10 5.2 SDDM/ LOSAM Medium SD De-assert/LOS Assert Level RLOS/SDLVL = 2.5kΩ, Note 10 HYSM Medium SD/LOS Hysteresis SDAH/ LOSDH 2.5 12 mVPP 3.7 mVPP RLOS/SDLVL = 2.5kΩ, Note 11 3 dB High SD Assert/LOS De-assert Level RLOS/SDLVL = 50Ω, Note 10 15 SDDH/ LOSAH High SD De-assert/ LOS Assert Level RLOS/SDLVL = 50Ω, Note 10 HYSH High SD/LOS Hysteresis RLOS/SDLVL = 50Ω, Note 11 B-3dB 6 24 mVPP 9.5 mVPP 4 dB 3dB Bandwidth 1 GHz AV(Diff) Differential Voltage Gain 48 dB S21 Single-ended Small-Signal Gain 42 dB Notes: 4. Amplifier in limiting mode. Input is a 200MHz square wave. 5. The time between applying RESET and outputs being disabled. 6. Deterministic jitter measured using 1.25Gbps K28.5 pattern, VID = 10mVPP. 7. Random jitter measured using 1.25Gbps K28.7 pattern, VID = 10mVPP. 8. SD is the opposite polarity of LOS. Therefore, an SD Assert parameter is equivalent to a LOS De-assert parameter and vice versa. 9. See “Typical Operating Characteristics” for graphs showing input signal vs. SD Assert/LOS De-assert time at various RLOS/SDLVL settings. 10. See “Typical Operating Characteristics” for a graph showing how to choose a particular RLOS/SDLVL for a particular assert and its associated de-assert amplitude. 11. This specification defines electrical hysteresis as 20log (SD Assert/SD De-assert). The ratio between optical hysteresis and electrical hysteresis is found to vary between 1.5 and 2 depending upon the level of received optical power and ROSA characteristics. Based upon that ratio, the optical hysteresis corresponding to the electrical hysteresis range 2dB-5dB, shown in the AC characteristics table, will be: 1dB-4dB optical Hysteresis. 12. JAM Low to High transition propagation delay refers to the time it takes from a LOW to HIGH transition at JAM input to turning on (if SD is selected) or turning off (if LOS is selected) the LVPECL outputs. 13. JAM High to Low transition propagation delay refers to the time it takes from a HIGH to LOW transition at JAM input to turning off (if SD is selected) or turning on (if LOS is selected) the LVPECL outputs. June 2010 5 M9999-061110-I [email protected] or (408) 955-1690 Micrel, Inc. SY88149HL Typical Operating Characteristics VCC = 3.3V, TA = 25°C, RL = 50Ω to VCC–2V, unless otherwise stated. June 2010 6 M9999-061110-I [email protected] or (408) 955-1690 Micrel, Inc. SY88149HL Functional Block Diagram Detailed Description The SY88149HL is a high-sensitivity limiting post amplifier which operates on a +3.3V power supply over the industrial temperature range. Signals with data rates up to 1.25Gbps and as small as 4mVpp can be amplified. Figure 1 shows the allowed input voltage swing. Depending upon the LOS/SDSEL option, the SY88149HL can generate an SD or LOS output, and allow feedback to the JAM input for output stability. LOS/SDLVL sets the sensitivity of the input amplitude detection. To satisfy the stringent timing requirements of the GPON specifications, the signal detect circuit offers 5ns SD assert (LOS de-assert) time and the option to de-assert SD (assert LOS) using the /AUTORESET or manual RESET function. When /AUTORESET is enabled, SD de-asserts/LOS asserts automatically within 100ns after the last high-to-low transition of the input burst. When the /AUTORESET function is disabled, the SD Deassert/LOS Assert time can be reset by using the provided RESET pin. Output Buffer The SY88149HL’s LVPECL output buffer is designed to drive 50Ω lines. The output buffer requires appropriate termination for proper operation. An external Ω 50 resistor to VCC–2V for each output pin provides this. Figure 3 shows a simplified schematic of the output stage. Loss of Signal/Signal Detect The SY88149HL generates a chatter-free Signal-Detect (SD) or LOS LVTTL output, as shown in Figure 4. A highly sensitive signal detect circuit is used to determine that the input amplitude is too small to be considered a valid input. LOS asserts high if the input amplitude falls below the threshold set by LOS/SDLVL and de-asserts low otherwise. SD asserts high if the input amplitude rises above the threshold set by LOS/SDLVL and de-asserts low otherwise. LOS/SD can be fed back to the JAM input to maintain output stability under the absence of an invalid signal condition. Typically, a 3 dB hysteresis is provided to prevent chattering. Input Buffer Figure 2 shows a simplified schematic of the input stage. The high sensitivity of the input amplifier allows signals as small as 4mVpp to be detected and amplified. The input buffer can allow input signals as large as 1800mVPP. Input signals are linearly amplified with a typically 48dB differential voltage gain until the outputs reach 1500mVPP (typ). Applications requiring the SY88149HL to operate with high-gain should have the upstream TIA placed as close as possible to the SY88149HL’s input pins. This ensures the best performance of the device. LOS/SD Level Set A programmable LOS/SD level set pin (LOS/SDLVL) sets the threshold of the input amplitude detection. Connecting an external resistor between VCC and LOS/SDLVL sets the voltage at LOS/SDLVL. This voltage ranges from VCC to VREF. The external resistor creates a voltage divider between VCC and VREF, as shown in Figure 5. Set the LOS/SDLVL voltage closer to VREF or more sensitive LOS/SD detection or closer to VCC for higher amplitude inputs. June 2010 7 M9999-061110-I [email protected] or (408) 955-1690 Micrel, Inc. SY88149HL Timing Diagrams a) No manual RESET & /AutoReset tied HIGH b) No manual RESET & /AutoReset tied LOW c) Manual RESET pulse & /AutoReset tied LOW d) Manual RESET Pulse & /AutoReset tied LOW June 2010 8 M9999-061110-I [email protected] or (408) 955-1690 Micrel, Inc. SY88149HL Figure 1. VIS and VID Definition June 2010 Figure 2. Input Structure Figure 3. Output Structure Figure 4. SD Output Structure Figure 5. LOS/SDLVL Setting Circuit 9 M9999-061110-I [email protected] or (408) 955-1690 Micrel, Inc. SY88149HL Related Product and Support Documentation Part Number Function Datasheet Link SY88903AL 3.3V, Burst Mode 1.25Gbps PECL HighSensitivity Limiting Post Amplifier with TTL Loss-of-Signal http://www.micrel.com/product-info/sy88903al.shtml SY88149CL 3.3V, 1.25Gbps PECL Limiting Post Amplifier w/High Gain TTL Signal Detect http://www.micrel.com/product-info/sy88149cl.shtml Application Notes Notes on Sensitivity and Hysteresis in Micrel Post Amplifiers http://www.micrel.com/product-info/app_hints+notes.shtml June 2010 10 M9999-061110-I [email protected] or (408) 955-1690 Micrel, Inc. SY88149HL Package Information 16-Pin QFN MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2010 Micrel, Incorporated. June 2010 11 M9999-061110-I [email protected] or (408) 955-1690