SY88149HAL 1.25Gbps Burst-Mode Limiting Amplifier with Ultra-Fast Signal Assert Timing General Description The SY88149HAL is a high-sensitivity, burst-mode capable, limiting-post amplifier designed for FTTH PON optical line terminal (OLT) receiver applications. The SY88149HAL satisfies the strict timing restrictions of the GPON standards by providing ultra-fast loss-of-signal (LOS) or signal-detect (SD) output. Auto reset and manual reset options are provided to control LOS/SD output timing. The device can be connected to burst-mode capable transimpedance amplifiers (TIAs) using AC or DC coupling. The SY88149HAL generates a high-gain LVTTL LOS or SD output. A programmable LOS/SD level set pin (LOS/SDLVL) sets the sensitivity of the input amplitude detection. For increased flexibility, this device also includes an option to select between LOS or SD output by using the LOS/SD SEL pin. The LOS/SD output can be fed back to the JAM input to maintain data output stability under an invalid input signal conditions. Typically, 3dB LOS/SD hysteresis is provided to prevent chattering. The SY88149HAL operates from a single +3.3V power supply, over temperatures ranging from –40oC to +85oC. With its wide bandwidth and high gain, signals up to 1.25Gbps and as small as 5mVpp can be amplified to LVPECL levels. All support documentation can be found on Micrel’s web site at: www.micrel.com. Features • <5ns SD Assert (LOS Deassert) time • Option to AUTO RESET or manual RESET LOS/SD output • Selectable LOS/SD output option • High-sensitivity LOS/SD signal detect • Low-noise LVPECL data outputs • Squelching function to maintain output stability • Programmable LOS/SD level set (LOS/SDLVL) • 5mVpp input sensitivity • 1.25Gbps operation • Single 3.3V power supply • Available in a 16-pin (3mm × 3mm) QFN® package Applications • • • • • • GE-PON/GPON Gigabit Ethernet Fibre Channel OC-3/12/24 SONET/SDH High-gain line driver and line receiver Low-gain TIA interface Markets • FTTH PON • Datacom/Telecom • Optical transceiver Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com July 2011 M9999-072511-A [email protected] or (408) 955-1690 Micrel, Inc. SY88149HAL Ordering Information Part Number Package Type Operating Range Package Marking SY88149HALMG Lead-Free QFN-16 Industrial 149A with Pb-Free Bar-Line Indicator SY88149HALMG TR(1) Lead-Free QFN-16 Industrial 149A with Pb-Free Bar-Line Indicator Notes: 1. Tape and Reel. Pin Configuration 16-Pin QFN® (QFN-16) Pin Description Pin Number Pin Name Pin Function 1, 4 DIN, /DIN Differential Data Inputs. If AC-coupled, terminate each pin to VREF with 50Ω. 2 VREF Reference Voltage Output. Typically VCC – 1.3V. 3, 11, 8 GND Device Ground. Exposed pad must be soldered (or equivalent) to the same potential as the ground pins. 10 /AUTO RESET 5, 16 VCC 6 RESET July 2011 LVTTL Input. This pin is internally connected to a 25kΩ pull-up resistor and defaults to HIGH. When this pin is LOW or tied to ground, the /AUTO RESET function is enabled and SD deasserts or LOS asserts within 120ns (typical) after the last high-to-low transition of the burst input. When this pin is left floating or tied high, the AUTO RESET function is disabled and the SD deassert or LOS assert must be forced by using the manual RESET function. Positive power supply. Bypass with 0.1uF | | 0.01uF low ESR capacitors. 0.01uF capacitors should be as close as possible to VCC pins. LVTTL Input. Apply a high-level signal (>2V) to this pin to reset the SD deassert time or LOS assert within 5ns. RESET defaults to LOW if left floating. If the /AUTO RESET function is not used, this RESET function needs to be used to quickly deassert the SD or assert LOS. This pin is internally connected to a 25kΩ pull-down resistor and defaults to LOW. 2 M9999-072511-A [email protected] or (408) 955-1690 Micrel, Inc. SY88149HAL Pin Description (Continued) Pin Number Pin Name 7 LOS/SD 12, 9 DOUT, /DOUT Pin Function LVTTL Output. Signal detect (SD) asserts high when the data input amplitude rises above the threshold sets by SDLVL. Conversely, loss-of-signal (LOS) deasserts low when the data input amplitude rises above the threshold set by LOSLVL. LVPECL Outputs. When JAM disables the device, output DOUT is forced to logic LOW and output /DOUT is forced to logic HIGH. 13 LOS/SD SEL Allows the user to select between whether LOS or SD is outputted on the LOS/SD pin. Also controls the polarity of the JAM input. When SD is selected, JAM is active HIGH and LOS/SD (Pin 7) operates as signal detect. Conversely, when LOS is selected, JAM is active LOW and LOS/SD operates as loss-of-signal. This pin is internally connected to a 25kΩ pull-up resistor and defaults to HIGH (SD output selected). 14 LOS/SDLVL Voltage Input. Sets the LOS/SD level. A resistor from this pin to VCC sets the threshold for the data input amplitude at which LOS/SD will be asserted. 15 July 2011 JAM LVTTL Input. This JAM input acts as a squelch function and switches its polarity depending on LOS/SD SEL status. When LOS is selected, this pin is active LOW. When SD is selected, this pin is Active HIGH. To create a squelch function, connect JAM to LOS/SD. When JAM disables the device, output Q is forced to logic LOW and output /Q is forced to logic HIGH. Note that this input is internally connected to a 25kΩ pull-up resistor. 3 M9999-072511-A [email protected] or (408) 955-1690 Micrel, Inc. SY88149HAL Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC)....................................... 0V to +4.0V Input Voltage (DIN, /DIN) .......................................0 to VCC Output Current (IOUT) Continuous........................................................ ±50mA Surge .............................................................. ±100mA EN Voltage .............................................................0 to VCC VREF Current .......................................... -800μA to +500μA SDLVL Voltage ....................................................VREF to VCC Lead Temperature (soldering, 20s).......................... 260°C Storage Temperature (Ts) ....................... –65°C to +150°C Supply Voltage (VCC)................................. +3.0V to +3.6V Ambient Temperature (TA).......................–40°C to +85°C Junction Temperature (TJ) .....................–40°C to +125°C Junction Thermal Resistance(3) QFN® (θJA) Still-Air ...........................................60°C/W QFN® (ΨJB) Junction-to-Board .........................38°C/W DC Electrical Characteristics VCC = 3.0 to 3.6V; TA = –40°C to +85°C, typical values at VCC = 3.3V, TA = 25°C. Symbol Parameter Condition ICC Power Supply Current No output load Min. LOS/SDLVL LOS/SDLVL Voltage VOH LVPECL Output HIGH Voltage 50Ω to VCC − 2V VCC − 1.085 VOL LVPECL Output LOW Voltage 50Ω to VCC − 2V VCC − 1.830 IOFFSET Input Offset Voltage VIHCMR Common Mode Range Note 4 GND + 1.4 VREF Reference Voltage IDIN Input Sink Current (DIN & /DIN) Typ. Max. Units 58 80 mA VCC V VCC − 0.955 VCC − 0.880 V VCC − 1.705 VCC − 1.555 V VREF VCC − 1.48 VCC − 1.32 No Input Load 1 mV VCC V VCC − 1.16 V 6 uA Max. Units 0.8 V LVTTL DC Electrical Characteristics VCC = 3.0 to 3.6V; TA = –40°C to +85°C, typical values at VCC = 3.3V, TA = 25°C. Symbol Parameter Condition VIH LVTTL Input HIGH Voltage VIL LVTTL Input LOW Voltage IIH_JAM JAM Input HIGH Current VIN = VCC VIN = 2.7V IIL_JAM JAM Input LOW Current VIN = 0.5V IIH_AR /AUTORESET Input HIGH Current VIN = VCC VIN = 2.7V IIL_AR /AUTORESET Input LOW Current VIN = 0.5V Min. Typ. 2.0 V 20 20 −0.3 µA mA 100 20 −0.3 µA mA Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Thermal performance assumes the use of a 4-layer PCB. Exposed pad must be soldered to the device’s most negative potential on the PCB. 4. VIHCMR is defined as common mode range of the VIH level on DIN and /DIN. It is the most positive level of the differential signal. July 2011 4 M9999-072511-A [email protected] or (408) 955-1690 Micrel, Inc. SY88149HAL LVTTL DC Electrical Characteristics (Continued) VCC = 3.0 to 3.6V; TA = –40°C to +85°C, typical values at VCC = 3.3V, TA = 25°C. Symbol Parameter Condition IIH_RESET RESET Input HIGH Current VIN = VCC VIN = 2.7V IIL_RESET RESET Input LOW Current VIN = 0.5V VOH SD/LOS Output HIGH Level IOH = −100uA VOL SD/LOS Output LOW Level IOL = 100uA Min. Typ. Max. Units 300 µA 250 0 mA 2.1 2.7 V 0.35 0.5 V AC Electrical Characteristics VCC = 3.0V to 3.6V; RLOAD = 50Ω to VCC – 2V; TA = –40°C to +85°C. Parameter Condition tr, tf Symbol Output Rise/Fall Time (20% to 80%) Note 5 tJAM JAM Enable/Disable Time tAUTORESET SD Deassert or LOS Assert with Auto Reset Enabled. tRESET RESET time constant tON SD Assert Time/LOS Deassert time tJITTER Deterministic Min. 100 Typ. Max. Units 260 ps 2 ns 150 ns 5 ns 5 ns 120 Note 6 Note 7 15 Random Note 8 VID Differential Input Voltage Swing Figure 1 VOD Differential Output Voltage Swing VID ≥18mVPP SDAL /LOSDL Low SD Assert/LOS De- Assert Level RLOS/SDLVL = 10kΩ, Note 9, 10 psPP 5 5 psRMS 1800 mVPP 1500 mVPP 4 mVPP SDDL//LOSAL Low SD Deassert /LOS Assert Level RLOS/SDLVL = 10kΩ, Note 10 3 mVPP HYSL Low SD/LOS Hysteresis RLOS/SDLVL = 10kΩ, Note 11 2.5 dB SDAM/LOSDM Medium SD Assert/LOS Deassert Level RLOS/SDLVL = 5kΩ, Note 10 4.76 mVPP SDDM/LOSAM Medium SD Deassert /LOS Assert Level RLOS/SDLVL = 5kΩ, Note 10 3.6 mVPP HYSM Medium SD/LOS Hysteresis RLOS/SDLVL = 5kΩ, Note 11 SDAH/LOSDH High SD Assert/LOS De- Assert Level RLOS/SDLVL = 50Ω, Note 10 18 mVPP SDDH/LOSAH High SD Deassert/ LOS Assert Level RLOS/SDLVL = 50Ω, Note 10 12.5 mVPP HYSH High SD/LOS Hysteresis RLOS/SDLVL = 50Ω, Note 11 B-3dB 3dB Bandwidth 750 MHz AV(Diff) Differential Voltage Gain 48 dB S21 Single-Ended Small-Signal Gain 42 dB 2 2 3 3 4 4 dB dB Notes: 5. Amplifier in limiting mode. Input is a 200MHz square wave. 6. The time between applying RESET and outputs being disabled. 7. Deterministic jitter measured using 1.25Gbps K28.7 pattern, VID = 10mVPP. 8. Random jitter measured using 1.25Gbps K28.7 pattern, VID = 10mVPP. 9. SD is the opposite polarity of LOS. Therefore, an SD Assert parameter is equivalent to a LOS deassert parameter and vice versa. 10. See “Typical Operating Characteristics” for a graph showing how to choose a particular RLOS/SDLVL for a particular assert and its associated deassert amplitude. 11. This specification defines electrical hysteresis as 20log(SD assert/SD deassert). The ratio between optical hysteresis and electrical hysteresis is found to vary between 1.5 and 2 depending upon the level of received optical power and ROSA characteristics. Based upon that ratio, the optical hysteresis corresponding to the electrical hysteresis range 3dB − 6dB, shown in the AC Characteristics table, will be 1.5dB-4dB optical hysteresis. July 2011 5 M9999-072511-A [email protected] or (408) 955-1690 Micrel, Inc. SY88149HAL Typical Operating Characteristics VCC = 3.3V, TA = 25°C, RL = 50Ω to VCC – 2V, unless otherwise stated. LOS/SD Hysteresis LOS Assert/De-Assert Levels 6 5 Hysteresis (dB) Signal Amplitude (mV) 100 10 3 2 1 1 0.1 1 10 0.1 LOS/SDLVL Resistor (KOhm) July 2011 4 1 10 LOS/SDLVL Resistor (KOhm) 6 M9999-072511-A [email protected] or (408) 955-1690 Micrel, Inc. SY88149HAL Functional Block Diagram July 2011 7 M9999-072511-A [email protected] or (408) 955-1690 Micrel, Inc. SY88149HAL Loss of Signal/Signal Detect The SY88149HAL generates a chatter-free Signal-Detect (SD) or LOS LVTTL output, as shown in Figure 4. A highly-sensitive signal detect circuit is used to determine that the input amplitude is too small to be considered a valid input. LOS asserts high if the input amplitude falls below the threshold sets by LOS/SDLVL and deasserts low otherwise. SD asserts high if the input amplitude rises above threshold set by LOS/SDLVL and deasserts low otherwise. LOS/SD can be fed back to the JAM input to maintain output stability under the absence of an invalid signal condition. Typically, a 3dB hysteresis is provided to prevent chattering. Detailed Description The SY88149HAL is a high-sensitivity limiting post amplifier which operates on a +3.3V power supply over the industrial temperature range. Signals with data rates up to 1.25Gbps and as small as 5mVpp can be amplified. Depending on the LOS/SD SEL option, the SY88149HAL can generate an SD or LOS output, and allow feedback to the JAM input for output stability. LOS/SDLVL sets the sensitivity of the input amplitude detection. To satisfy the stringent timing requirements of the GPON specifications, the signal detect circuit offers 5ns SD assert (LOS deassert) time and the option to deassert SD (assert LOS) using the /AUTO RESET or manual RESET function. When /AUTO RESET is enabled, SD deasserts/LOS asserts automatically within 120ns after the last high-to-low transition of the input burst. When the /AUTORESET function is disabled, the SD deassert/LOS assert time can be reset by using the provided RESET pin. LOS/SD Level Set A programmable LOS/SD level pin (LOS/SDLVL) sets the threshold of the input amplitude detection. Connecting an external resistor between VCC and LOS/SDLVL sets the voltage at LOS/SDLVL. This voltage ranges from VCC to VREF. The external resistor creates a voltage divider between VCC and VREF, as shown in Figure 5. Set the LOS/SDLVL voltage closer to VREF or more sensitive LOS/SD detection or closer to VCC for higher inputs. Input Buffer Figure 2 shows a simplified schematic of the input stage. The high sensitivity of the input amplifier allows signals as small as 5mVpp to be detected and amplified. The input buffer can allow input signals as large as 1800mVPP. Input signals are linearly amplified with a typically 48dB differential voltage gain until the outputs reach 1500mVPP (typical). Applications requiring the SY88149HAL to operate with high-gain should have the upstream TIA placed as close as possible to the SY88149HAL’s input pins. This ensures the best performance of the device. Output Buffer The SY88149HAL’s LVPECL output buffer is designed to drive 50Ω lines. The output buffer requires appropriate termination for proper operation. An external 50Ω resistor to VCC – 2V for each output pin provides this. Figure 3 shows a simplified schematic of the output stage. July 2011 8 M9999-072511-A [email protected] or (408) 955-1690 Micrel, Inc. SY88149HAL Timing Diagrams No Manual RESET and /AUTORESET Tied HIGH No Manual RESET and /AUTORESET Tied LOW Manual RESET and /AUTORESET Tied HIGH or LOW July 2011 9 M9999-072511-A [email protected] or (408) 955-1690 Micrel, Inc. SY88149HAL Figure 1. VIS and VID Definition July 2011 Figure 2. Input Structure Figure 3. Output Structure Figure 4. SD Output Structure Figure 5. LOS/SDLVL Setting Circuit 10 M9999-072511-A [email protected] or (408) 955-1690 Micrel, Inc. SY88149HAL Package Information 16-Pin QFN® (QFN-16) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2011 Micrel, Incorporated. July 2011 11 M9999-072511-A [email protected] or (408) 955-1690