SY89851U Low Power, 3GHz, 1:2 LVPECL Fanout Buffer/Translator with Internal Termination General Description The SY89851U is a low jitter, low skew, high-speed 1:2 differential fanout buffer optimized for precision telecom and enterprise server distribution applications. The SY89851U distributes clock frequencies from DC to >3GHz, and data rates to 2.5Gbps guaranteed over temperature and voltage. The SY89851U differential input includes Micrel's unique, 3-pin input termination architecture that directly interfaces to any differential signal (AC- or DC-coupled) as small as 100mV (200mVpp) without any level shifting or termination resistor networks in the signal path. The outputs are 800mV, 100Kcompatible LVPECL with extremely fast rise/fall time guaranteed to be less than 180ps. The SY89851U operates from a 2.5V ±5% or 3.3V ±10% supply and is guaranteed over the full industrial temperature range of –40°C to +85°C. The SY89851U is part of Micrel's high-speed, Precision ® Edge product line. All support documentation can be found on Micrel's web site at www.micrel.com. Functional Block Diagram Precision Edge ® Features • Precision 1:2, 800mV LVPECL fanout buffer • Low power consumption: 80mW typ. (2.5V) • Guaranteed AC performance over temperature and voltage: – DC to >3GHz clock throughput – <340ps propagation delay – <180ps rise/fall time – <20ps output-to-output skew • Ultra-low jitter design: – <1psRMS random jitter – <10psPP deterministic jitter – <10psPP total jitter (clock) • Unique, patented input termination and VT pin accepts DC- and AC-coupled inputs (CML, LVPECL, LVDS) • 100K LVPECL-compatible outputs • Power supply 2.5V ±5% or 3.3V ±10% • –40°C to +85°C industrial temperature range • Available in 16-pin (3mm x 3mm) QFN package Applications • • • • All SONET and GigE clock distribution Fibre Channel applications Backplane distribution High-end, low skew, multiprocessor synchronous clock distribution Precision Edge is a registered trademark of Micrel, Inc. July 2005 M9999-071205 [email protected] or (408) 955-1690 Micrel, Inc. SY89851U Ordering Information(1) Part Number Package Type Operating Range Package Marking Lead Finish SY89851UMG QFN-16 Industrial 851U with Pb-Free bar-line indicator Pb-Free NiPdAU QFN-16 Industrial 851U with Pb-Free bar-line indicator Pb-Free NiPdAu (2) SY89851UMGTR Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. Pin Configuration 16-Pin QFN July 2005 2 M9999-071205 [email protected] or (408) 955-1690 Micrel, Inc. SY89851U Pin Description Pin Number Pin Name 1,4 IN, /IN Differential Inputs: This input pair is the differential signal input to the device. Inputs accept AC- or DC-coupled signals as small as 100mV (200mVpp). Each pin terminates to a VT pin through 50Ω. Note that these inputs will default to an indeterminate state if left open. Please refer to the "Input Interface Applications" section for more details. 2 VT Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT pins provide a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section for more details. 3 VREF-AC Reference Voltage: This output biases to VCC–1.2V. It is used when ACcoupling the inputs (IN, /IN). For AC-coupled applications, connect VREF-AC to the VT pin and bypass with a 0.01µF low ESR capacitor to VCC. Maximum sink/source current is ±1.5mA. See “Input Interface Applications” section for more details. 5,8,13,16 VCC 12,11 9,10 Q0, /Q0, Q1, /Q1 6,7,14,15 GND, Exposed Pad July 2005 Pin Function Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors and place as close to each VCC pin as possible. Differential Outputs: These 100K LVPECL-compatible output pairs are the precision, low skew copies of the inputs. Unused output pairs may be left open. Terminate with 50Ω to VCC–2V. See “LVPECL Output Interface Application” section for more details. Ground. GND and exposed pad must both be connected to the same ground plane. 3 M9999-071205 [email protected] or (408) 955-1690 Micrel, Inc. SY89851U Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) .......................... –0.5V to +4.0V Input Voltage (IN, /IN) .............................–0.5V to VCC LVPECL Output Current (IOUT) Continuous ............................................... ±50mA Surge ...................................................... ±100mA Termination Current Source or sink current on VT .................. ±100mA VREF-AC Current Source or sink current ............................... ±2mA Input Current Source or sink current on IN, /IN .............. ±50mA Lead Temperature (soldering, 20sec.) ........... +260°C Storage Temperature (Ts) ..................–65°C to 150°C Supply Voltage (VCC).................. +2.375V to +2.625V ......................................................+3.0V to +3.6V Ambient Temperature (TA) ................ –40°C to +85°C (3) Package Thermal Resistance QFN (θJA) Still-Air ..................................................... 60°C/W QFN (ψJB) Junction-to-Board .................................... 33°C/W DC Electrical Characteristics(4) TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter VCC Power Supply Condition Min Typ Max Units 2.375 2.5 2.625 V 3.0 3.3 3.6 V 32 45 mA ICC Power Supply Current No load, max. VCC RIN Single-Ended Input Resistance (IN-to-VT) 45 50 55 Ω RDIFF_IN Differential Input Resistance (IN-to-/IN) 90 100 110 Ω VIH Input High Voltage (IN, /IN) VCC –1.6 VCC V VIL Input Low Voltage (IN, /IN) 0 VIH-0.1 V VIN Input Voltage Swing (IN, /IN) See Figure 1a. 0.1 1.7 V VDIFF_IN Differential Input Voltage Swing |IN-/IN| See Figure 1b. VT_IN IN-to-VT (IN, /IN) VREF-AC Output Reference Voltage Note 5 0.2 VCC –1.3 V VCC –1.2 1.28 V VCC –1.1 V Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. θJA and ψJB values are for a 4-layer board in still air, unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 5. VIH(min) not lower than 1.2V July 2005 4 M9999-071205 [email protected] or (408) 955-1690 Micrel, Inc. SY89851U 100K LVPECL Output DC Electrical Characteristics(6) VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to + 85°C; RL = 50Ω to VCC –2V, unless otherwise stated. Symbol Parameter Condition Min Typ Max Units VOH Output HIGH Voltage (Q, /Q) VCC–1.145 VCC–0.895 V VOL Output LOW Voltage (Q, /Q) VCC–1.945 VCC–1.695 V VOUT Output Voltage Swing (Q, /Q) See Figure 1a. 550 800 mV VDIFF_OUT Differential Output Voltage Swing (Q, /Q) See Figure 1b. 1100 1600 mV Note: 6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. July 2005 5 M9999-071205 [email protected] or (408) 955-1690 Micrel, Inc. SY89851U AC Electrical Characteristics(7) VCC = 2.5V ±5% or 3.3V ±10%, RL = 50Ω to VCC –2V, VIN ≥ 100mV (200mVPP); TA = –40°C to + 85°C, unless otherwise stated. Symbol fMAX Parameter Condition Min Typ Maximum Operating Frequency NRZ Data 2.5 3.5 Gbps 3 4 GHz 140 220 Clock tpd Differential Propagation Delay tpd Tempco ∆tpd Temperature Coefficient tSKEW Output-to-Output Skew Part-to-Part Skew IN-to-Q Max 340 130 Note 8 Note 9 6 Units ps fs/°C 20 120 ps ps Data tJITTER tr , tf Random Jitter Note 10 1 psRMS Deterministic Jitter Note 11 10 psPP Cycle-to-Cycle Jitter Note 12 1 psRMS Total Jitter Note 13 10 psPP 180 ps Clock Output Rise/Fall Time (20% to 80%) At full output swing 50 100 Notes: 7. High-frequency AC-parameters are guaranteed by design and characterization. 8. Output-to-output skew is measured between two different outputs under identical input transitions. 9. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 10. Random jitter is measured with a K28.7 character pattern, measured at 2.5Gbps. 23 11. Deterministic jitter is measured at 2.5Gbps, with both K28.5 and 2 – 1 PRBS pattern. 12. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the output signal. 13. Total jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 10 deviate by more than the specified peak-to-peak jitter value. July 2005 6 12 output edges will M9999-071205 [email protected] or (408) 955-1690 Micrel, Inc. SY89851U Typical Operating Characteristics VCC = 3.3V, GND = 0V, VIN = 100mV (200mVPP), RL = 50Ω to VCC –2V, TA = 25°C, unless otherwise stated. July 2005 7 M9999-071205 [email protected] or (408) 955-1690 Micrel, Inc. SY89851U Functional Characteristics VCC = 3.3V, GND = 0V, VIN = 100mV (200mVPP), RL = 50Ω to VCC –2V, TA = 25°C, unless otherwise stated. July 2005 8 M9999-071205 [email protected] or (408) 955-1690 Micrel, Inc. SY89851U Single-Ended and Differential Swings Figure 1b. Differential Voltage Swing Figure 1a. Single-Ended Voltage Swing Timing Diagrams Input and Output Stages Figure 2a. Simplified Differential Input Stage July 2005 Figure 2b. Simplified LVPECL Output Stage 9 M9999-071205 [email protected] or (408) 955-1690 Micrel, Inc. SY89851U Input Interface Applications Optional: may connect VT to VCC Figure 3a. LVPECL Interface (DC-Coupled) Figure 3b. LVPECL Interface (AC-Coupled) Figure 3d. CML Interface (AC-Coupled) Figure 3e. LVDS Interface July 2005 10 Figure 3c. CML Interface (DC-Coupled) M9999-071205 [email protected] or (408) 955-1690 Micrel, Inc. SY89851U LVPECL Output Interface Applications LVPECL has high input impedance, very low output (open emitter) impedance, and small signal swing which result in low EMI. LVPECL is ideal for driving 50Ω- and 100Ω-controlled impedance transmission lines. There are several techniques for terminating the LVPECL output including: Parallel TerminationThevenin Equivalent, Parallel Termination (3Resistor), and AC-Coupled Termination. Unused output pairs may be left floating. However, singleended outputs must be terminated, or balanced. Figure 4b. Parallel Termination (3-Resistor) Figure 4a. Parallel Thevenin-Equivalent Termination Related Product and Support Documentation Part Number Function Data Sheet Link SY58012U 5GHz, 1:2 LVPECL Fanout Buffer/Translator with Internal Input Termination www.micrel.com/product-info/products/sy58012u.shtml HBW Solutions New Products and Applications www.micrel.com/product-info/products/solutions.shtml July 2005 11 M9999-071205 [email protected] or (408) 955-1690 Micrel, Inc. SY89851U Package Information 16-Pin QFN Package Notes: 1. Package meets Level 2 Moisture Sensitivity Classification. 2. All parts are dry-packaged before shipment. 3. Exposed pad must be soldered to a ground for proper thermal management. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. July 2005 12 M9999-071205 [email protected] or (408) 955-1690