MICREL SY898530UTZTX

SY898530U
500MHz 1:16 3.3V-to-2.5/3.3V LVPECL
Fanout Buffer
General Description
Features
The SY898530U is a 1:16 Fanout buffer which can accept
most standard differential logic levels and outputs the
signal as a differential 2.5V or 3.3V LVPECL signal. The
part can amplify input signals as small as 150mVpp to the
full LVPECL output swing. The SY898530U is well suited
for clock distribution applications which demand versatility
and low-skew performance. It is pin-to-pin compatible with
IDT’s ICS8530 fanout buffer.
The SY898530U operates from a 3.3V ±5% core power
supply and a 2.5V ±5% or a 3.3V ±5% output supply. The
SY898530U is guaranteed over the full commercial
temperature range (0°C to +70°C). It is available in a 48pin TQFP lead-free package.
Data sheets and support documentation can be found on
Micrel’s web site at www.micrel.com.
 16 Differential 2.5V/3.3V LVPECL outputs
 Differential CLK inputs. Accepts LVDS, LVPECL,
LVHSTL, SSTL, HCSL logic levels
 Translates any single-ended input signal to 2.5/3.3V
LVPECL levels with a resistor bias on /CLK input
 500MHz maximum output frequency
 <50ps output skew
 <250ps part-to-part skew
 <2ns propagation delay
 3.3V Core, 2.5/3.3V output operating supply
 0°C to +70°C operating temperature
 Available in 48-pin TQFP package
 Pin-to-pin compatible with ICS8530
Functional Block Diagram
Applications




Data distribution
High-performance PCs
Communications
Parallel processor-based systems
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
November 2011
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SY898530U
Ordering Information(1)
Part Number
Package Type
Operating Range
Package Marking
Lead Finish
TQFP-48
Commercial
SY898530UTZ with Pb-Free bar-line indicator
Matte-Sn
(2)
TQFP-48
Commercial
SY898530UTZ with Pb-Free bar-line indicator
Matte-Sn
(2, 3)
TQFP-48
Commercial
SY898530UTZ with Pb-Free bar-line indicator
Matte-Sn
SY898530UTZ
SY898530UTZTR
SY898530UTZTX
Notes:
1.
Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2.
Tape and Reel.
3.
EIA specification orientation.
Pin Configuration
48-Pin TQFP (TQFP-48)
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SY898530U
Pin Description
Pin Number
Pin Name
Pin Function
36, 37
CLK, /CLK
Differential Clock Inputs. Accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL logic levels.
CLK is internally connected to a pull-down resistor, /CLK is internally connected to a pullup resistor. See “Pin Characteristics” for typical values.
33, 34
Q0, /Q0
31, 32
Q1, /Q1
28, 29
Q2, /Q2
26, 27
Q3, /Q3
22, 23
Q4, /Q4
20, 21
Q5, /Q5
17, 18
Q6, /Q6
15, 16
Q7, /Q7
9, 10
Q8, /Q8
7, 8
Q9, /Q9
4, 5
Q10, /Q10
2, 3
Q11, /Q11
46, 47
Q12, /Q12
44, 45
Q13, /Q13
41, 42
Q14, /Q14
39, 40
Q15, /Q15
1, 11, 14, 24,
LVPECL Differential Output Pairs. Differential buffered copies of the input signal. The
output swing is typically 740mV. See Interface Applications for termination information.
Output Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to the
VCCO pins as possible. Supplies the output buffers.
VCCO
25, 35, 38, 48
12, 13
VCC
Core Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to the VCC
pins as possible. Supplies input and core circuitry.
6, 19, 30, 43
VEE
Ground
Pin Characteristics
Symbol
Description
Min.
Typ.
Max.
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pull Up Resistor
50
KΩ
RPULLDOWN
Input Pull Down Resistor
30
KΩ
Clock Input Function Table
Inputs
Outputs
CLK
/CLK
0
1
0
1
Input to Output Mode
Polarity
Qx
/Qx
1
Low
High
Differential to Differential
Non-Inverting
0
High
Low
Differential to Differential
Non-Inverting
Biased(1)
Low
High
Single-Ended to Differential
Non-Inverting
(1)
High
Low
Single-Ended to Differential
Non-Inverting
Biased
(1)
Biased
0
High
Low
Single-Ended to Differential
Inverting
Biased(1)
1
Low
High
Single-Ended to Differential
Inverting
Note:
1.
Refer to Interface Applications for Single-Ended Interfaces.
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SY898530U
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VCC)................................................4.6V
Input Voltage (VIN) ............................–0.5V to VCC + 0.5V
LVPECL Output Current (IOUT)
Continuous.......................................................50mA
Surge .............................................................100mA
Lead Temperature (soldering, 20sec.).................. 260°C
Storage Temperature (Ts) ....................–65°C to +150°C
Supply Voltage (VCC) ......................... 3.135V to 3.465V
Output Supply Voltage (VCCO)............ 2.375V to 3.465V
Ambient Temperature (TA)........................0°C to +70°C
Package Thermal Resistance(3)
TQFP
Still-air (JA) .........................................48°C/W
Junction-to-Case (JC).........................13°C/W
DC Electrical Characteristics(6)
VCC = 3.135V to 3.465V, VCCO = 2.375V to 3.465V, TA = 0°C to +70°C, unless otherwise stated.
Symbol
Parameter
Min.
Typ.
Max.
Units
VCC
Power Supply Voltage Range
Condition
3.135
3.3
3.465
V
VCCO
Output Power Supply
2.375
3.465
V
IEE
Power Supply Current
125
mA
IIH
Input HIGH Current
IIL
Input LOW Current
VPP
Peak-to-Peak Input Swing
VCMR
Common Mode Input Voltage
Max. VCC, VCCO
CLK
/CLK
CLK
/CLK
VCC = VIN = 3.465V
VCC = 3.465V, VIN = 0.5V
Note 4, 5
150
uA
5
uA
5
uA
150
uA
0.15
1.3
V
0.5
Vcc  0.85
V
PECL Outputs DC Electrical Characteristics(6)
VCC = 3.135V to 3.465V, VCCO = 2.375V to 3.465V, TA = 0°C to +70°C, Outputs terminated with 50Ω to VCCO-2V unless otherwise stated.
Symbol
Parameter
VOH
Output HIGH Voltage
VOL
VOUT
Condition
Min.
Typ.
Max.
Units
VCCO  1.1
VCCO  0.7
V
Output LOW Voltage
VCCO  2.0
VCCO  1.4
V
Output Voltage Swing
0.55
0.93
V
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions
for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. JA and JC values are determined for a 4-layer board in still-air.
4. For single-ended applications, the maximum input voltage for CLK, /CLK is VCC+0.3V.
5. Common mode voltage is defined as VIH.
6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
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SY898530U
AC Electrical Characteristics
VCC = 3.135V to 3.465V, VCCO = 2.375V to 3.465V, TA = 0°C to +70°C, unless otherwise stated.
Symbol
Parameter
Condition
Min.
fMAX
Maximum Frequency
tPD
Propagation Delay
Note 7
Output-to-Output skew
Note 8, 10
Part-to-Part Skew
Notes 9, 10
tJITTER
Integration Range = 12kHz  20MHz
Output = 500MHz
tR, tF
Output Rise/Fall Times
(20% to 80%)
At full output swing.
tSkew
Typ.
Max.
500
MHz
1
26
Duty Cycle
2
ns
50
ps
250
ps
fsRMS
127
300
47
Units
50
700
ps
53
%
Notes:
7.
Measured from the differential input crossing point to the differential output crossing point.
8.
Output-to-Output skew is the difference in time between outputs, receiving data from the same input, for the same temperature, voltage and
transition.
9.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective
inputs.
10. This parameter is defined in accordance with JEDEC Standard 65.
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SY898530U
Phase Noise Graph
Phase Noise Plot: 500MHz @ 3.3V
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SY898530U
Test Circuit
Differential Input Level
Output Duty Cycle
Propagation Delay
Output Rise/Fall Times
Output-to-Output Skew
Part-to-Part Skew
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Typical Characteristics
VCC = 3.3V, VCCO = 2.5V or 3.3V, TA = 25°C, Input Signal = 800mV
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SY898530U
Junction Temperature
The maximum recommended junction temperature is TJ =125°C. The outputs are terminated with 50 ohms to Vcco - 2V.
Below is a calculation of the worst case scenario with zero airflow:
TJ= Junction Temperature
TA = Ambient Temperature
ΘJA = Junction-to-Ambient Thermal Resistance
Pd = Power Dissipation
Pd = Pd_core + Pd_outputs
Pd_core = Vcc_max * Iee_max
Pd_core = 3.465V * 125mA = 433mW
Pd_output = Pd_h + Pd_l
Pd_h = [(Voh – (Vcco – 2V))/RL] * (Vcco - Voh_max)
Pd_h = [(2V – 0.7V)/50Ω] * 0.7V
Pd_h = 18.2mW
Pd_l = [(Vol – (Vcco – 2V))/RL] * (Vcco - Vol_max)
Pd_l = [(2V – 1.4V)/50Ω] * 1.4V
Pd_l = 16.8mW
Pd_output = 35mW
Pd_outputs = 16 * 35mW
Pd_outputs = 560mW
Pd = 433mW + 560mW
Pd = 0.993 W
TJ = TA + ΘJA * Pd
TJ_worst_case = 70°C + 0.993W * 48°C/W
TJ_worst_case = 118 °C in still air.
The worst case junction temperature is below 125 C.
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SY898530U
Output Interface Applications
Figure 1. Parallel Termination-Thevenin Equivalent
Notes:
1. For +2.5V systems: R1 = 250Ω, R2 = 82.5Ω.
Figure 2. Three-Resistor “Y-Termination”
Notes:
1. Power-saving alternatives to Thevenin termination.
2. Place termination resistors as close to destination inputs as possible.
3. For +2.5V systems, Rb = 19Ω. Rb resistor sets the DC bias voltage, equal to Vt.
Figure 3. Terminating Unused I/O
Notes:
1. Unused output (/Q) must be terminated to balance the output.
2. For 2.5V systems: R1 = 250Ω, R2 = 62.5Ω, R3 = 1.25kΩ, R4 = 1.2kΩ.
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SY898530U
Input Interface Applications
Figure 4. CLK and /CLK Input Driven By 1.8V LVHSTL
Figure 5. CLK and /CLK Input Driven By 3.3V LVDS Driver
Figure 6. CLK and /CLK Input Driven By 3.3V LVPECL Driver with AC Couple
Notes:
1. For +2.5V systems: R5 = 50 Ω. R1 & R2 = 220Ω, R3 & R4 = 68Ω.
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SY898530U
Package Information
48-Pin TQFP (TQFP-48)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
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relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
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