MICREL SY89827LHY

Precision Edge®
®
SY89827L
Precision Edge
3.3V 500MHz DUAL 1:10 HSTL FANOUT
BUFFER/TRANSLATOR WITH 2:1 MUX INPUT
Micrel, Inc.
SY89827L
FEATURES
■ Dual LVPECL or HSTL input, 10 differential 1.5V
HSTL compatible outputs
■ Configurable as dual-channel 10 output or a singlechannel 20 output clock driver
■ Guaranteed AC parameters over temperature and
voltage:
• > 500MHz fMAX
• < 50ps within device skew
• < 1.5ns propagation delay
• < 700ps tr / tf time
■ Low jitter design
• 186fsRMS phase jitter
■ 3.3V core supply, 1.8V output supply
■ Output enable function
■ Available in a 64-Pin EPAD-TQFP
Precision Edge®
DESCRIPTION
The SY89827L is a High Performance Bus Clock
Driver with dual 1:10 or single 1:20 HSTL (High Speed
Transceiver Logic) output pairs. The part is designed for
use in low voltage (3.3V/1.8V) applications which require a
large number of outputs to drive precisely aligned, ultra low
skew signals to their destination. The input is multiplexed
from either HSTL or LVPECL (Low Voltage Positive Emitter
Coupled Logic) by the CLK_SEL pin. The Output Enables
(OE1 & OE2) are synchronous so that the outputs will only
be enabled/disabled when they are already in the LOW state.
This avoids any chance of generating a runt clock pulse
when the device is enabled/disabled as can happen with an
asynchronous control.
The SY89827L features extremely low skew performance
of <50ps over temperature and voltage –performance
previously unachievable in a standard product having such
a high number of outputs. The SY89827L is available in a
single space saving package, enabling a lower overall cost
solution. For applications that require greater HSTL fanout
capability, consider the SY89824L.
APPLICATIONS
■
■
■
■
■
High-performance PCs
Workstations
Parallel processor-based systems
Other high-performance computing
Communications
TYPICAL APPLICATION CIRCUIT
10
PrimaryClockSource
LVPECL_CLKA
10
/LVPECL_CLKA
RedundantBackup
ClockSource
LVPECL_CLKB
10
/LVPECL_CLKB
10
Primary
Card
Redundant
Card
SEL1
Primary/Backup Clock Select
(Switchover within 2.0ns)
System using SY89827L as a switchover circuit from a Primary Clock to a Redundant Backup Clock in a failsafe application.
LVPECL inputs only, shown in this application.
Precision Edge is a registered trademark of Micrel, Inc.
M9999-073010
[email protected] or (408) 955-1690
1
Rev.: F
Amendment: /0
Issue Date: July 2010
Precision Edge®
SY89827L
Micrel, Inc.
PACKAGE/ORDERING INFORMATION
VCCO
Q0
/Q0
Q1
/Q1
Q2
/Q2
Q3
/Q3
Q4
/Q4
Q5
/Q5
Q6
/Q6
VCCO
Ordering Information(1)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
SEL2
HSTL_CLKB
/HSTL_CLKB
VCCI
HSTL_CLKA
/HSTL_CLKA
CLK_SEL1
LVPECL_CLKA
/LVPECL_CLKA
GND
OE1
LVPECL_CLKB
/LVPECL_CLKB
CLK_SEL2
OE2
SEL1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VCCO
Q7
/Q7
Q8
/Q8
Q9
/Q9
VCCO
VCCO
Q10
/Q10
Q11
/Q11
Q12
/Q12
VCCO
VCCO
/Q19
Q19
/Q18
Q18
/Q17
Q17
/Q16
Q16
/Q15
Q15
/Q14
Q14
/Q13
Q13
VCCO
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Part Number
Package
Type
Operating Range
Package
Marking
Lead
Finish
SY89827LHI
H64-1
Industrial
SY89827LHI
Sn-Pb
SY89827LHITR(2)
H64-1
Industrial
SY89827LHI
Sn-Pb
SY89827LHY(3)
H64-1
Industrial
SY89827LHY with
Pb-Free
Pb-Free bar-line indicator Matte-Sn
Industrial
SY89827LHYTR(2, 3) H64-1
SY89827LHY with
Pb-Free
Pb-Free bar-line indicator Matte-Sn
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.
64-Pin TQFP (H64-1)
FUNCTIONAL BLOCK DIAGRAM
CLK_SEL1
HSTL_CLKA
/HSTL_CLKA
LVPECL_CLKA
/LVPECL_CLKA
OE1
SEL1
0
10
0
10
1
Q0 – Q9
/Q0 – /Q9
1
LEN
HSTL_CLKB
/HSTL_CLKB
LVPECL_CLKB
/LVPECL_CLKB
Q
0
D
1
CLK_SEL2
0
10
10
1
LEN
SEL2
Q
D
OE2
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Q10 – Q19
/Q10 – /Q19
Precision Edge®
SY89827L
Micrel, Inc.
TRUTH TABLE
OE1(1)OE2(1) SEL1(1) SEL2(1) CLK_SEL1(1) CLK_SEL2(1)
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
X
X
X
X
0
0
1
1
X
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
X
X
X
X
X
0
1
0
0
1
1
0
0
1
1
X
X
0
1
X
X
0
1
X
X
X
X
X
0
1
0
1
0
1
0
1
0
1
X
X
0
1
X
X
0
1
X
Q0 – Q9
/Q0 – /Q9
Q10 – Q19
/Q10 – /Q19
HSTL_CLKA
LVPECL_CLKA
HSTL_CLKA
HSTL_CLKA
LVPECL_CLKA
LVPECL_CLKA
HSTL_CLKB
LVPECL_CLKB
HSTL_CLKB
LVPECL_CLKB
HSTL_CLKB
LVPECL_CLKB
LOW
LOW
LOW
LOW
HSTL_CLKA
LVPECL_CLKA
HSTL_CLKB
LVPECL_CLKB
LOW
/HSTL_CLKA
/LVPECL_CLKA
/HSTL_CLKA
/HSTL_CLKA
/LVPECL_CLKA
/LVPECL_CLKA
/HSTL_CLKB
/LVPECL_CLKB
/HSTL_CLKB
/LVPECL_CLKB
/HSTL_CLKB
/LVPECL_CLKB
HIGH
HIGH
HIGH
HIGH
/HSTL_CLKA
/LVPECL_CLKA
/HSTL_CLKB
/LVPECL_CLKB
HIGH
HSTL_CLKA
LVPECL_CLKA
HSTL_CLKB
LVPECL_CLKB
HSTL_CLKB
LVPECL_CLKB
HSTL_CLKA
HSTL_CLKA
LVPECL_CLKA
LVPECL_CLKA
HSTL_CLKB
LVPECL_CLKB
HSTL_CLKA
LVPECL_CLKA
HSTL_CLKB
LVPECL_CLKB
LOW
LOW
LOW
LOW
LOW
/HSTL_CLKA
/LVPECL_CLKA
/HSTL_CLKB
/LVPECL_CLKB
/HSTL_CLKB
/LVPECL_CLKB
/HSTL_CLKA
/HSTL_CLKA
/LVPECL_CLKA
/LVPECL_CLKA
/HSTL_CLKB
/LVPECL_CLKB
/HSTL_CLKA
/LVPECL_CLKA
/HSTL_CLKB
/LVPECL_CLKB
HIGH
HIGH
HIGH
HIGH
HIGH
Note 1. Input has internal pull-up Floating input = 1.
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SY89827L
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PIN DESCRIPTIONS
Pin Number
Pin Name
I/O
Type
Internal
P/U
Pin Function
5, 6
HSTL_CLKA
Input
HSTL
/HSTL_CLKA
Differential clock input selected by CLK_SEL1, SEL1 and SEL2. Can be left floating if not selected. Floating input, if selected produces an indeterminate output. HSTL input signal requires external termination 50Ω-to-GND.
2, 3
HSTL_CLKB
Input
HSTL
/HSTL_CLKB
Differential clock input selected by CLK_SEL1, SEL1 and SEL2. Can be left floating if not selected. Floating input, if selected produces an indeterminate output. HSTL input signal requires external termination 50Ω-to-GND.
8, 9
LVPECL_CLKA Input LVPECL 75kΩ
Differential clock input selected by CLK_SEL1, SEL1 and SEL2. /LVPECL_CLKA
pull-down Can be left floating. Floating input, if selected produces a LOW at output. Requires external termination. See Figure 1.
12, 13
LVPECL_CLKB Input LVPECL 75kΩ
Differential clock input selected by CLK_SEL2, SEL1 and SEL2. /LVPECL_CLKB
pull-down Requires external termination. See Figure 1.
7
CLK_SEL1
Input
LVTTL/
CMOS
11kΩ
Pull-up
Selects HSTL_CLKA input when LOW and LVPECL_CLKA input when HIGH.
14
CLK_SEL2
Input
LVTTL/
CMOS
11kΩ
Pull-up
Selects HSTL_CLKB input when LOW and LVPECL_CLKB input when HIGH.
16
SEL1
Input
LVTTL/
CMOS
11kΩ
Pull-up
Selects input source CLKA when LOW and CLKB when HIGH for outputs Q0 – Q9 and /Q0 – /Q9.
1
SEL2
Input
LVTTL/
CMOS
11kΩ
Pull-up
Selects input source CLKA when LOW and CLKB when HIGH for outputs Q10 – Q19 and /Q10 – /Q19.
11
OE1
Input
LVTTL/
CMOS
11kΩ
Pull-up
Enable input synchronized internally to prevent glitching of the
Q0 – Q9 and /Q0 – /Q9 outputs.
15
OE2
Input
LVTTL/
CMOS
11kΩ
Pull-up
Enable input synchronized internally to prevent glitching of the
Q10 – Q19 and /Q10 – /Q19 outputs.
4
VCCI
Power
Core VCC connected to 3.3V supply. Bypass with 0.1µF in parallel with 0.01µF low ESR capacitors as close to VCC pins as possible.
17, 32, 33,
VCCO
Power
40, 41, 48, 49, 64
Output buffer VCC connected to 1.8V nominal supply. All VCCO pins should be connected together on the PCB. Bypass with 0.1µF in parallel with 0.01µF low ESR capacitors as close to VCCO pins as possible.
Ground.
10
GND
Power
63, 61, 59, 57, 55
Q0 – Q9
Output HSTL
53, 51, 47, 45, 43
Differential clock outputs from CLKA when SEL1 = LOW and from CLKB when SEL1 = HIGH. HSTL outputs (Q and /Q) must be terminated with 50Ω-to-GND. Q outputs are static when
OE1 = LOW. Unused output pairs may be left floating.
62, 60, 58, 56, 54
/Q0 – /Q9
Output HSTL
52, 50, 46, 44, 42
Differential clock outputs (complement) from CLKA when SEL1 = LOW and from CLKB when SEL1 = HIGH. HSTL outputs (Q and /Q) must be terminated with 50Ω-to-GND. /Q outputs are static HIGH when OE1 = LOW. Unused output pairs may be left floating.
39, 37, 35, 31, 29
Q10 – Q19
Output HSTL
27, 25, 23, 21, 19
Differential outputs from CLKA when SEL2 = LOW and from CLKB when SEL2 = HIGH. HSTL outputs (Q and /Q) must be terminated with 50Ω-to-GND. Q outputs are static LOW when OE2 = LOW. Unused output pairs may be left floating.
38, 36, 34, 30, 28 /Q10 – /Q19 Output HSTL
26, 24, 22, 20, 18
Differential outputs (complement) from CLKA when SEL2 = LOW and from CLKB when SEL2 = HIGH. HSTL outputs (Q and /Q) must be terminated with 50Ω-to-GND. /Q outputs are static HIGH when OE2 = LOW. Unused output pairs may be left floating.
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Precision Edge®
SY89827L
Micrel, Inc.
Absolute Maximum Ratings(Note 1)
Operating Ratings(Note 2)
Power Supply Voltage (VCCI, VCCO)................ –0.5 to +4.0V
Input Voltage (VIN)............................................. –0.5 to VCCI
Output Current (IOUT)................................................ –50mA
Lead Temperature (TLEAD, Soldering, 20sec.)........... 260°C
Storage Temperature (TS)............................. –65 to +150°C
ESD Rating, Note 3 . ................................................... >1kV
Supply Voltage
(VCCI)...................................................... +3.3V to +3.47V
(VCCO)...................................................... +1.6V to +2.0V
Ambient Temperature (TA)........................... –40°C to +85°C
Package Thermal Resistance
TQFP (θJA)
Exposed pad soldered to GND, Note 4
Still-Air (multi-layer PCB).......................................... 23°C/W
–200lfpm (multi-layer PCB). .................................... 18°C/W
–500lfpm (multi-layer PCB). .................................... 15°C/W
Exposed pad NOT soldered to GND (not recommended)
Still-Air (multi-layer PCB).......................................... 44°C/W
–200lfpm (multi-layer PCB). .................................... 36°C/W
–500lfpm (multi-layer PCB). .................................... 30°C/W
TQFP (θJC).......................................................... 4.4°C/W
DC ELECTRICAL CHARACTERISTICS
Power Supply: TA = –40°C to +85°C
Symbol
Parameter
VCCI
VCC Core
VCCO
ICCI
Condition
VCC Output
ICC Core
Min
Typ
Max
Units
3.13
3.3
3.47
V
1.6
No Load
HSTL Input/Output: VCCI = 3.3V ±5%, VCCO = 1.8V ±10%, TA = –40°C to +85°C
1.8
2.0
V
140
170
mA
Typ
Max
Units
1.2
V
Symbol
Parameter
Condition
Min
VOH
Output HIGH Voltage
Note 5
1.0
Output LOW Voltage
Note 5
VIH
Input HIGH Voltage
VX
Input Crossover Voltage
0.68
Input HIGH Current
IIL
VOL
VIL
IIH
0.2
0.4
V
VX +0.1
1.6
V
VX –0.1
V
0.9
V
+20
–350
µA
Input LOW Current
–500
µA
Input LOW Voltage
–0.3
Note 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended periods may affect device reliability.
Note 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
Note 3. Devices are ESD sensitive. Handling precautions recommended.
Note 4. It is highly recommended to solder the exposed pad of the EPAD-TQFP package to a ground plane on the PCB for maximum thermal
efficiency.
Note 5. Outputs loaded with 50Ω-to-ground.
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Precision Edge®
SY89827L
Micrel, Inc.
DC ELECTRICAL CHARACTERISTICS
LVPECL Input: VCCI = 3.3V ±5%, TA = –40°C to +85°C
Symbol
Parameter
VIH
Input HIGH Voltage (Single-Ended)
VPP
Minimum Input Swing (LVPECL_CLK) Note 6
IIH
Input HIGH Current
VIL
VCMR
IIL
Condition
Min
VCCI –1.165
Input LOW Voltage
Common Mode Range (LVPECL_CLK)
Typ
VCCI –1.945
Max
Units
VCCI –0.880
V
VCCI –1.625
300
Note 7
GNDI +1.8
Input LOW Current
VCCI –0.4
150
0.5
V
mV
V
µA
µA
Note 6. The VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay.
Note 7. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The numbers in the table are referenced to VCCI. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal
to VPP (min.). VCMR range varies 1:1 with VCCI. VCMR (min) is fixed at GNDI +1.8V
CMOS/LVTTL Inputs: VCCI = 3.3V ±5%, VCCO = 1.8V ±10%, TA = –40°C to +85°C
Symbol
Parameter
VIH
Input HIGH Voltage
IIH
Input HIGH Current
VIL
IIL
Condition
Min
Typ
Max
2.0
Input LOW Voltage
0.8
Units
V
V
+20
–250
µA
Input LOW Current
–600
µA
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Precision Edge®
SY89827L
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AC ELECTRICAL CHARACTERISTICS(Note 1)
VCCI = 3.3V ±5%, VCCO = 1.8V ±10%, TA = –40°C to +85°C, all outputs loaded, unless noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
Maximum Toggle Frequency
Note 2
500
MHz
Differential Propagation Delay
Note 3
1.0
1.3
1.5
ns
Minimum Input Swing, Note 4
VPP
HSTL
PECL
200
150
Switchover Time
tSW
CLK_SEL-to-Q
SEL-to-Q
1.6
1.4
2.0
1.75
tJITTER
RMS Phase Jitter
Output: 622MHz
Integration Range: 12kHz - 20MHz
186
fs
tS(OE)
Output Enable Set-Up Time
Note 5
1.0
ns
Output Enable Hold Time
Note 5
0.5
ns
fMAX
tPD
tH(OE)
Within Device Skew
Note 6
tskew
0°C to +85°C
–40°C
25
35
Note 7
Part-to-Part Skew
tr, tf
Output Rise/Fall Times
(20% to 80%)
450
50
75
mV
mV
ns
ns
ps
ps
400
ps
700
ps
Note 1. Outputs loaded with 50Ω-t- ground.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Note 7.
fMAX is defined as the maximum toggle frequency, measured with a 750mV LVPECL/HSTL input. HSTL output swing is > 400mV.
Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the
differential output signals.
The VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay.
OE set-up time is defined with respect to the rising edge of the clock. OE HIGH-to-LOW transition ensures outputs remain disabled during the
next clock cycle. OE LOW-to-HIGH transition enables normal operation of the next input clock.
The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the
same voltage and temperature. This parameters includes within bank skew and bank-to-bank skew.
The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same
voltage and temperature.
Phase Noise
0
-10
RMS Phase Jitter (Random)
12kHz to 20MHz: 186fs (Typical)
-20
-30
NOISEPOWER(dBc/Hz)
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
10
100
1K
10K
100K
1M
OFFSETFREQUENCY(Hz)
Phase Noise Plot: 622MHz @ 3.3V
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10M
100M
Precision Edge®
SY89827L
Micrel, Inc.
TYPICAL OPERATING CHARACTERISTICS
VCCI = 3.3V, VCCO = 1.8V, TA = 25°C, unless otherwise stated.
Output Amplitude
vs.Frequency
PROPAGATION DELAY (ps)
700
600
500
400
300
200
100
0
0
200 400 600 800
FREQUENCY(MHz)
1000
PECL INPUT
800
600
400
200
0
0
1400
8
HSTL INPUT
1200
1000
800
LVPECL INPUT
600
400
200
-25
0
25 50 75
TEMPERATURE ( °C)
100
CLK_SELSwitchoverTime
vs.Temperature
1600
1400
1200
1000
800
600
400
200
0
-50
200 400 600 800 1000
INPUT AMPLITUDE (mV)
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1600
1800
HSTL INPUT
1200
NominalPropagationDelay
vs.Temperature
1800
0
-50
1000
PropagationDelay
vs.InputAmplitude
1400
PROPAGATION DELAY (ns)
2000
SWITCHOVER TIME (ns)
OUTPUT AMPLITUDE (mV)
800
-25
0
25 50 75
TEMPERATURE ( °C)
100
Precision Edge®
SY89827L
Micrel, Inc.
FUNCTIONAL CHARACTERISTICS
VCCI = 3.3V, VCCO = 1.8V, TA = 25°C, unless otherwise stated.
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Precision Edge®
SY89827L
Micrel, Inc.
LVPECL/HSTL INPUTS
Figure 2. Simplified HSTL Input Stage
Figure 1. Simplified LVPECL Input Stage
HSTL OUTPUTS
QOUT
QOUT
1.6V
QOUT — /QOUTT
800mV
/QOUT
/QOUT
Figure 4. Output Driver Signal Levels
(Differential)
Figure 3. Output Driver Signal Levels
(Single-Ended)
RELATED PRODUCT AND SUPPORT DOCUMENTATION
Part Number Function
Data Sheet Link
SY89809L
3.3V 1:9 High-Performance, Low-Voltage Bus Clock Driver
www.micrel.com/product-info/products/sy89809l.shtml
SY89824L
3.3V 1:22 High-Performance, Low-Voltage Bus Clock Driver
www.micrel.com/product-info/products/sy89824l.html
Exposed Pad Application Note
www.amkor.com/products/notes_papers/epad.pdf
M-0317
HBW Solutions
www.micrel.com/product-info/products/solutions.shtml
MIC3775
750mA µCap Low-Voltage Low-Dropout Regulator
www.micrel.com/product-info/products/mic3775.shtml
M9999-073010
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Precision Edge®
SY89827L
Micrel, Inc.
64-PIN EPAD-tqfP (DIE UP) (H64-1)
+0.05
–0.05
+0.002
–0.002
+0.05
–0.05
+0.012
–0.012
+0.03
–0.03
+0.012
–0.012
+0.15
–0.15
+0.006
–0.006
+0.05
–0.05
+0.002
–0.002
Package
EP- Exposed Pad
Die
CompSide Island
Heat Dissipation
Heat Dissipation
Heavy Copper Plane
Heavy Copper Plane
VEE
VEE
PCB Thermal Consideration for 64-Pin EPAD-TQFP Package
(Always solder, or equivalent, the exposed pad to the PCB)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
tel
+ 1 (408) 944-0800
fax
+ 1 (408) 944-0970
web
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The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2002 Micrel, Incorporated.
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