Revised April 2005 74VHCT574A Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The VHCT574A is an advanced high speed CMOS octal flip-flop with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type flipflop is controlled by a clock input (CP) and an Output Enable input (OE). When the OE input is HIGH, the eight outputs are in a high impedance state. ■ High speed: fMAX Protection circuits ensure that 0V to 7V can be applied to the input and output (Note 1) pins without regard to the supply voltage. This device can be used to interface 3V to 5V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. 140 MHz (typ) at TA 25qC ■ Power Down Protection is provided on all inputs and outputs. ■ Low Noise: VOLP 1.6V (max) ■ Low Power Dissipation: ICC 4 PA (max) @ TA 25qC ■ Pin and Function Compatible with 74HCT574 Note 1: Outputs in OFF-State. Ordering Code: Order Number Package Number 74VHCT574AM 74VHCT574ASJ 74VHCT574AMTC 74VHCT574AN Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC20 N20A 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Logic Symbol Connection Diagram IEEE/IEC © 2005 Fairchild Semiconductor Corporation DS500029 www.fairchildsemi.com 74VHCT574A Octal D-Type Flip-Flop with 3-STATE Outputs July 1997 74VHCT574A Pin Descriptions Pin Names Truth Table Description Inputs D0–D7 Data Inputs Dn CP Clock Pulse Input 3-STATE H OE Output Enable Input 3-STATE L O0–O7 Outputs X CP Outputs OE On L H L L X H Z H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance LOW-to-HIGH Transition Functional Description tion. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops. The VHCT574A consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transi- Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions (Note 6) 0.5V to 7.0V 0.5V to 7.0V Supply Voltage (VCC) DC Input Voltage (VIN) 4.5V to 5.5V Supply Voltage (VCC) DC Output Voltage (VOUT ) 0V to 5.5V Input Voltage (VIN) (Note 3) (Note 4) Input Diode Current (IIK) Output Diode Current (IOK) (Note 5) DC Output Current (IOUT ) DC VCC/GND Current (ICC) Storage Temperature (TSTG) 0.5V to VCC 0.5V 0.5V to 7.0V 20 mA r20 mA r25 mA r75 mA 65qC to 150qC Output Voltage (VOUT) 0V to VCC (Note 4) 0V to 5.5V 40qC to 85qC Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC 5.0V r 0.5V 0 ns/V a 20 ns/V Note 2: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Lead Temperature (TL) 260qC (Soldering, 10 seconds) (Note 3) Note 3: HIGH or LOW state. IOUT absolute maximum rating must be observed. Note 4: When outputs are in OFF-State or when VCC OV. Note 5: VOUT GND, V OUT ! VCC (Outputs Active). Note 6: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH Parameter 25qC TA Typ Max 40qC to 85qC Min 4.5 2.0 2.0 5.5 2.0 20 Max 4.5 0.8 0.8 Input Voltage 5.5 0.8 0.8 HIGH Level LOW Level 3-STATE Output Input Leakage 4.5 4.5 4.40 4.50 3.94 0.0 Units Conditions V LOW Level Off-State Current IIN TA Min Input Voltage Output Voltage IOZ (V) HIGH Level Output Voltage VOL VCC V 4.40 V 3.80 V 0.1 0.1 V 0.36 0.44 V VIN VIH 50 PA IOH or VIL IOH 8 mA VIN VIH IOL 50 PA or VIL IOL 8 mA VIN VIH or VIL 5.5 r0.25 r2.5 PA 0–5.5 r0.1 r1.0 PA VIN 5.5V or GND 5.5 4.0 40.0 PA VIN VCC or GND 5.5 1.35 1.50 mA VIN 3.4V VOUT VCC or GND Current ICC Quiescent Supply Current ICCT Maximum ICC/Input Other Input IOFF Output Leakage Current 0.0 0.5 5.0 PA VOUT VCC or GND 5.5V (Power Down State) 3 www.fairchildsemi.com 74VHCT574A Absolute Maximum Ratings(Note 2) 74VHCT574A Noise Characteristics VOLP TA 25qC VCC (V) Typ Limits Quiet Output Maximum Dynamic VOL 5.0 1.2 1.6 V CL 50 pF Quiet Output Minimum Dynamic VOL 5.0 1.2 1.6 V CL 50 pF Minimum HIGH Level Dynamic Input Voltage 5.0 2.0 V CL 50 pF Maximum LOW Level Dynamic Input Voltage 5.0 0.8 V CL 50 pF Symbol Parameter Units Conditions (Note 7) VOLV (Note 7) VIHD (Note 7) VILD (Note 7) Note 7: Parameter guaranteed by design. AC Electrical Characteristics Symbol tPLH Propagation Delay tPHL Time tPZL 3-STATE Output tPZH Enable Time tPLZ 3-STATE Output tPHZ Disable Time tOSLH Output to tOSHL Output Skew fMAX (V) TA Min 5.0 r 0.5 5.0 r 0.5 5.0 r 0.5 25qC Typ Maximum Clock 5.0 r 0.5 TA Max 40qC to 85qC Min Max 4.1 9.4 1.0 10.5 10.4 1.0 11.5 6.5 10.2 1.0 11.5 7.3 11.2 1.0 12.5 7.0 11.2 1.0 12.0 ns 1.0 ns 1.0 90 140 80 85 130 75 Input Units 5.6 5.0 r 0.5 Frequency CIN VCC Parameter 4 Conditions ns ns 1 k: RL 1 k: RL 10 15 pF CL 50 pF CL 15 pF CL 50 pF CL 50 pF CL 15 pF CL 50 pF (Note 8) MHz 10 CL pF VCC Open 9 pF VCC 5.0V 25 pF (Note 9) Capacitance COUT Output Capacitance CPD Power Dissipation Capacitance Note 8: Parameter guaranteed by design. tOSLH |tPLH max t PLH min|; tOSHL |tPHL max tPHL min| Note 9: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) CPD * VCC * fIN ICC/8 (per F/F). The total CPD when n pcs. of the Octal D Flip-Flop operates can be calculated by the equation: CPD (total) 20 12n. AC Operating Requirements Symbol tW(H) Parameter Minimum Pulse Width (CP) tW(L) TA 25qC TA 40qC to 85qC VCC (V) Min 5.0 r 0.5 6.5 8.5 Typ Max Min tS Minimum Set-Up Time 5.0 r 0.5 2.5 2.5 tH Minimum Hold Time 5.0 r 0.5 2.5 2.5 www.fairchildsemi.com 4 Units Max ns ns 74VHCT574A Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com 74VHCT574A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74VHCT574A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com 74VHCT574A Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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