FDD24AN06LA0_F085 N-Channel Logic Level PowerTrench® MOSFET 60V, 36A, 24mΩ Features Applications • r DS(ON) = 20mΩ (Typ.), VGS = 5V, ID = 36A • Motor / Body Load Control • Qg(tot) = 16nC (Typ.), VGS = 5V • ABS Systems • Low Miller Charge • Powertrain Management • Low QRR Body Diode • Injection Systems • UIS Capability (Single Pulse and Repetitive Pulse) • DC-DC converters and Off-line UPS • Qualified to AEC Q101 • Distributed Power Architectures and VRMs • RoHS Compliant • Primary Switch for 12V and 24V systems Formerly developmental type 83547 DRAIN (FLANGE) GATE D G SOURCE TO-252AA FDD SERIES S MOSFET Maximum Ratings TC = 25°C unless otherwise noted Symbol V DSS Drain to Source Voltage Parameter Ratings 60 Units V VGS Gate to Source Voltage ±20 V Drain Current ID Continuous (TC = 25oC, VGS = 10V) 40 A Continuous (TC = 25oC, VGS = 5V) 36 A Continuous (TC = 100oC, VGS = 5V) 25 A Continuous (TA = 25oC, VGS = 5V, RθJA = 52oC/W) 7.1 A Pulsed E AS PD TJ, TSTG Single Pulse Avalanche Energy (Note 1) Figure 4 A 32 mJ Power dissipation 75 W Derate above 25oC 0.5 W/oC Operating and Storage Temperature o C -55 to 175 Thermal Characteristics RθJC Thermal Resistance Junction to Case TO-252 2.0 oC/W RθJA Thermal Resistance Junction to Ambient TO-252 100 o C/W RθJA Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area 52 o C/W This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html. All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification. ©2011 Fairchild Semiconductor Corporation FDD24AN06LA0_F085 Rev. C1 www.fairchildsemi.com FDD24AN06LA0_F085 N-Channel Logic Level PowerTrench® MOSFET August 2011 Device Marking FDD24AN06LA0 Device FDD24AN06LA0 Package TO-252AA Reel Size 330mm Tape Width 16mm Quantity 2500 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units 60 - - - V - 1 - - 250 µA VGS = ±20V - - ±100 nA V GS = VDS, ID = 250µA 1 - 2 V ID = 40A, VGS = 10V - 0.016 0.019 ID = 36A, VGS = 5V - 0.020 0.024 ID = 36A, VGS = 5V, TJ = 175oC - 0.047 0.056 - 1850 - - 180 - pF - 75 - pF 16 21 nC - 1.8 2.4 nC - 6.3 - nC - 4.5 - nC - 5.0 - nC Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V V DS = 50V VGS = 0V TC = 150oC On Characteristics VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance Ω Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance V DS = 25V, VGS = 0V, f = 1MHz Qg(TOT) Total Gate Charge at 5V VGS = 0V to 5V Qg(TH) Threshold Gate Charge VGS = 0V to 1V Qgs Gate to Source Gate Charge Qgs2 Gate Charge Threshold to Plateau Qgd Gate to Drain “Miller” Charge VDD = 30V ID = 36A Ig = 1.0mA pF Switching Characteristics (VGS = 5V) tON Turn-On Time - - 195 ns td(ON) Turn-On Delay Time - 12 - ns tr Rise Time td(OFF) Turn-Off Delay Time - 118 - ns - 26 - tf ns Fall Time - 41 - tOFF ns Turn-Off Time - - 101 ns V DD = 30V, ID = 36A VGS = 5V, RGS = 9.1Ω Drain-Source Diode Characteristics ISD = 36A - - 1.25 V ISD = 18A - - 1.0 V Reverse Recovery Time ISD = 36A, dISD/dt = 100A/µs - - 34 ns Reverse Recovered Charge ISD = 36A, dISD/dt = 100A/µs - - 30 nC V SD Source to Drain Diode Voltage trr QRR Notes: 1: Starting T J = 25°C, L = 80µH, I AS = 28A. ©2011 Fairchild Semiconductor Corporation FDD24AN06LA0_F085 Rev. C1 www.fairchildsemi.com FDD24AN06LA0_F085 N-Channel Logic Level PowerTrench® MOSFET Package Marking and Ordering Information 50 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 40 VGS = 10V 30 VGS = 5V 20 10 0.2 0 25 0 50 75 100 150 125 0 175 25 50 75 TC , CASE TEMPERATURE (oC) 100 125 150 175 TC, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Ambient Temperature Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE 0.01 10-5 10 -4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance IDM, PEAK CURRENT (A) 400 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION CURRENT AS FOLLOWS: VGS = 10V 100 30 175 - TC I = I25 150 VGS = 5V 10 -5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) Figure 4. Peak Current Capability ©2011 Fairchild Semiconductor Corporation FDD24AN06LA0_F085 Rev. C1 www.fairchildsemi.com FDD24AN06LA0_F085 N-Channel Logic Level PowerTrench® MOSFET Typical Characteristics TC = 25°C unless otherwise noted 1000 100 100 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 10µs 100µs 1ms 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 10ms DC SINGLE PULSE TJ = MAX RATED TC = 25 oC 10 STARTING TJ = 150oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 1 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 0.001 0.01 0.1 1 NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 6. Unclamped Inductive Switching Capability 60 60 VGS = 10V ID, DRAIN CURRENT (A) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V 45 30 TJ = 175oC TJ = 25 oC 15 VGS = 5V VGS = 3.5V 45 30 VGS = 3V 15 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TJ = -55o C 0 TC = 25oC 0 1 3 2 4 0 1.0 0.5 VGS , GATE TO SOURCE VOLTAGE (V) 1.5 2.0 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics 50 2.5 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON), DRAIN TO SOURCE ON RESISTANCE (mΩ) 100 10 tAV, TIME IN AVALANCHE (ms) Figure 5. Forward Bias Safe Operating Area ID , DRAIN CURRENT (A) STARTING TJ = 25oC 40 ID = 40A 30 20 ID = 5A PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 2.0 1.5 1.0 0.5 VGS = 10V, ID = 40A 0 10 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 9. Drain to Source On Resistance vs Gate Voltage and Drain Current ©2011 Fairchild Semiconductor Corporation FDD24AN06LA0_F085 Rev. C1 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (o C) Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature www.fairchildsemi.com FDD24AN06LA0_F085 N-Channel Logic Level PowerTrench® MOSFET Typical Characteristics TC = 25°C unless otherwise noted 1.10 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.25 NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250µA 1.00 0.75 0.50 ID = 250µA 1.05 1.00 0.95 0.25 0.90 -80 -40 0 40 80 120 160 200 -80 -40 TJ, JUNCTION TEMPERATURE (oC) Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature 80 120 160 200 10 VGS , GATE TO SOURCE VOLTAGE (V) C, CAPACITANCE (pF) 40 Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 2500 CISS = CGS + C GD 1000 COSS ≅ CDS + C GD CRSS = CGD 100 40 0 TJ , JUNCTION TEMPERATURE (oC) VGS = 0V, f = 1MHz 1 0.1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 13. Capacitance vs Drain to Source Voltage ©2011 Fairchild Semiconductor Corporation FDD24AN06LA0_F085 Rev. C1 60 VDD = 30V 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 36A ID = 5A 2 0 0 5 10 15 20 Qg, GATE CHARGE (nC) 25 30 Figure 14. Gate Charge Waveforms for Constant Gate Current www.fairchildsemi.com FDD24AN06LA0_F085 N-Channel Logic Level PowerTrench® MOSFET Typical Characteristics TC = 25°C unless otherwise noted VDS BVDSS tP L VARY tP TO OBTAIN + RG REQUIRED PEAK IAS - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS + - VGS VGS = 5V Qgs2 VDD DUT VGS = 1V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS 90% - VDD 10% 10% 0 DUT 90% VGS VGS 0 Figure 19. Switching Time Test Circuit ©2011 Fairchild Semiconductor Corporation FDD24AN06LA0_F085 Rev. C1 90% + VGS RGS tf 50% 10% PULSE WIDTH 50% Figure 20. Switching Time Waveforms www.fairchildsemi.com FDD24AN06LA0_F085 N-Channel Logic Level PowerTrench® MOSFET Test Circuits and Waveforms (T –T ) JM A P D M = ----------------------------R θ JA (EQ. 1) In using surface mount devices such as the TO-252 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 125 RθJA = 33.32+ 23.84/(0.268+Area) EQ.2 RθJA = 33.32+ 154/(1.73+Area) EQ.3 100 RθJA (o C/W) The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. 75 50 25 0.01 (0.0645) 0.1 (0.645) 1 (6.45) 10 (64.5) AREA, TOP COPPER AREA in2 (cm2 ) Figure 21. Thermal Resistance vs Mounting Pad Area 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the RθJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. R θ JA 23.84 ( 0.268 + Area ) = 33.32 + ------------------------------------- (EQ. 2) Area in Inches Squared R θ JA 154 ( 1.73 + Area ) = 33.32 + ---------------------------------- (EQ. 3) Area in Centimeters Squared ©2011 Fairchild Semiconductor Corporation FDD24AN06LA0_F085 Rev. C1 www.fairchildsemi.com FDD24AN06LA0_F085 N-Channel Logic Level PowerTrench® MOSFET Thermal Resistance vs. Mounting Pad Area TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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