NC7WZ17 TinyLogic® UHS Dual Buffer with Schmitt Trigger Inputs Features Description Ultra-High Speed: tPD 3.6ns (Typical) into 50pF at 5V VCC High Output Drive: ±24mA at 3V VCC Power Down High Impedance Inputs/Outputs Proprietary Noise/EMI Reduction Circuitry The NC7WZ17 is a dual buffer with Schmitt trigger inputs from Fairchild's Ultra-High Speed (UHS) series of TinyLogic® products. The device is fabricated with advanced CMOS technology to achieve ultra-high speed with high output drive, while maintaining low static power dissipation over a very broad VCC operating range. The device is specified to operate over the 1.65V to 5.5V VCC range. The inputs and outputs are high-impedance when VCC is 0V. Inputs tolerate voltages up to 7V, independent of VCC operating voltage. Schmitt trigger inputs achieve 1V typical hysteresis between the positive- and negativegoing input threshold voltage at 5V. Broad VCC Operating Range: 1.65V to 5.5V Matches Performance of LCX when Operated at 3.3V VCC Over-Voltage Tolerance Inputs Facilitate 5V to 3V Translation Ultra-Small MicroPak™ Packages Space-Saving SC70 Package Ordering Information Operating Temperature Top Mark NC7WZ17P6X -40 to +85°C Z17 6-Lead SC70, EIAJ SC-88a, 1.25mm Wide 3000 Units on Tape & Reel NC7WZ17L6X -40 to +85°C A5 6-Lead MicroPak™, 1.00mm Wide 5000 Units on Tape & Reel NC7WZ17FHX -40 to +85°C A5 6-Lead, MicroPak2, 1x1mm Body, .35mm Pitch 5000 Units on Tape & Reel Part Number © 1999 Fairchild Semiconductor Corporation NC7WZ17 • Rev. 1.0.6 Package Packing Method www.fairchildsemi.com NC7WZ17 — TinyLogic® UHS Dual Buffer with Schmitt Trigger Inputs January 2012 IEEC/IEC A1 Y1 1 A2 Y2 Figure 1. Logic Symbol Pin Configurations A1 1 6 Y1 GND 2 5 VCC A2 3 4 Y2 Figure 2. SC70 (Top View) A1 1 6 Y1 GND 2 5 VCC A2 3 4 Y2 Figure 3. MicroPak (Top Through View) AAA Pin One Notes: 1. AAA represents Product Code Top Mark (see ordering code). 2. Orientation of Top Mark determines Pin One location. Read the top product code mark left to right. Pin One is the lower left pin. Figure 4. SC70 Pin 1 Orientation NC7WZ17 — TinyLogic® UHS Dual Buffer with Schmitt Trigger Inputs Connection Diagrams Pin Definitions Pin # SC70 Pin # MicroPak Name Description 1 1 A1 2 2 GND 3 3 A2 Input 4 4 Y2 Output 5 5 VCC Supply Voltage 6 6 Y1 Output Input Ground Function Table Y=A Inputs Output A Y L L H H H = HIGH Logic Level L = LOW Logic Level © 1999 Fairchild Semiconductor Corporation NC7WZ17 • Rev. 1.0.6 www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCC Supply Voltage -0.5 7.0 V VIN DC Input Voltage -0.5 7.0 V VOUT 7.0 V IIK DC Input Diode Current VIN < -0.5V -50 mA IOK DC Output Diode Current VOUT < -0.5V -50 mA IOUT DC Output Current ±50 mA DC VCC or Ground Current ±100 mA +150 °C +150 °C +260 °C ICC or IGND TSTG DC Output Voltage -0.5 Storage Temperature Range -65 TJ Junction Temperature Under Bias TL Junction Lead Temperature (Soldering, 10 Seconds) PD Power Dissipation at 85°C SC70-6 180 MicroPak-6 130 MicroPak2-6 ESD mW 120 Human Body Model, JEDEC:JESD22-A114 4000 Charge Device Model, JEDEC:JESD22-C101 2000 V Recommended Operating Conditions(3) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCC VIN VOUT TA JA Parameter Conditions Min. Max. Supply Voltage Operating 1.65 5.50 Supply Voltage Data Retention 1.5 5.5 Input Voltage 0 5.5 V Output Voltage 0 VCC V -40 +85 °C Operating Temperature Thermal Resistance SC70-6 350 MicroPak-6 500 MicroPak2-6 560 NC7WZ17 — TinyLogic® UHS Dual Buffer with Schmitt Trigger Inputs Absolute Maximum Ratings Unit V °C/W Note: 3. Unused inputs must be held HIGH or LOW. They may not float. © 1999 Fairchild Semiconductor Corporation NC7WZ17 • Rev. 1.0.6 www.fairchildsemi.com 3 Symbol VP VN VH Parameter Positive Threshold Voltage Negative Threshold Voltage Hysteresis Voltage VCC (V) Min. 1.00 1.40 0.60 1.40 1.07 1.50 0.70 1.50 2.30 1.00 1.38 1.80 1.00 1.80 3.00 1.30 1.74 2.20 1.30 2.20 4.50 1.90 2.43 3.10 1.90 3.10 5.50 2.20 2.88 3.60 2.20 3.60 1.65 0.20 0.50 0.80 0.20 0.80 1.80 0.25 0.56 0.90 0.25 0.90 2.30 0.40 0.75 1.15 0.40 1.15 3.00 0.60 0.98 1.50 0.60 1.50 4.50 1.00 1.42 2.00 1.00 2.00 5.50 1.20 1.68 2.30 1.20 2.30 1.65 0.10 0.48 0.90 0.10 0.90 1.80 0.15 0.51 1.00 0.15 1.00 2.30 0.25 0.62 1.10 0.25 1.10 3.00 0.40 0.76 1.20 0.40 1.20 4.50 0.60 1.01 1.50 0.60 1.50 5.50 0.70 1.20 1.70 0.70 1.70 1.65 1.55 1.65 1.55 1.70 1.80 1.70 2.20 2.30 2.20 3.00 2.90 3.00 2.90 4.50 4.40 4.50 4.40 VIN=VIH, IOH=-100µA 1.65 IOH=-4mA 1.29 1.52 1.29 2.30 IOH=-8mA 1.90 2.14 1.90 3.00 IOH=-16mA 2.40 2.75 2.40 3.00 IOH=-24mA 2.30 2.62 2.30 4.50 IOH=-32mA 3.80 4.13 IIN Input Leakage Current IOFF Power Off Leakage Current ICC Quiescent Supply Current © 1999 Fairchild Semiconductor Corporation NC7WZ17 • Rev. 1.0.6 V V 3.80 0.10 0.10 0.00 0.10 0.10 0.00 0.10 0.10 3.00 0.00 0.10 0.10 4.50 0.00 0.10 0.10 VIN=VIL, IOL=100µA V V 0.00 2.30 Units Max. 0.60 1.80 LOW Level Output Voltage Min. 0.70 1.65 VOL Max. 1.65 2.30 HIGH Level Output Voltage Typ. TA=-40 to 85°C 1.80 1.80 VOH TA=25°C Conditions V 1.65 IOL=4mA 0.08 0.24 0.24 2.30 IOL=8mA 0.10 0.30 0.30 3.00 IOL=16mA 0.16 0.40 0.40 3.00 IOL=24mA 0.24 0.55 0.55 4.50 IOL=32mA 0.25 0.55 0.55 ±0.1 ±1.0 µA VIN or VOUT=5.5V 1 10 µA VIN=5.5V, GND 1 10 µA 0 to 5.5 0 1.65 to 5.50 VIN=5.5V, GND NC7WZ17 — TinyLogic® UHS Dual Buffer with Schmitt Trigger Inputs DC Electrical Characteristics www.fairchildsemi.com 4 Symbol Parameter VCC (V) Conditions Min. Typ. Propagation Delay 2.0 8.3 14.3 2.0 15.8 6.9 11.9 2.0 13.1 1.5 4.8 8.2 1.5 9.0 3.30 ± 0.30 1.0 3.7 5.6 1.0 6.2 5.00 ± 0.50 0.8 3.0 4.7 0.8 5.2 CL=15pF, RL=1M CL=50pF, RL=500 1.5 4.3 6.6 1.5 7.3 1.0 3.6 5.6 1.0 6.2 Input Capacitance 0.00 2.5 Power Dissipation (4) Capacitance 3.30 10.0 5.00 12.0 Units Figure Max. 2.0 5.00 ± 0.50 CPD Min. 1.80 3.30 ± 0.30 CIN Max. 1.65 2.50 ± 0.20 tPLH, tPHL TA=-40 to 85°C TA=25°C Figure 5 Figure 6 ns Figure 5 Figure 6 pF pF Figure 7 Note: 4. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output loading and operating at 50% duty cycle. CPD is related to ICCD dynamic operating current by the expression: ICCD=(CPD)(VCC)(fIN)+(ICCstatic). tf = 3ns tr = 3ns VCC VCC 90% Input Input CL 50% 10% GND Output 90% 50% tW RL tPHL tPLH Note: 5. CL includes load and stray capacitance; Input PRR=1.0MHz; tW =500ns 10% NC7WZ17 — TinyLogic® UHS Dual Buffer with Schmitt Trigger Inputs AC Electrical Characteristics VOH Output 50% 50% VOL Figure 5. AC Test Circuit Figure 6. AC Waveforms VCC A Input Note: 6. Input=AC Waveform; tr=tf=1.8ns; PRR=10MHz; Duty Cycle =50%. Figure 7. ICCD Test Circuit © 1999 Fairchild Semiconductor Corporation NC7WZ17 • Rev. 1.0.6 www.fairchildsemi.com 5 NC7WZ17 — TinyLogic® UHS Dual Buffer with Schmitt Trigger Inputs Physical Dimensions SYMM C L 2.00±0.20 0.65 A 0.50 MIN 6 4 B PIN ONE 1.25±0.10 1 1.90 3 0.30 0.15 0.10 (0.25) 0.65 0.40 MIN A B 1.30 LAND PATTERN RECOMMENDATION 1.30 1.00 0.80 SEE DETAIL A 1.10 0.80 0.10 C 0.10 0.00 C 2.10±0.30 SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED GAGE PLANE (R0.10) 0.25 0.10 0.20 A) THIS PACKAGE CONFORMS TO EIAJ SC-88, 1996. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. D) DRAWING FILENAME: MKT-MAA06AREV6 30° 0° 0.46 0.26 DETAIL A SCALE: 60X Figure 8. 6-Lead, SC70, EIAJ SC-88a, 1.25mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specification Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/analog/pdf/sc70-6_tr.pdf. Package Designator P6X © 1999 Fairchild Semiconductor Corporation NC7WZ17 • Rev. 1.0.6 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 6 NC7WZ17 — TinyLogic® UHS Dual Buffer with Schmitt Trigger Inputs Physical Dimensions 2X 0.05 C 1.45 B 2X (1) 0.05 C (0.254) (0.49) 5X 1.00 (0.75) PIN 1 IDENTIFIER 5 (0.52) 1X A TOP VIEW 0.55MAX (0.30) 6X PIN 1 0.05 C 0.05 0.00 RECOMMENED LAND PATTERN 0.05 C C 0.25 0.15 6X 1.0 DETAIL A 0.10 0.05 0.45 0.35 0.10 0.00 6X C B A C 0.40 0.30 0.35 5X 0.25 0.40 5X 0.30 0.5 (0.05) 6X DETAIL A PIN 1 TERMINAL 0.075 X 45 CHAMFER (0.13) 4X BOTTOM VIEW Notes: 1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y14.5M-1994 4. FILENAME AND REVISION: MAC06AREV4 5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY OTHER LINE IN THE MARK CODE LAYOUT. Figure 9. 6-Lead, MicroPak™, 1.0mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specification Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf. Package Designator L6X © 1999 Fairchild Semiconductor Corporation NC7WZ17 • Rev. 1.0.6 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 7 NC7WZ17 — TinyLogic® UHS Dual Buffer with Schmitt Trigger Inputs Physical Dimensions 0.89 0.35 0.05 C 1.00 2X B A 5X 0.40 PIN 1 MIN 250uM 0.66 1.00 1X 0.45 6X 0.19 0.05 C TOP VIEW RECOMMENDED LAND PATTERN FOR SPACE CONSTRAINED PCB 2X 0.90 0.05 C 0.35 0.55MAX C 5X 0.52 SIDE VIEW 0.73 (0.08) 4X 1 DETAIL A 2 1X 0.57 0.09 0.19 6X 3 0.20 6X ALTERNATIVE LAND PATTERN FOR UNIVERSAL APPLICATION (0.05) 6X 5X 0.35 0.25 6 5 4 0.35 0.60 (0.08) 4X 0.10 .05 C C B A 0.40 0.30 BOTTOM VIEW NOTES: A. COMPLIES TO JEDEC MO-252 STANDARD B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. LANDPATTERN RECOMMENDATION IS BASED ON FSC DESIGN. E. DRAWING FILENAME AND REVISION: MGF06AREV3 0.075X45° CHAMFER DETAIL A PIN 1 LEAD SCALE: 2X Figure 10. 6-Lead, MicroPak2, 1x1mm Body, .35mm Pitch Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specification Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf. Package Designator FHX © 1999 Fairchild Semiconductor Corporation NC7WZ17 • Rev. 1.0.6 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 8 NC7WZ17 — TinyLogic® UHS Dual Buffer with Schmitt Trigger Inputs © 1999 Fairchild Semiconductor Corporation NC7WZ17 • Rev. 1.0.6 www.fairchildsemi.com 9