www.fairchildsemi.com AN-9731 LED Application Design Guide Using BCM Power Factor Correction (PFC) Controller for 100W Lighting System 1. Introduction This application note presents practical step-by-step design considerations for a Boundary-Conduction-Mode (BCM) Power-Factor-Correction (PFC) converter employing Fairchild PFC controller, FL7930. It includes designing the inductor and Zero-Current-Detection (ZCD) circuit, selecting the components, and closing the control loop. The design procedure is verified through an experimental 140W prototype converter. Unlike the Continuous Conduction Mode (CCM) technique often used at this power level, BCM offers inherent zero-current switching of the boost diodes (no reverse-recovery losses), which permits the use of lessexpensive diodes without sacrificing efficiency. The FL3930B provides an additional OVP pin that can be used to shut down the boost power stage when output voltage exceeds the OVP level due to damaged resistors connected at the INV pin. The FL7930C provides a PFCready pin can be used to trigger other power stages when PFC output voltage reaches the proper level (with hysteresis). This signal can be used as the VCC trigger signal for another power stage controller after PFC stage or be transferred to the secondary side to synchronize the operation with PFC voltage condition. This simplifies the external circuit around the PFC controller and saves BOM cost. The internal proprietary logic for detecting input voltage improves the stability of PFC operation. Together with the maximum switching frequency clamping at 300kHz, FL7930 can limit inductor current to within predesigned ranges at one or two cycles of the AC-inputabsent test to simulate a sudden blackout. Due to the startup-without-overshoot design, audible noise from repetitive OVP triggering is eliminated. Protection functions include output over-voltage, over-current, openfeedback, and under-voltage lockout. An Excel®-based design tool is available with this application note and the design result is shown with the calculation results as an example. Figure 1. Typical Application Circuit © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 www.fairchildsemi.com AN-9731 2. Operation Principle of BCM Boost PFC Converter The most widely used operation modes for the boost converter are Continuous Conduction Mode (CCM) and Boundary Conduction Mode (BCM). These two descriptive names refer to the current flowing through the energy storage inductor of the boost converter, as depicted in Figure 2. As the names indicate, the inductor current in CCM is continuous; while in BCM, the new switching period is initiated when the inductor current returns to zero, which is at the boundary of continuous conduction and discontinuous conduction operations. Even though the BCM operation has higher RMS current in the inductor and switching devices, it allows better switching condition for the MOSFET and the diode. As shown in Figure 2, the diode reverse recovery is eliminated and a fast-recovery diode is not needed. The MOSFET is also turned on with zero current, which reduces the switching loss. A by-product of BCM is that the boost converter runs with variable switching frequency that depends primarily on the selected output voltage, the instantaneous value of the input voltage, the boost inductor value, and the output power delivered to the load. The operating frequency changes as the input current follows the sinusoidal input voltage waveform, as shown in Figure 3. The lowest frequency occurs at the peak of sinusoidal line voltage. Figure 3. Operation Waveforms of BCM PFC The voltage-second balance equation for the inductor is: VIN ( t ) ⋅ t ON = (VOUT − VIN ( t )) ⋅ t OFF (1) where VIN(t) is the rectified line voltage and VOUT is the output voltage. The switching frequency of BCM boost PFC converter is: fSW = = 1 1 VOUT − VIN ( t ) = ⋅ tON + tOFF tON VOUT 1 tON ⋅ VOUT − VIN ,PK ⋅ sin (2π ⋅ fLINE ⋅ t ) (2) VOUT Figure 2. CCM vs. BCM Control The fundamental idea of BCM PFC is that the inductor current starts from zero in each switching period, as shown in Figure 3. When the power transistor of the boost converter is turned on for a fixed time, the peak inductor current is proportional to the input voltage. Since the current waveform is triangular; the average value in each switching period is proportional to the input voltage. In a sinusoidal input voltage, the input current of the converter follows the input voltage waveform with very high accuracy and draws a sinusoidal input current from the source. This behavior makes the boost converter in BCM operation an ideal candidate for power factor correction. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 where VIN,PK is the amplitude of the line voltage and fLINE is the line frequency. Figure 4 shows how the MOSFET on time and switching frequency change as output power decreases. When the load decreases, as shown in the right side of Figure 4, the peak inductor current diminishes with reduced MOSFET on time and, therefore, the switching frequency increases. Since this can cause severe switching losses at light-load condition and too-high switching frequency operation may occur at startup, the maximum switching frequency is limited to 300kHz. www.fairchildsemi.com 2 AN-9731 3. Startup without Overshoot and AC-Absent Detection Figure 4. Frequency Variation of BCM PFC Since the design of the filter and inductor for a BCM PFC converter with variable switching frequency should be at minimum frequency condition, it is worthwhile to examine how the minimum frequency of BCM PFC converter changes with operating conditions. Feedback control speed of the PFC is typically quite slow. Due to the slow response, there is a gap between output voltage and feedback control. That is why Over-Voltage Protection (OVP) is critical at the PFC controller. Voltage dip caused by fast load change from light to heavy is diminished by a large bulk capacitor. OVP is easily triggered at startup. Switching starting and stopping by OVP at startup may cause audible noise and can increase voltage stress at startup, which may be higher than normal operation. This operation is improved when soft-start time is very long. However, too-long startup time raises the time needed for the output voltage to reach the rated value, especially at light load. FL7930 includes a startupwithout-overshoot feature. During startup, the feedback loop is controlled by an internal proportional gain controller and, when output voltage approaches the rated value, changes to the external compensator after an internally fixed transition time described in the Figure 6. In short, an internal proportional gain controller prevents overshoot at startup; an external conventional compensator takes over after startup. Figure 5 shows the minimum switching frequency, which occurs at the peak of line voltage as a function of the RMS line voltage for three output voltage settings. It is interesting that, depending on where the output voltage is set, the minimum switching frequency may occur at the minimum or at the maximum line voltage. When the output voltage is approximately 405V, the minimum switching frequency is the same for both low line (85VAC) and high line (265VAC). Figure 6. Startup Without Overshoot Figure 5. Minimum Switching Frequency vs. RMS Line Voltage (L = 280µH, POUT = 140W) © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 FL7930 eliminates AC input voltage detection to save the power loss caused by an input-voltage-sensing resistor array and to optimize THD. Therefore, no information about input voltage is available at the internal controller. In many cases, the VCC of PFC controller is supplied by an independent power source, like standby power. When the electric power is suddenly interrupted during one or two AC line periods, VCC is still alive during that time and PFC output voltage drops. Accordingly, the control loop tries to compensate output voltage drop and control voltage reaches its maximum. When AC line input voltage is live, control voltage allows high switching current and creates stress on the MOSFET and diode. To protect against this, FL7930 checks if the input AC voltage exists. Once the controller verifies that the input voltage does not exist, soft-start is reset and waits until AC input voltage is applied again. Soft-start manages the turn-on time for smooth, operation after detecting that the AC voltage is live and results in less voltage and current stress during startup. www.fairchildsemi.com 3 AN-9731 Figure 7. AC-Off Operation without AC-Absent Detection Circuit Figure 8. AC-Off Operation with AC-Absent Detection Circuit 4. Design Considerations In this section, a design procedure is presented using the schematic in Figure 9 as a reference. A 140W PFC application with universal input range is selected as a design example. The design specifications are: Line Voltage Range: 90~265VAC (Universal Input), 50Hz Nominal Output Voltage and Current: 400V/0.35A Hold-up Time Requirement: Output Voltage Should Not Drop Below 330V During One Line Cycle Output Voltage Ripple: Less than 8VPP Minimum Switching Frequency: Higher than 50kHz Control Bandwidth: 5~15Hz VCC Supplied from Auxiliary Power Supply. (140W) Figure 9. Reference Circuit for Design Example of BCM Boost PFC © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 www.fairchildsemi.com 4 AN-9731 [STEP-1] Define System Specifications Line Frequency Range (VLINE,MIN and VLINE,MAX) Line Frequency (fLINE) Output Voltage (VOUT) Output Load Current (IOUT) Output Power (POUT =VOUT × IOUT) Estimated Efficiency (η) (Design Example) Input voltage range is universal input, output load is 350mA, and estimated efficiency is selected as 0.9. VLINE ,MIN = 90VAC , VLINE ,MAX = 265VAC f LINE = 50 Hz VOUT = 400V , I OUT = 350 mA To calculate the maximum input power, it is necessary to estimate the power conversion efficiency. At universal input range, efficiency is recommended at 0.9; 0.93~0.95 is recommended when input voltage is high. η = 0 .9 When input voltage is set at the minimum, input current becomes the maximum to deliver the same power compared at high line. Maximum boost inductor current can be detected at the minimum line voltage and at its peak. Inductor current can be divided into two categories; rising current when MOSFET is on and output diode current when MOSFET is off, as shown in Figure 10. I IN ,MAX = I L, PK = 4 ⋅ POUT η ⋅ 2 ⋅ VLINE ,MIN I L,PK I IN ,MAXRMS = 4 ⋅ 400V ⋅ 0.35 A 0.9 ⋅ 2 ⋅ 90 = 4.889 A 4.889 A = 2.444 A 2 I IN ,MAX 2.444 A = = = 1.728 A 2 2 2 = Figure 10. Inductor and Input Current Because switching frequency is much higher than line frequency, input current can be assumed to be constant during a switching period, as shown in Figure 11. [STEP-2] Boost Inductor Design The boost inductor value is determined by the output power and the minimum switching frequency. The minimum switching frequency must be higher than the maximum audible frequency band of 20kHz. Minimum frequency near 20kHz can decrease switching loss with the cost of increased inductor size and line filter size. Toohigh minimum frequency may increase the switching loss and make the system respond to noise. Selecting in the range of about 30~60kHz is a common choice; 40~50kHz is recommended with FL7930. Figure 11. Inductor and Input Current With the estimated efficiency, Figure 10 and Figure 11 inductor current peak (IL,PK), maximum input current (IIN,MAX), and input RMS (Root Mean Square) current (IIN,MAXRMS) are given as: I L , PK = 4 ⋅ POUT η ⋅ 2 ⋅ V LINE ,MIN [ A] (3) The minimum switching frequency may appear at minimum input voltage or maximum input voltage, depending on the output voltage level. When PFC output voltage is less than 405V, minimum switching appears at the maximum input voltage, according to Fairchild application note AN-6086. The inductance is obtained using the minimum switching frequency: L= IIN,MAX = IL,PK / 2 [ A ] (4) IIN ,MAXRMS = IIN ,MAX / 2 [ A ] (5) © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 η⋅ ( 2V ) 4 ⋅ fSW ,MIN ⋅ POUT 2 LINE ⎛ 2VLINE ⋅ ⎜1 + ⎜ VOUT − 2VLINE ⎝ ⎞ ⎟ ⎟ ⎠ [H] (6) where L is boost inductance and fSW,MIN is the minimum switching frequency. www.fairchildsemi.com 5 AN-9731 The maximum on time needed to carry peak inductor current is calculated as: IL,PK tON,MAX = L ⋅ 2 ⋅ VLINE,MIN [s] (7) Once inductance and the maximum inductor current are calculated, the number of turns of the boost inductor should be determined considering the core saturation. The minimum number of turns is given as: N BOOST ≥ I L ,PK ⋅ L [ μH ] Ae [ mm 2 ] ⋅ ΔB Figure 13. Ae and AW [ Turns ] (8) where Ae is the cross-sectional area of core and ΔB is the maximum flux swing of the core in Tesla. ΔB should be set below the saturation flux density. (Design Example) Since the output voltage is 400V, the minimum frequency occurs at high-line (265VAC) and full-load condition. Assuming the efficiency is 90% and selecting the minimum frequency as 50kHz, the inductor value is obtained as: Figure 12 shows the typical B-H characteristics of ferrite core from TDK (PC45). Since the saturation flux density (ΔB) decreases as the temperature increases, the high temperature characteristics should be considered. L= = RMS inductor current (IL,RMS) and current density of the coil (IL,DENSITY) can be given as: I L ,RMS = I L ,PK I L ,DENSITY = (9) [ A] 6 I L ,RMS 2 π ⋅ ⎛⎜ d wire 2 ⎞⎟ ⋅ Nwire ⎝ [ A / mm 2 ] where dWIRE is the diameter of winding wire and NWIRE is the number of strands of winding wire. When selecting wire diameter and strands; current density, window area (AW, refer to Figure 13) of selected core, and fill factor need to be considered. The winding sequence of the boost inductor is relatively simple compared to a DC-DC converter, so fill factor can be assumed about 0.2~0.3. ) 2 ⎛ 2VLINE 4 ⋅ f SW ,MIN ⋅ POUT ⋅ ⎜1 + ⎜ V OUT − 2VLINE ⎝ 0.9 ⋅ ( 2 × 265) ⎞ ⎟ ⎟ ⎠ 2 ⎛ 2 ⋅ 265 ⎞⎟ 4 ⋅ 50 ⋅10 ⋅140 ⋅ ⎜1 + ⎜ 400 − 2 ⋅ 265 ⎟ ⎝ ⎠ = 284.4[ μH ] 3 Assuming EER3019N core (PL-7, Ae=137mm2) is used and setting ΔB as 0.3T, the primary winding should be: N BOOST ≥ (10) ⎠ ( η ⋅ 2VLINE I L ,PK ⋅ L[ μH ] Ae [ mm 2 ] ⋅ ΔB = 6.984 ⋅ 284 = 34[T ] 137 ⋅ 0.3 The number of turns (NBOOST) of the boost inductor is determined as 34 turns. When 0.10mm diameter and 50-strand wire is used, RMS current of inductor coil and current density are: I L ,RMS = I L,DENSITY= I L ,PK 6 4.889 = 2[ A] 6 I L,RMS 2 π ⋅ ⎛⎜dwire2 ⎞⎟ ⋅ Nwire ⎝ Layers cause the skin effect and proximity effect in the coil, so real current density may be higher than expected. = = 2 π ⋅ (0.1/ 2) ⋅ 50 2 = 5.1 [A/ mm2 ] ⎠ Figure 12. Typical B-H Curves of Ferrite Core © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 www.fairchildsemi.com 6 AN-9731 [STEP-3] Inductor Auxiliary Winding Design Figure 14 shows the application circuit of nearby ZCD pin from auxiliary winding. Auxiliary winding must give enough energy to trigger ZCD threshold to detect zero current. Minimum auxiliary winding turns are given as: NAUX ≥ 1.5V ⋅ NBOOST VOUT − 2VLINE,MAX [ Turns] (11) where 1.5V is the positive threshold of the ZCD pin. To guarantee stable operation, auxiliary winding turns are recommended to add 2~3 turns to the calculation result from Equation (11). However, too many auxiliary winding turns raise the negative clamping loss at high line and positive clamping loss at low line. (Design Example) 34 turns are selected as boost inductor turns and auxiliary winding turns are calculated as: NAUX ≥ Figure 14. Application Circuit of ZCD Pin The first role of ZCD winding is detecting the zerocurrent point of the boost inductor. Once the boost inductor current becomes zero, the effective capacitor shown at the MOSFET drain pin (Ceff) and the boost inductor resonate together. To minimize the constant turnon time deterioration and turn-on loss, the gate is turned on again when the drain-source voltage of the MOSFET (VDS) reaches the valley point shown in Figure 15. When input voltage is lower than half of the boosted output voltage, Zero Voltage Switching (ZVS) is possible if MOSFET turn-on is triggered at valley point. 1.5V ⋅ NBOOST VOUT − 2VLINE,MAX = 1.5 ⋅ 34 400 − 2 ⋅ 265 = 2.02[ Turns] Choice should be around 4~5 turns after adding 2~3 turns. [STEP-4] ZCD Circuit Design If a transition time when VAUXILIARY drops from 1.4V to 0V is ignored from Figure 15, the needed additional delay by the external resistor and capacitor is one quarter of the resonant period. The time constant made by ZCD resistor and capacitor should be the same as one quarter of the resonant period: 2π Ceff ⋅ L (12) RZCD ⋅ CZCD = 4 where Ceff is the effective capacitor shown at the MOSFET drain pin; CZCD is the external capacitance at the ZCD pin; and RZCD is the external resistance at the ZCD pin. The second role of RZCD is the current limit of the internal negative clamp circuit when auxiliary voltage drops to negative due to MOSFET turn on. ZCD voltage is clamped 0.65V and minimum RZCD can be given as: RZCD ⎛ N AUX ⎞ ⎜ 2VLINE,MAX − 0.65V ⎟⎟ ⎜N BOOST ⎠ [Ω] ≥⎝ 3mA (13) where 3mA is the clamping capability of the ZCD pin. Figure 15. ZCD Detection Waveforms © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 The calculated result of Equation (13) is normally higher than 15kΩ. If 20kΩ is assumed as RZCD, calculated CZCD from Equation (12) is around 10pF when the other components are assumed as conventional values used in the field. Because most IC pins have several pF parasitic capacitance, CZCD can be eliminated when RZCD is higher than 30kΩ. However, a small capacitor would be helpful when auxiliary winding suffers from operating noise. www.fairchildsemi.com 7 AN-9731 The PFC control loop has two conflicting goals: output voltage regulation and making the input current shape the same as input voltage. If the control loop reacts to regulate output voltage smoothly, as shown in Figure 16, control voltage varies widely with the input voltage variation. Input current acts to the control loop and sinusoidal input current shape cannot be attained. This is why control response of most PFC topologies is very slow and turn-on time over AC period is kept constant. This is also why output voltage ripple is made by input and output power relationship, not by control-loop performance. Figure 17. Inductor Current at AC Voltage Peak Figure 16. Input Current Deterioration by Fast Control If on-time is controlled constantly over one AC period, inductor current peak follows the AC input voltage shape and achieves good power factor. Off-time is basically inductor current reset time due to the boundary mode and is determined by the input and output voltage difference. When input voltage is at its peak, the voltage difference between input and output voltage is small and long turnoff time is necessary. When input voltage is near zero, turn-off time is short, as shown in Figure 17 and Figure 18. Though inductor current drops to zero, there is a minor delay, explained above. The delay can be assumed as fixed when AC is at line peak and zero. Near AC line peak, the inductor current decreasing slope is slow and inductor current slope is also slow during the ZCD delay. The amount of negative current is not much higher than the inductor current peak. Near the AC line zero, inductor current decreasing slope is very high and the amount of negative current is higher than positive inductor current peak because input voltage is almost zero. Figure 18. Inductor Current at AC Voltage Zero Negative inductor current creates zero-current distortion and degrades the power factor. Improve this by extending turn-on time at the AC line input near the zero cross. Negative auxiliary winding voltage, when MOSFET is turned on, is linearly proportional to the input voltage. Sourcing current generated by the internal negative clamping circuit is also proportional to sinusoidal input voltage. That current is detected internally and added to the internal sawtooth generator, as shown in Figure 19. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 www.fairchildsemi.com 8 AN-9731 Figure 19. ZCD Current and Sawtooth Generator When AC input voltage is almost zero, no negative current is generated from inside; but sourcing current, when input voltage is high, is used to raise the sawtooth generator slope and turn-on time is shorter. As a result, turn-on time, when AC voltage is zero, is longer compared to AC voltage, in peaks shown as in Figure 20. Figure 20. THD Improvement Figure 22. Internal Sawtooth Wave Slope Variation RZCD also influences control range. Because FL7930 doesn’t detect input voltage, voltage-mode control value is determined by the turn-on time to deliver needed current to boost output voltage. When input voltage increases, control voltage decreases rapidly. For example, if input voltage doubles, control voltage drops to one quarter. Making control voltage maximum when input voltage is low and at full load is necessary to use the whole control range for the rest of the input voltage conditions. Matching maximum turn-on time needed at low line is calculated in Equation (7) and turn-on time adjustment by RZCD guarantees use of the full control range. RZCD for control range optimization is obtained as: The current that comes from the ZCD pin, when auxiliary voltage is negative, depends on RZCD. The second role of RZCD is related to improving the Total Harmonic Distortion (THD). R ZCD ≥ 2 ⋅ VLINE ,MIN ⋅ N AUX 28 μs ⋅ t ON ,MAX 1 − t ON ,MAX 0.469 mA ⋅ N BOOST (14) where: tON,MAX is calculated by Equation (7); tON,MAX1 is maximum on-time programming 1; NBOOST is the winding turns of boost inductor; and NAUX is the auxiliary winding turns. The third role of RZCD is making the maximum turn-on time adjustment. Depending on sourcing current from the ZCD pin, the maximum on-time varies as in Figure 21. RZCD calculated by Equation (13) is normally lower than the value calculated in Equation (14). To guarantee the needed turn on-time for the boost inductor to deliver rated power, the resulting RZCD from Equation (13) is normally not suitable. RZCD should be higher than the result of Equation (14) when output voltage drops as a result of low line voltage. Figure 21. Maximum On-Time Variation vs. IZCD With the aid of IZCD, an internal sawtooth generator slope is changed and turn-on time varies as shown in Figure 22. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 When input voltage is high and load is light, not much input current is needed and control voltage of VCOMP touches switching stop level, such as if FL7930 is 1V. However, in some applications, a PFC block is needed to operate normally at light load. To compensate control www.fairchildsemi.com 9 AN-9731 range correctly, input voltage sensing is necessary, such as with Fairchild’s interleaved PFC controller FAN9612, or special care on sawtooth generator is necessary. Without it, optimizing RZCD is only slightly helpful for control range. This is explained and depicted in the associated Excel® design tool “COMP Range” worksheet. To guarantee enough control range at high line, clamping output voltage lower than rated output on the minimum input condition can help. COUT ≥ 2 ⋅ POUT ⋅ tHOLD (VOUT − 0.5 ⋅ ΔVOUT,RIPPLE)2 −VOUT,MIN2 [f ] (16) where tHOLD is the required hold-up time and VOUT,MIN is the minimum output voltage during hold-up time. (Design Example) Minimum RZCD for clamping capability is calculated as: ⎞ ⎛ NAUX ⎜ 2VLINE,MAX − 0.65V ⎟⎟ ⎜N ⎠ ⎝ BOOST RZCD ≥ 3mA ⎞ ⎛5 2 ⋅ 265 − 0.65V ⎟ ⎜ ⎠ ⎝ 34 = 18.2kΩ = 3mA Minimum RZCD for control range is calculated as: RZCD ≥ = 2 ⋅ VLINE ,MIN ⋅ N AUX 28 μs ⋅ tON ,MAX1 − tON ,MAX 0.469 mA ⋅ NBOOST 28 μs 2 ⋅ 90 ⋅ 5 ⋅ = 37.2 kΩ 42 μs − 10.9μs 0.469 mA ⋅ 34 A choice close to the value calculated by the control range is recommended. 39kΩ is chosen in this case. Figure 23. Output Voltage Ripple The voltage rating of capacitor can be obtained as: VST ,COUT = VOVP ,MAX ⋅ VOUT [ V ] VREF (17) where VOVP,MAX and VREF are the maximum tolerance specifications of over-voltage protection triggering voltage and reference voltage at error amplifier. [STEP-5] Output Capacitor Selection (Design Example) With the ripple specification of 8Vpp, the capacitor should be: The output voltage ripple should be considered when selecting the output capacitor. Figure 23 shows the line frequency ripple on the output voltage. With a given specification of output ripple, the condition for the output capacitor is obtained as: COUT ≥ IOUT [F] 2π ⋅ fLINE ⋅ ΔVOUT,RIPPLE CO ≥ I OUT 0.35 = = 139.3[μF ] 2π ⋅ f LINE ⋅ ΔVOUT,ripple 2π ⋅ 50 ⋅ 8 Since minimum allowable output voltage during one cycle line (20ms) drop-outs is 330V, the capacitor should be: (15) CO ≥ where VOUT,RIPPLE is the peak-to-peak output voltage ripple specification. = 2 × POUT ⋅ t HOLD (VOUT − 0.5 ⋅ ΔVOUT , ripple )2 − VOUT , MIN 2 2 ⋅140 ⋅ 20 ×10− 3 = 116.9[ μF ] The output voltage ripple caused by ESR of electrolytic capacitor is not as serious as other power converters because output voltage is high and load current is small. Since too much ripple on the output voltage may cause premature OVP during normal operation, the peak-to-peak ripple specification should be smaller than 15% of the nominal output voltage. To meet both conditions, the output capacitor must be larger than 140μF. A 240μF capacitor is selected for the output capacitor. The hold-up time should also be considered when determining the output capacitor as: VST ,COUT = © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 (400 − 0.5 ⋅ 8)2 − 3302 The voltage stress of selected capacitor is calculated as: VOVP,MAX 2.730 ⋅ 400 = 436.8[ V ] ⋅VOUT = 2.500 VREF www.fairchildsemi.com 10 AN-9731 The precise turn-off loss calculation is difficult because of the nonlinear characteristics of MOSFET turn off. When piecewise linear current and voltage of MOSFET during turn-off and inductive load are assumed, MOSFET turnoff loss is obtained as: PQ,SWOFF = 1 ⋅VOUT ⋅ I L ⋅ tOFF ⋅ fSW [ W ] 2 (21) where tOFF is the turn-off time and fSW is the switching frequency. Boundary Mode PFC inductor current and switching frequency vary at every switching moment. RMS inductor current and average switching frequency over one AC period can be used instead of instantaneous values. [STEP-6] MOSFET and Diode Selection Selecting the MOSFET and diode needs extensive knowledge and calculation regarding loss mechanisms and gets more complicated if proper selection of a heatsink is added. Sometimes the loss calculation itself is based on assumptions that may be far from reality. Refer to industry resources regarding these topics. This note shows the voltage rating and switching loss calculations based on the linear approximation. The voltage stress of the MOSFET is obtained as: VST ,Q = VOVP ,MAX ⋅ VOUT + VDROP,DOUT [ V ] VREF (18) where VDROP,DOUT is the maximum forward-voltage drop of output diode. After the MOSFET is turned off, the output diode turns on and a large output electrolytic capacitor is shown at the drain pin. Thus a drain voltage clamping circuit that is necessary on other topologies is not necessary in PFC. During the turn-off transient, boost inductor current changes the path from MOSFET to output diode and before the output diode turns on; a minor voltage peak can be shown at drain pin, which is proportional to MOSFET turn-off speed. MOSFET loss can be divided into three parts: conduction loss, turn-off loss, and discharge loss. Boundary Mode guarantees Zero Current Switching (ZCS) of MOSFET when turned on, so turn-on loss is negligible. The MOSFET RMS current and conduction loss are obtained as: IQ,RMS = IL,PK ⋅ 1 4 2 ⋅VLINE [ A] − 6 9π ⋅VOUT PQ,CON = (IQ,RMS )2 ⋅ RDS,ON [ W ] (19) Individual loss portions are changed according to the input voltage; maximum conduction loss appears at low line because of high input current; and maximum switching off loss appears at high line because of the high switching frequency. Thus, resulting loss is always lower than the summation of the two losses calculated above. Capacitive discharge loss made by effective capacitance shown at drain and source, which includes MOSFET COSS (an externally added capacitor to reduce dv/dt and parasitic capacitors shown at drain pin) is also dissipated at MOSFET. That loss is calculated as: PQ,DISCHG= 1 2 (COSS + CEXT + CPAR) ⋅VOUT ⋅ fSW [ W ] 2 (22) where: COSS is the output capacitance of MOSFET; CEXT is an externally added capacitor at drain and source of MOSFET; and CPAR is the parasitic capacitance shown at drain pin. Because the COSS is a function of the drain and source voltage, it is necessary to refer to graph data showing the relationship between COSS and voltage. Estimate the total power dissipation of MOSFET as the sum of three losses: PQ = PQ,CON + PQ,SWOFF + PQ,DISCHG [ W ] (23) Diode voltage stress is the same as the output capacitor stress calculated in Equation (17). The average diode current and power loss are obtained as: I DOUT,AVE = IOUT η [ A] PDOUT = VDROP,DOUT ⋅ I DOUT,AVE [ W ] (20) (24) (25) where VDROP,DOUT is the forward voltage drop of diode. where IQ,RMS is the RMS value of MOSFET current, PQ,CON is the conduction loss caused by MOSFET current, and RDS,ON is the on resistance of the MOSFET. On resistance, described as “static on resistance,” varies with junction temperature. That variation information is normally supplied in the datasheet by manufacturer. When calculating conduction loss, generally multiply three with the RDS,ON for more accurate estimation. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 www.fairchildsemi.com 11 AN-9731 (Design Example) Internal reference at the feedback pin is 2.5V and maximum tolerance of OVP trigger voltage is 2.73V. If Fairchild’s FDPF12N60NZ MOSFET and FFPF08H60S diode are selected, VD,FOR is 2.1V at 8A, 25oC, maximum RDS,ON is 0.53Ω at drain current 6A, and maximum COSS is 150pF at drain-source voltage 480V. VST,Q = Once resistance is calculated, its power loss at low line is calculated as: PRCS = IQ2 ,RMS ⋅ RCS [ W ] Power rating of the sensing resistor is recommended a twice the power rating calculated in Equation (27). VOVP,MAX ⋅VOUT + VDROP,DIODE VREF (Design Example) Maximum inductor current is 4.889A and sensing resistor is calculated as: 2.73 = ⋅ 400 + 2.1 = 438.9 [V ] 2.50 ⎛ 1 4 2 ⋅ VLINE PQ,CON = ⎜ I L,PK ⋅ − ⎜ 6 9π ⋅ VOUT ⎝ ⎛ 1 4 2 ⋅ 90 = ⎜ 4.889⋅ − ⎜ 6 9π ⋅ 400 ⎝ PQ,SWOFF = = (27) RCS = 2 ⎞ ⎟ ⋅ (R DS,ON ) ⎟ ⎠ VCS , LIM pk I ind ⋅ 1 .1 = 0 .8 = 0 .149[ Ω ] 4.889 ⋅ 1.1 Choosing 0.1Ω as RCS, power loss is calculated as: PRCS,LOSS = I Q2 ,RMS ⋅ RCS = 1.7052 ⋅ 0.1 = 0.29[W ] 2 ⎞ ⎟ ⋅ (0.53× 3) = 4.62[W ] ⎟ ⎠ Recommended power rating of sensing resistor is 0.58W. 1 ⋅ VOUT ⋅ I L ⋅ tOFF ⋅ f SW 2 1 ⋅ 400 ⋅ 1.782 ⋅ 50ns ⋅ (50k / 0.8) =1.08[W ] 2 1 2 PQ,DISCHG = ⋅ (COSS + CEXT + CPAR) ⋅ VOUT ⋅ f SW 2 1 = ⋅150p ⋅ 4002 ⋅ (50k / 0.8) = 0.75 [W ] 2 [STEP-9] Design Compensation Network Diode average current and forward-voltage drop loss as: I DOUT, AVE = I OUT η = 0.35 = 0.39[ A] 0.9 The boost PFC power stage can be modeled as shown in Figure 24. MOSFET and diode can be changed to lossfree resistor model and then be modeled as a voltagecontrolled current source supplying RC network. PDOUT,LOSS = VDOUT,FOR ⋅ I DOUT, AVE = 2.1 ⋅ 0.39 = 1.02[W ] [STEP-8] Determine Current-Sense Resistor It is typical to set pulse-by-pulse current limit level a little higher than the maximum inductor current calculated by Equation (3). For 10% margin, the current-sensing resistor is selected as: RCS = VCS,LIM I L,PK ⋅1.1 [Ω] © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 Figure 24. Small Signal Modeling of the Power Stage (26) www.fairchildsemi.com 12 AN-9731 By averaging the diode current during the half line cycle, the low-frequency behavior of the voltage controlled current source of Figure 24 is obtained as: I DOUT,AVE = KSAW ⋅ 2VLINE 2VLINE ⋅ [ A] 4VOUT L (28) Proportional and Integration (PI) control with a highfrequency pole is typically used for compensation, as shown in Figure 27. The compensation zero (fCZ) introduces phase boost, while the high-frequency compensation pole (fCP) attenuates the switching ripple. The transfer function of the compensation network is obtained as: where: L is the boost inductance, VOUT is the output voltage; and KSAW is the internal gain of sawtooth generator (that of FL7930 is 8.496×10-6). ∧ v COMP ∧ v OUT Then the low-frequency, small-signal, control-to-output transfer function is obtained as: ∧ v OUT ∧ v COMP = KSAW (V )2 RL ⋅ ⋅ LINE 4VOUT ⋅ L 2π fI = ⋅ s fI = 1 1+ s (29) where fCZ 2π f p 2 where f p = and RL is the output load 2π ⋅ RLCOUT resistance in a given load condition. Figure 25 and Figure 26 show the variation of the controlto-output transfer function for different input voltages and different loads. Since DC gain and crossover frequency increase as input voltage increases and DC gain increases as load decreases, high input voltage and light load is the worst condition for feedback loop design. s 2π fCZ s 1+ 2π fCP 1+ 2.5 115μmho ⋅ VOUT 2π ⋅ CCOMP, LF + CCOMP, HF ( ) (30) 1 = 2π ⋅ RCOMP ⋅ CCOMP, LF 1 ⎛ CCOMP, LF ⋅ CCOMP, HF ⎞ ⎟ 2π ⋅ RCOMP ⋅ ⎜ ⎜ CCOMP, LF + CCOMP, HF ⎟ ⎠ ⎝ If CCOMP,LF is much larger than CCOMP,HF, fI and fCP can be simplified as: fCP = fI ≅ 2.5 115μmho [ Hz] ⋅ VOUT 2π ⋅ CCOMP, LF fCP ≅ (31) 1 [ Hz] 2π ⋅ RCOMP ⋅ CCOMP, HF GM = 115 μ mho Figure 25. Control-to-Output Transfer Function for Different Input Voltages Gain fSW 0dB 1 fCZ = 2 RCOMP CCOMP,LF Frequency 1 2 RCOMP CCOMP,HF//CCOMP,HF 1 = 2 RCOMP CCOMP,HF fCP = Figure 27. Compensation Network Figure 26. Control-to-Output Transfer Function for Different Loads The feedback resistor is chosen to scale down the output voltage to meet the internal reference voltage: RFB1 ⋅ VOUT = 2.5V RFB1 + RFB2 © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 (32) www.fairchildsemi.com 13 AN-9731 Typically, high RFB1 is used to reduce power consumption and, at the same time, CFB can be added to raise the noise immunity. The maximum CFB currently used is several nano farads. Adding a capacitor at the feedback loop introduces a pole as: fFP = ≅ 1 2π ⋅ (RFB1 // RFB2 ) ⋅ CFB 1 2π ⋅ RFB2 ⋅ CFB where (33) [ Hz] (R FB1 // R FB 2 ) = R FB1 ⋅ R FB 2 R FB 1 + R FB 2 Though RFB1 is high, pole frequency made by the synthesized total resistance and several nano farads is several kilo hertz and rarely affects control-loop response. Figure 28. Compensation Network Design The procedure to design the feedback loop is: a. D etermine the crossover frequency (fC) around 1/10~1/5 of line frequency. Since the control-tooutput transfer function of the power stage has -20dB/dec slope and -90o phase at the crossover frequency, as shown in Figure 28; place the zero of the compensation network (fCZ) around the crossover frequency so 45° phase margin is obtained. The capacitor CCOMP,LF is determined as: CCOMP, LF ≅ KSAW (VLINE )2 2.5 ⋅115μ mho 2 ⋅VOUT2 ⋅ L ⋅ COUT (2π fC )2 [f ] (34) To place the compensation zero at the crossover frequency, the compensation resistor is obtained as: RCOMP = b. 1 [Ω] 2π ⋅ fC ⋅ CCOMP,LF (35) P lace this compensator high-frequency pole (fCP) at least a decade higher than fC to ensure that it does not interfere with the phase margin of the voltage regulation loop at its crossover frequency. It should also be sufficiently lower than the switching frequency of the converter for noise to be effectively attenuated. The capacitor CCOMP,HF is determined as: CCOMP,HF = 1 [Ω] 2π ⋅ fCP ⋅ RCOMP © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 (36) www.fairchildsemi.com 14 AN-9731 (Design Example) If RFB1 is 11.7MΩ, then RFB2 is: 2.5V 2.5 RFB2 = RFB1 = 11.7 ×106 = 73.58kΩ VOUT − 2.5V 400 − 2.5 Choosing the crossover frequency (control bandwidth) at 15Hz, CCOMP,LF is obtained as: K SAW (VLINE ) 2.5 ⋅ 115 μ mho 2 CCOMP , LF ≅ = 2 ⋅ VOUT ⋅ L ⋅ COUT (2π f C ) 2 2 8.496 × 10 −6 (230 ) 2.5 ⋅ 115 × 10 −6 2 2 ⋅ 400 2 ⋅ 280 × 10 −6 ⋅ 240 × 10 −6 (2π 15 ) 2 = 665 nF [STEP-10] Line Filter Capacitor Selection It is typical to use small bypass capacitors across the bridge rectifier output stage to filter the switching current ripple, as shown in Figure 29. Since the impedance of the line filter inductor at line frequency is negligible compared to the impedance of the capacitors, the line frequency behavior of the line filter stage can be modeled, as shown in Figure 29. Even though the bypass capacitors absorb switching ripple current, they also generate circulating capacitor current, which leads the line voltage by 90o, as shown in Figure 30. The circulating current through the capacitor is added to the load current and generates displacement between line voltage and current. The displacement angle is given by: Actual CCOMP,LF is determined as 1000nF since it is the closest value among the off-the-shelf capacitors. RCOMP is ⎛ η ⋅ (VLINE )2 ⋅ 2π ⋅ fLINE ⋅ CEQ ⎞ ⎟ obtained as: θ = tan−1 ⎜ (37) ⎜ ⎟ POUT ⎝ ⎠ 1 1 where CEQ is the equivalent capacitance that appears RCOMP = = = 15.95kΩ 2π ⋅ f C ⋅ CCOMP,LF 2π ⋅ 15 ⋅ 665×10−9 across the AC line (CEQ=CF1+CF2+CHF). Selecting the high-frequency pole as 150Hz, CCOMP,HF is The resultant displacement factor is: obtained as: DF = cos(θ ) (38) 1 1 CCOMP,HF = = = 66.5nF Since the displacement factor is related to power factor, 2π ⋅ f CP ⋅ RCOMP 2π ⋅ 150 ⋅ 15.95 × 103 the capacitors in the line filter stage should be selected These components result in a control loop with a bandwidth carefully. With a given minimum displacement factor of 19.7Hz and phase margin of 46°. The actual bandwidth is (DFMIN) at full-load condition, the allowable effective input capacitance is obtained as: a little larger than the asymptotic design. CEA < POUT η ⋅ (VLINE )2 ⋅ 2π ⋅ fLINE ( ) ⋅ tan cos−1 (DFMN ) [ F ] (39) One way to determine if the input capacitor is too high or PFC control routine has problems is to check Power Factor (PF) and Total Harmonic Distortion (THD). PF is the degree to which input energy is effectively transferred to the load by the multiplication of displacement factor. THD is input current shape deterioration ratio. PFC control loop rarely has no relation to displacement factor and input capacitor rarely has no impact on the input current shape. If PF is low (high is preferable), but THD is quite good (low is preferable), it can be concluded that input capacitance is too high and PFC controller is fine. (Design Example) Assuming the minimum displacement factor at full load is 0.98, the equivalent input capacitance is obtained as: CEA < < POUT η ⋅ (VLINE) ⋅ 2π ⋅ f LINE 2 ( ( ) ⋅ tan cos−1(DFMN ) ) 140 ⋅ tan cos−1 (0.96) = 2.0565μF 2 0.9 ⋅ (264) ⋅ 2π ⋅ 50 Thus, the sum of the capacitors on the input side should be smaller than 2.0µF. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 www.fairchildsemi.com 15 AN-9731 θ Figure 29. Equivalent Circuit of Line Filter Stage Figure 30. Line Current Displacement © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 www.fairchildsemi.com 16 AN-9731 Appendix 1: Use of the RDY Pin for FL7930C Typically, boosted output voltage from the PFC block is used as input voltage to the DC-DC conversion block. For some types of DC-DC converter, it is recommended to trigger operation after the input voltage rises to some level. For example, LLC resonant converter or forward converter’s input voltage is limited to some range to enhance performance or guarantee the stable operation. The FL7930C provides a PFC-ready pin that can be used to trigger other power stage when PFC output voltage reaches the proper level. For that purpose, the PFC RDY pin is assigned and can be used as a acknowledge signal for the DC-DC conversion stages. When PFC output voltage rises higher than the internal threshold, PFC RDY output is pulled HIGH by the external pull-up voltage and drops to zero with hysteresis. 2.240V VOUT [V ] 2.500V 1.640V VOUT,RDYL = VOUT [V ] 2.500V VOUT,RDYH = a large electrolytic capacitor is typically used at the VCC supply, that breakdown current flows high for a long time. In this case, the internal MOSFET may be damaged since the external small-signal bipolar junction transistor current capability is higher than the internal RDY MOSFET. Once circuit configuration is settled, voltage after subtracting forward-voltage drop of the diode and voltage drop (by the multiplication of base current and RPULLUP) from the VCC of FL7930C is available for the LLC controller’s VCC source. Another example is using RDY when the secondary side needs PFC voltage information. When a Cold Cathode Fluorescent Lamp (CCFL) is used for the backlight source of an LCD TV, the inverter stage to ignite CCFL can receive PFC output voltage directly. For that application, Figure 32 can be a suitable circuit configuration. (40) where VOUT,RDYH is the VOUT voltage to trigger PFC RDY output to pull HIGH and VOUT,RDYL is the VOUT voltage to trigger PFC ready output to drop to zero. If rated VOUT is 400VDC, then VOUT,RDYH is 358VDC, and VOUT,RDYL is 262VDC. When LLC resonant converter is assumed to connect at the PFC output, the RDY pin can control the VCC for the LLC controller, as shown in Figure 31. Figure 32. RDY Application Circuit Using Opto-Coupler Voltage source from standby block With this application circuit, the minimum RPULLUP is given by Equation (42) and the maximum RPULLUP is limited by sufficient current to guarantee stable operation of the opto-coupler. Assuming 1mA is the typical quantity to drive opto-coupler, the maximum RPULLUP is: VCC 8 RPULLUP RDY PN2222A 2 1N4148 - 2.24V/1.64V VCC for LLC controller RPULLUP ≤ + INV 1mA [Ω] (42) where VOPTO,R is the input forward-voltage drop of the opto-coupler. 1 Figure 31. RDY Application Circuit for VCC Driving RPULLUP is chosen based on the current capability of internal open-drain MOSFET and can be obtained as: RPULLUP ≥ VPULLUP − VOPTO,F VPULLUP − VRDY,SAT I RDY,SK [Ω] (41) It may possible that a secondary microcontroller has authority to give a trigger signal to the CCFL inverter controller; however, after combining the microcontroller signal and RDY signal from the primary-side, the inverter stage is triggered only when the two signals meet the requirements at the same time. where VPULLUP is the pull-up voltage, VRDY,SAT is the saturation voltage of the internal MOSFET, and IRDY,SK is the allowable sink current for the internal MOSFET. A fast diode, such as 1N4148, is needed to prohibit the emitter-base breakdown. Without that diode, when RDY voltage drops to VRDY,SAT after being pulled up, emitter voltage maintains operating voltage for LLC controller and almost all the voltage is applied to the emitter and base. Breakdown current flows from emitter, base, and drain of the MOSFET to the source of MOSFET. Because © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 www.fairchildsemi.com 17 AN-9731 Appendix 2: Gate Driver Design FL7930 directly drives the gate of the MOSFET and various combinations of gate driver circuits are possible. Figure 33 and Figure 31 show the three circuits that are widely used. When only one resistor is used, the turn-on and turn-off paths follow the same routine and turn-on and turn-off speed cannot be changed simultaneously. To accommodate this, make different paths by two resistors and diodes if possible. Turn-off current flows through the diode first, instead of RON, and then RON and ROFF show together. Accordingly, faster turn-off is possible. However, a turn-off path using the internal gate driver’s sinking path and current is limited by sinking current capability. If a PNP transistor is added between the gate and source of the MOSFET, the gate is shorted to source locally without sharing the current path to the gate driver. This makes the gate discharge to the much smaller path than that made by the controller. The possibility of ground bounce is reduced and power dissipation in the gate driver is reduced. Due to new high-speed MOSFET types such as SupreMOS® or SuperFET™, gate speed is getting fast. This decreases the switching loss of the MOSFET. At the same time, power systems suffer from the EMI deterioration or noise problems, like gate oscillation. Therefore, sometimes a gate discharge circuit is inevitable to use high-speed characteristics fully. The most difficult and uncertain task in direct gate drive is optimizing circuit layout. Gate driving path from the OUT pin, resistor, MOSFET gate, and MOSFET source to the GND pin should be as short as possible to reduce parasitic inductance; which may make MOSFET on/off speed slow or introduce unwanted gate oscillation. Using a wider PCB pattern for this lane reduces parasitic inductance. To damp unwanted gate oscillation made by the capacitance at the gate pin and parasitic inductance formed by MOSFET internal bonding wire and PCB pattern, proper resistance can match the impedance at the resonant frequency. To meet EMI regulations or for the redundant system, fast gate speed can be sacrificed by increasing serial resistance between the gate driver and gate. An optimal gate driver circuit needs intensive knowledge of MOSFET turn-on/off characteristics and consideration of the other critical performance requirements of the system. This is beyond the scope of this paper, but many reference papers can be found in the industry literature. Figure 33. Equivalent Circuit of Line Filter Stage © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 www.fairchildsemi.com 18 AN-9731 Appendix 3: Experimental Verification To show the validity of the design procedure presented in this application note, the converter of the design example was built and tested. All the circuit components are exactly as designed in the example. Figure 34 and Figure 35 show the inductor current and input current for 115VAC and 230VAC conditions. Figure 35 shows the startup performance for 95VAC full-load condition. Figure 37 (a) and (b) show the PFC output voltage changed under about 35V when AC input voltage was step changed from 115V to 235V and from 235V to 115V at full load. Figure 38 (a) and (b) show the PFC output voltage changed about 32V when output load was step changed from no-load to full-load condition and from full-load to no-load at 235V. The power factor at full load is 0.988 and 0.93 for 110VAC and 230VAC, respectively. (a) Input Voltage Change from 115V to 235V (b) Input Voltage Change from 235V to 115V Figure 34. Inductor Current Waveforms at 115VAC Figure 37. Output Dynamic Response at Po=100W Figure 35. Inductor Current Waveforms at 230VAC (a) Output Load Change from 0W to 100W (b) Output Load Change from 100W to 0W Figure 36. Startup Performance at 95VAC, Full Load Figure 38. Output Dynamic Response at VIN=235VAC © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 www.fairchildsemi.com 19 AN-9731 Definition of Terms η is the efficiency. θ is the displacement angle. ΔB is the maximum flux swing of the core at nominal output power in Tesla. Ae is the cross-sectional area of core. AW is the window area of core. BMAX is the maximum flux density of boost inductor at maximum output power in Tesla. CCOMP,HF is the high-frequency compensation capacitance. CCOMP,LF is the low-frequency compensation capacitance. Ceff is the effective capacitance shown at the MOSFET drain pin. CEA is the effective input capacitance to meet a given displacement factor. CEXT is the external capacitance at drain-source to decrease the turn-off slope. CEQ is the equivalent input capacitance. CFB is the feedback capacitance parallel with RFB2. COUT is the output capacitance. COSS is the output capacitance of power MOSFET. CPAR is the parasitic capacitance at drain-source of power MOSFET. CZCD is the capacitance connected at ZCD pin to improve noise immunity. dWIRE is the diameter of boost inductor winding wire. DF is the displacement factor between input voltage and input current. fC is the crossover frequency. fCP is the high-frequency compensation pole to attenuate the switching ripple. fCZ is the compensation zero. fLINE is the line frequency. fI is the integral gain of the compensator. fP is the pole frequency in the PFC power stage transfer function. fSW is the switching frequency. fSW,MIN is the minimum switching frequency. ICS,LIM is the pulse-by-pulse current limit level determined by sensing resistor. IDOUT,AVE is the average current of output diode. IIN,MAX is the maximum input current from the AC outlet. IIN,MAXRMS is the maximum RMS (Root Mean Square) input current from the AC outlet. IL is the inductor current at the nominal output power. IL,PK is the maximum peak inductor current at the nominal output power. IL,RMS is the RMS value of the inductor current at the nominal output power. IL,DENSITY is the current density of the boost inductor coil. IOUT is the nominal output current of the boost PFC stage. IQ,RMS is the RMS current at the power switch. IRDY,SK is the allowable sink current for the internal MOSFET in RDY pin. KSAW is the internal gain of sawtooth generator (that of FL7930 is 8.496×10-6). L is the boost inductance. NAUX is the number of turns of auxiliary winding in boost inductor. NBOOST is the number of turns of primary winding in boost inductor. NWIRE is the number of strands of boost inductor winding wire. PDOUT is the loss of output diode. POUT is the nominal output power of boost PFC stage. PQ,CON is conduction loss of the power MOSFET. PQ,SWOFF is turn-off loss of power MOSFET. PQ,DISCHRGE is the drain-source capacitance discharge loss and consumed at power MOSFET. PQ is the total loss of power MOSFET made by PQ,CON, PQ,SWOFF, and PQ,DISCHARGE. PRCS is the power loss caused by current-sense resistance. RCOMP is the compensation resistance. RCS is the power MOSFET current-sense resistance. RDS,ON is the static drain-source on resistance of the power switch. RFB1 is the feedback resistance between the INV pin and output voltage. RFB2 is the feedback resistance between the INV pin and ground. RL is the output load resistance in a given load condition. RPULLUP is the pull-up resistance between the RDY pin and pull-up voltage. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 www.fairchildsemi.com 20 AN-9731 RZCD is the resistor connected at the ZCD pin to optimize THD. tHOLD is the required hold-up time. tOFF is the inductor current reset time. tON,MAX is the maximum on time fixed internally. tON,MAX1 is the programmed maximum on time. VCOMP is compensation pin voltage. VCS,LIM is power MOSFET current-sense limit voltage. VDROP,DOUT is the forward-voltage drop of output diode. VIN(t) is the rectified line voltage. VIN,PK is the amplitude of line voltage. VLINE is RMS line voltage. VLINE,MAX is the maximum RMS line voltage. VLINE,MIN is the minimum RMS line voltage. VLINE,OVP is the line OVP trip point in RMS. VOPTO,F is the input forward voltage drop of opto-coupler. VOUT is the PFC output voltage. VOUT,MIN is the allowable minimum output voltage during the hold-up time. VOUT,RDYH is the VOUT to trigger PFC RDY out pulls high. VOUT,RDYL is the VOUT to trigger PFC RDY out drops to zero. ΔVOUT,RIPPLE is the peak-to-peak output voltage ripple. VPULLUP is the pull-up voltage for RDY pin. VRDY,SAT is the internal saturation voltage of RDY pin. VREF is the internal reference voltage for the feedback input. VOVP,MAX is the maximum tolerance of Over-Voltage Protection specification VST,COUT is the voltage stress at the output capacitor. VST,Q is the voltage stress at the power MOSFET. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 www.fairchildsemi.com 21 AN-9731 References [1] Fairchild Datasheet FAN9612, Interleaved Dual BCM, PFC Controller [2] Fairchild Datasheet FL7930 Critical Conduction Mode PFC Controller [3] Fairchild Application Note AN-6027, Design of Power Factor Correction Circuit Using FAN7530 [4] Fairchild Application Note AN-8035, Design of Power Factor Correction Circuit Using FAN7930 [5] Fairchild Application Note AN-6086, Design Consideration for Interleaved BCM PFC using FAN9612 [6] Robert W. Erikson, Dragan Maksimovic, Fundamentals of Power Electronics, Second Edition, Kluwer Academic Publishers, 2001. Related Datasheets FL7930 — Critical Conduction Mode PFC Controller FAN9611 / FAN9612 — Interleaved Dual BCM PFC Controllers 1N/FDLL 914/A/B / 916/A/B / 4148 / 4448 Small Signal Diode PN2222A/MMBT2222A/PZT2222A NPN General Purpose Amplifier FDP12N60NZ — 600V N-Channel MOSFET, UniFETTM FFPF08H60S — 8A, 600V Hyperfast Rectifier DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 3/24/11 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 22