www.fairchildsemi.com KA3882C/KA3883C SMPS Controller Features Description • • • • • • • The KA3882C/KA3883C is a fixed PWM controller for Off Line and DC to DC converter applications. The internal circuits include an UVLO, a low start up current circuit, a temperature compensated reference, a high gain error amplifier, a current sensing comparator, and the high current totem-pole output for driving a POWER MOSFET. Also the KA3882C/KA3883C provides low start-up current below 0.3mA and short shutdown delay time typ. 100ns. The KA3882C has the UVLO threshold of 16V (on) and 10V(off). The KA3883C is 8.4V(on) and 7.6V(off). The KA3882C and KA3883C can operate within 100% duty cycle. Low Start Current 0.2mA (Typ) Operating Range Up To 500kHz Cycle by Cycle Current Limiting Under Voltage Lock Out With Hysteresis Short Shutdown Delay Time: Typ.100ns High Current Totem-Pole Output Output Swing Limiting: 22V 8-DIP 1 8-SOP 1 Internal Block Diagram 7 VCC 29V 5V VREF VREF 8 SET/ RESET 5 GND UVLO Internal Bias Good LOGIC 7 PWR VC 1/2VREF VFB 2 Error Amp + - C.S PWM Comp. LATCH 1/3 R 22V 1V 6 OUTPUT S COMP 1 5 PWR T C.S 3 RT/CT 4 GND OSCILLATOR Rev. 1.0.1 ©2002 Fairchild Semiconductor Corporation KA3882C/KA3883C Absolute Maximum Ratings Parameter Symbol Value Unit Supply Voltage VCC 30 V Output Current IO ±1 A VI(ANA) -0.3 to 6.3 V ISINK(EA) 10 mA PD 1 W Thermal Resistance, Junction-to-Air (Note4) 8-SOP 8-DIP Rθja 280 95 °C/W Storage Temperature Tstg -65 ~ 150 °C Analog Inputs (pin 2, 3) Error Amp. Output Sink Current Power Dissipation Electrical Characteristics (VCC = 15V, RT = 10kΩ, CT = 3.3nF, TA = 0°C to +70°C ,Unless otherwise specified) Parameter Symbol Conditions Min. Typ. Max. Unit 4.9 - 5.0 6 5.1 20 V mV REFERENCE SECTION Output Voltage Line Regulation VREF ∆VREF TJ = 25°C, IO = 1mA VCC = 12V to 25V Load Regulation ∆VREF IO = 1mA to 20mA - 6 25 mV ISC Ta = 25°C - -100 -180 mA FOSC TJ = 25°C 47 52 57 kHz Output Short Circuit OSILLATOR SECTION Initial Accuracy Voltage Stability Amplitude Discharge Current CURRENT SENSE SECTION Gain Maximum Input Signal PSRR Input Bias Current Delay to Output 2 STV VCC = 12V to 25V - 0.2 1 % VOSC VPIN4, Peak to Peak - 1.7 - V IDISCHG TJ = 25°C, Pin4 = 2V 7.8 8.3 8.8 mA (Note2, 3) 2.85 3 3.15 V/V VPIN1 = 5V(Note2) 0.9 1.0 1.1 V VCC = 12V to 25V (Note1, 2) - - 70 -2 -10 dB uA VPIN3 = 0 V to 2V (Note1) - 100 200 ns GV VI(MAX) PSRR IBIAS TD KA3882C/KA3883C Electrical Characteristics (Continued) (VCC = 15V, RT = 10kΩ, CT = 3.3nF, TA = 0°C to +70°C, Unless otherwise specified) Parameter Symbol Conditions Min. Typ. Max. Unit 2.42 2.50 2.58 V ERROR AMPLIFIER SECTION Input Voltage VI TPIN1 = 2.5V Input Bias Current IBIAS - -0.3 -2 uA Open Loop Gain GVO VO = 2V to 4V (Note1) 65 90 - dB Unity Gain Bandwidth GBW TJ= 25°C (Note1) 0.7 1 - MHz PSRR PSRR VCC = 12V to 25V (Note1) 60 70 - dB ISINK VPIN2 = 2.7V, VPIN1 = 1.1V 2 6 - mA ISOURCE VPIN2 = 2.3V, VPIN1 = 5.0V -0.5 -0.8 - mA Output Sink Current Output Source Current - Output High Voltage VOH VPIN2 = 2.3V, R1 = 15kΩ to GND 5 6 - V Output Low Voltage VOL VPIN2 = 2.7V, R1 = 15kΩ to Pin8 - 0.8 1.1 V OUTPUT SECTION Output Low Level VOL Output High Level VOH ISINK = 20mA - 0.1 0.4 V ISINK = 200mA - 1.5 2.2 V ISOURCE = 20mA 13 13.5 - V ISOURCE = 200mA 12 13.5 - V Rise Time tR TJ = 25°C, C1 = 1nF (Note1) - 40 100 ns Fall Time tF TJ = 25°C, C1 = 1nF (Note1) - 40 100 ns VCC = 27V, C1 = 1nF - 22 - V KA3882C 15 16 17 V KA3883C 7.8 8.4 9.0 V Output Voltage Swing Limit VOLIM UNDER VOLTAGE LOCKOUT SECTION Start Threshold VTH Min. Operating Voltage ( After turn on ) VTL KA3882C 9 10 11 V KA3883C 7.0 7.6 8.2 V 94 96 100 % PWM SECTION Maximum Duty Cycle DMAX KA3882C/KA3883C Minimum Duty Cycle DMIN - - - 0 % Start-Up Current IST - - 0.2 0.4 mA Operating Supply Current ICC VPIN2 = VPIN3 = 0V - 11 17 mA VCC Zener Voltage VZ ICC = 25mA - 29 - V TOTAL STANDBY CURRENT * Adjust VCC above the start threshold before setting at 15V Notes : 1. These parameters, although guaranteed, are not 100% tested in production. 2. Parameter measured at trip point of latch with V2 = 0V. 3. Gain defined as: GV = ∆VPIN1∆VPIN3(VPIN3 = 0 to 0.8V) 4. Junction-to-air thermal resistance test enviroments. -. PCB information ; Board thickness : 1.6mm , Board dimension : 76.2 X 114.3mm2 , Ref. : EIA / JSED51-3 and EIA / JSED51-7 -. Board structure; Using the single layer PCB. 3 KA3882C/KA3883C Mechanical Dimensions Package #4 #5 1.524 ±0.10 0.060 ±0.004 0.46 ±0.10 #8 2.54 0.100 9.60 MAX 0.378 #1 9.20 ±0.20 0.362 ±0.008 ( 6.40 ±0.20 0.252 ±0.008 0.018 ±0.004 0.79 ) 0.031 8-DIP 5.08 MAX 0.200 7.62 0.300 3.40 ±0.20 0.134 ±0.008 +0.10 0.25 –0.05 +0.004 0~15° 4 0.010 –0.002 3.30 ±0.30 0.130 ±0.012 0.33 MIN 0.013 KA3882C/KA3883C Mechanical Dimensions (Continued) Package 8-SOP MIN #5 6.00 ±0.30 0.236 ±0.012 8° 0~ +0.10 0.15 -0.05 +0.004 0.006 -0.002 MAX0.10 MAX0.004 1.80 MAX 0.071 3.95 ±0.20 0.156 ±0.008 5.72 0.225 0.41 ±0.10 0.016 ±0.004 #4 1.27 0.050 #8 5.13 MAX 0.202 #1 4.92 ±0.20 0.194 ±0.008 ( 0.56 ) 0.022 1.55 ±0.20 0.061 ±0.008 0.1~0.25 0.004~0.001 0.50 ±0.20 0.020 ±0.008 5 KA3882C/KA3883C Ordering Information Product Number Package KA3882C 8-DIP KA3882CD 8-SOP KA3883C 8-DIP KA3883CD 8-SOP Operating Temperature 0 ~ +70°C DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 9/10/02 0.0m 001 Stock#DSxxxxxxxx ” 2002 Fairchild Semiconductor Corporation