FDB3632_F085
N-Channel PowerTrench® MOSFET
100V, 80A, 9mΩ
Features
Applications
• r DS(ON) = 7.5mΩ (Typ.), V GS = 10V, ID = 80A
• DC/DC converters and Off-Line UPS
• Qg(tot) = 84nC (Typ.), VGS = 10V
• Distributed Power Architectures and VRMs
• Low Miller Charge
• Primary Switch for 24V and 48V Systems
• Low QRR Body Diode
• High Voltage Synchronous Rectifier
• UIS Capability (Single Pulse and Repetitive Pulse)
• Qualified to AEC Q101
• Direct Injection / Diesel Injection Systems
• RoHS Compliant
• 42V Automotive Load Control
• Electronic Valve Train Systems
D
DRAIN
(FLANGE)
GATE
G
SOURCE
TO-263AB
S
FDB SERIES
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
Drain to Source Voltage
Parameter
Ratings
100
Units
V
VGS
Gate to Source Voltage
±20
V
Continuous (TC < 111oC, VGS = 10V)
80
A
Continuous (Tamb = 25oC, VGS = 10V, R θJA = 43oC/W)
12
A
Drain Current
ID
Pulsed
E AS
PD
TJ, TSTG
Single Pulse Avalanche Energy (Note 1)
Figure 4
A
338
mJ
Power dissipation
310
W
Derate above 25oC
2.07
W/oC
Operating and Storage Temperature
o
-55 to +175
C
Thermal Characteristics
RθJC
Thermal Resistance Junction to Case TO-220, TO-263, TO-262
RθJA
Thermal Resistance Junction to Ambient TO-220, TO-262 (Note 2)
RθJA
2
Thermal Resistance Junction to Ambient TO-263, 1in copper pad area
0.48
o
C/W
62
o
C/W
43
o
C/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2012 Fairchild Semiconductor Corporation
FDB3632_F085 Rev. C1
FDB3632_F085
March 2012
Device Marking
FDB3632
Device
FDB3632_F085
Package
TO-263AB
Reel Size
330mm
Tape Width
24mm
Quantity
800 units
Electrical Characteristics TC = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
100
-
-
V
-
-
1
-
-
250
µA
VGS = ±20V
-
-
±100
nA
V GS = VDS, ID = 250µA
2
-
4
V
ID=80A, VGS=10V
-
0.0075
0.009
ID=80A, VGS=10V, TC=175oC
-
0.018
0.022
-
6000
-
pF
-
820
-
pF
-
200
-
pF
-
84
110
nC
-
11
14
nC
-
30
-
nC
VDS = 80V
VGS = 0V
TC= 150oC
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
Ω
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
Qg(TOT)
Total Gate Charge at 10V
VGS = 0V to 10V
Qg(TH)
Threshold Gate Charge
VGS = 0V to 2V
Qgs
Gate to Source Gate Charge
Qgs2
Gate Charge Threshold to Plateau
Qgd
Gate to Drain “Miller” Charge
VDS = 25V, VGS = 0V,
f = 1MHz
VDD = 50V
ID = 80A
Ig = 1.0mA
-
20
-
nC
-
20
-
nC
ns
Resistive Switching Characteristics (VGS = 10V)
tON
Turn-On Time
-
-
102
td(ON)
Turn-On Delay Time
-
30
-
ns
tr
Rise Time
-
39
-
ns
td(OFF)
Turn-Off Delay Time
-
96
-
ns
tf
Fall Time
-
46
-
ns
tOFF
Turn-Off Time
-
-
213
ns
V
VDD = 50V, ID = 80A
VGS = 10V, RGS = 3.6Ω
Drain-Source Diode Characteristics
ISD = 80A
-
-
1.25
ISD = 40A
-
-
1.0
V
Reverse Recovery Time
ISD = 75A, dISD/dt= 100A/µs
-
-
64
ns
Reverse Recovered Charge
ISD = 75A, dISD/dt= 100A/µs
-
-
120
nC
VSD
Source to Drain Diode Voltage
trr
QRR
Notes:
1: Starting TJ = 25°C, L = 0.12mH, IAS = 75A.
2: Pulse Width = 100s
©2012 Fairchild Semiconductor Corporation
FDB3632_F085 Rev. C1
FDB3632_F085
Package Marking and Ordering Information
FDB3632_F085
Typical Characteristics TA = 25°C unless otherwise noted
125
CURRENT LIMITED
BY PACKAGE
1.0
100
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
0.2
0
0
25
50
75
100
150
125
175
75
VGS = 10V
50
25
0
25
TC , CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
50
75
100
125
TC, CASE TEMPERATURE (oC)
150
175
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (s)
100
101
Figure 3. Normalized Maximum Transient Thermal Impedance
2000
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
1000
IDM, PEAK CURRENT (A)
CURRENT AS FOLLOWS:
VGS = 10V
I = I25
175 - TC
150
100
50
10-5
10-4
10-3
10-2
t, PULSE WIDTH (s)
10-1
100
101
Figure 4. Peak Current Capability
©2012 Fairchild Semiconductor Corporation
FDB3632_F085 Rev. C1
FDB3632_F085
Typical Characteristics TA = 25°C unless otherwise noted
400
200
10µs
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
100
100µs
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10
1ms
1
10ms
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
DC
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
100
STARTING TJ = 25oC
STARTING TJ = 150oC
0.1
1
tAV, TIME IN AVALANCHE (ms)
0.01
200
Figure 5. Forward Bias Safe Operating Area
10
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
150
150
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
90
VGS = 6V
VGS = 10V
TJ = 175oC
60
TJ = 25oC
TJ = -55oC
30
VGS = 5.5V
120
ID, DRAIN CURRENT (A)
120
ID , DRAIN CURRENT (A)
100
10
0.1
1
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
90
VGS = 5V
60
TC = 25oC
30
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
0
3.0
3.5
4.0
4.5
5.0
5.5
VGS , GATE TO SOURCE VOLTAGE (V)
0
6.0
Figure 7. Transfer Characteristics
4
Figure 8. Saturation Characteristics
10
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 6V
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
DRAIN TO SOURCE ON RESISTANCE (m Ω)
1
2
3
VDS , DRAIN TO SOURCE VOLTAGE (V)
9
8
VGS = 10V
7
2.0
1.5
1.0
VGS = 10V, ID =80A
6
0.5
0
20
40
62
ID, DRAIN CURRENT (A)
80
Figure 9. Drain to Source On Resistance vs Drain
Current
©2012 Fairchild Semiconductor Corporation
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
160
200
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
FDB3632_F085 Rev. C1
FDB3632_F085
Typical Characteristics TA = 25°C unless otherwise noted
1.4
1.2
VGS = VDS, ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
1.2
1.0
0.8
0.6
0.4
0.2
1.1
1.0
0.9
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
200
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
-80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
200
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
10000
10
VGS , GATE TO SOURCE VOLTAGE (V)
VDD = 50V
C, CAPACITANCE (pF)
CISS = CGS + CGD
COSS ≅ CDS + CGD
1000
CRSS = CGD
VGS = 0V, f = 1MHz
100
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 80A
ID = 40A
2
0
0.1
1
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
100
Figure 13. Capacitance vs Drain to Source
Voltage
©2012 Fairchild Semiconductor Corporation
0
20
40
60
Qg, GATE CHARGE (nC)
80
100
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
FDB3632_F085 Rev. C1
VDS
BVDSS
tP
VDS
L
IAS
VDD
VARY tP TO OBTAIN
+
RG
REQUIRED PEAK IAS
VDD
-
VGS
DUT
tP
IAS
0V
0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT)
VDS
L
VGS = 10V
VGS
+
VDD
VGS
-
VGS = 2V
DUT
Qgs2
0
Ig(REF)
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
RL
tr
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
50%
50%
PULSE WIDTH
VGS
0
Figure 19. Switching Time Test Circuit
©2012 Fairchild Semiconductor Corporation
10%
Figure 20. Switching Time Waveforms
FDB3632_F085 Rev. C1
FDB3632_F085
Test Circuits and Waveforms
FDB3632_F085
Thermal Resistance vs. Mounting Pad Area
(T
–T )
JM
A
P DM = ----------------------------Rθ JA
(EQ. 1)
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
80
RθJA = 26.51+ 19.84/(0.262+Area) EQ.2
RθJA = 26.51+ 128/(1.69+Area) EQ.3
60
RθJA (oC/W)
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
40
20
0.1
1
10
(0.645)
(6.45)
AREA, TOP COPPER AREA in2 (cm2)
(64.5)
Figure 21. Thermal Resistance vs Mounting
Pad Area
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
19.84
( 0.262 + Area )
R θ JA = 26.51 + -------------------------------------
(EQ. 2)
Area in Inches Squared
128
( 1.69 + Area )
R θ JA = 26.51 + ----------------------------------
(EQ. 3)
Area in Centimeters Squared
©2012 Fairchild Semiconductor Corporation
FDB3632_F085 Rev. C1
rev May 2002
LDRAIN
DPLCAP
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RSLC2
5
51
ESLC
EVTHRES
+ 19 8
+
LGATE
GATE
1
11
+
17
EBREAK 18
-
50
RDRAIN
6
8
ESG
DBREAK
+
Lgate 1 9 5.61e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 2.7e-9
RLDRAIN
RSLC1
51
Ebreak 11 7 17 18 102.5
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
DRAIN
2
5
EVTEMP
RGATE + 18 22
9
20
21
16
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
7
SOURCE
3
RSOURCE
RLSOURCE
RLgate 1 9 56.1
RLdrain 2 5 10
RLsource 3 7 27
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
S1A
12
S2A
13
8
14
13
S1B
CA
15
17
18
RVTEMP
S2B
13
CB
19
6
8
VBAT
5
8
EDS
-
IT
14
+
+
EGS
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 3.8e-3
Rgate 9 20 1.1
RSLC1 5 51 RSLCMOD 1.0e-6
RSLC2 5 50 1.0e3
Rsource 8 7 RsourceMOD 2.5e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
RBREAK
-
+
8
22
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*350),3))}
.MODEL DbodyMOD D (IS=5.9E-11 N=1.07 RS=2.3e-3 TRS1=3.0e-3 TRS2=1.0e-6
+ CJO=4e-9 M=0.58 TT=4.8e-8 XTI=4.2)
.MODEL DbreakMOD D (RS=0.17 TRS1=3.0e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=15e-10 IS=1.0e-30 N=10 M=0.6)
.MODEL MstroMOD NMOS (VTO=4.1 KP=200 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MmedMOD NMOS (VTO=3.4 KP=10.0 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.1)
.MODEL MweakMOD NMOS (VTO=2.75 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.1e+1 RS=0.1)
.MODEL RbreakMOD RES (TC1=1.0e-3 TC2=-1.7e-6)
.MODEL RdrainMOD RES (TC1=8.5e-3 TC2=2.8e-5)
.MODEL RSLCMOD RES (TC1=2.0e-3 TC2=2.0e-6)
.MODEL RsourceMOD RES (TC1=4e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-4.0e-3 TC2=-1.8e-5)
.MODEL RvtempMOD RES (TC1=-4.4e-3 TC2=2.2e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-2)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.8 VOFF=0.4)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.4 VOFF=-0.8)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2012 Fairchild Semiconductor Corporation
FDB3632_F085 Rev. C1
FDB3632_F085
PSPICE Electrical Model
.SUBCKT FDB3632 2 1 3 ;
CA 12 8 1.7e-9
Cb 15 14 2.5e-9
Cin 6 8 6.0e-9
FDB3632_F085
SABER Electrical Model
REV May 2002
template FDB3632 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=5.9e-11,nl=1.07,rs=2.3e-3,trs1=3.0e-3,trs2=1.0e-6,cjo=4e-9,m=0.58,tt=4.8e-8,xti=4.2)
dp..model dbreakmod = (rs=0.17,trs1=3.0e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=15e-10,isl=10.0e-30,nl=10,m=0.6)
m..model mstrongmod = (type=_n,vto=4.1,kp=200,is=1e-30, tox=1)
m..model mmedmod = (type=_n,vto=3.4,kp=10.0,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.75,kp=0.05,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-2)
LDRAIN
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-4)
DPLCAP 5
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.8,voff=0.4)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.4,voff=-0.8) 10
RLDRAIN
RSLC1
c.ca n12 n8 = 1.7e-9
51
c.cb n15 n14 = 2.5e-9
RSLC2
c.cin n6 n8 = 6.0e-9
DRAIN
2
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
spe.ebreak n11 n7 n17 n18 = 102.5
spe.eds n14 n8 n5 n8 = 1
GATE
spe.egs n13 n8 n6 n8 = 1
1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
LGATE
EVTEMP
RGATE + 18 22
9
20
21
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
-
MMED
MSTRO
RLGATE
CIN
8
LSOURCE
7
SOURCE
3
RSOURCE
i.it n8 n17 = 1
RLSOURCE
S1A
l.lgate n1 n9 = 5.61e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2.7e-9
res.rlgate n1 n9 = 56.1
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 27
DBREAK
50
-
12
S2A
13
8
14
13
S1B
CA
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
-
19
14
+
+
IT
VBAT
5
8
EDS
-
+
8
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=1.0e-3,tc2=-1.7e-6
res.rdrain n50 n16 = 3.8e-3, tc1=8.5e-3,tc2=2.8e-5
res.rgate n9 n20 = 1.1
res.rslc1 n5 n51 = 1.0e-6, tc1=2.0e-3,tc2=2.0e-6
res.rslc2 n5 n50 = 1.0e3
res.rsource n8 n7 = 2.5e-3, tc1=4e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-4.0e-3,tc2=-1.8e-5
res.rvtemp n18 n19 = 1, tc1=-4.4e-3,tc2=2.2e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/350))** 3))
}
}
©2012 Fairchild Semiconductor Corporation
FDB3632_F085 Rev. C1
th
JUNCTION
FDB3632
CTHERM1 TH 6 7.5e-3
CTHERM2 6 5 8.0e-3
CTHERM3 5 4 9.0e-3
CTHERM4 4 3 2.4e-2
CTHERM5 3 2 3.4e-2
CTHERM6 2 TL 6.5e-2
RTHERM1
CTHERM1
6
RTHERM1 TH 6 3.1e-4
RTHERM2 6 5 2.5e-3
RTHERM3 5 4 2.2e-2
RTHERM4 4 3 8.1e-2
RTHERM5 3 2 1.35e-1
RTHERM6 2 TL 1.5e-1
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model FDB3632
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =7.5e-3
ctherm.ctherm2 6 5 =8.0e-3
ctherm.ctherm3 5 4 =9.0e-3
ctherm.ctherm4 4 3 =2.4e-2
ctherm.ctherm5 3 2 =3.4e-2
ctherm.ctherm6 2 tl =6.5e-2
rtherm.rtherm1 th 6 =3.1e-4
rtherm.rtherm2 6 5 =2.5e-3
rtherm.rtherm3 5 4 =2.2e-2
rtherm.rtherm4 4 3 =8.1e-2
rtherm.rtherm5 3 2 =1.35e-1
rtherm.rtherm6 2 tl =1.5e-1
}
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
©2012 Fairchild Semiconductor Corporation
CASE
FDB3632_F085 Rev. C1
FDB3632_F085
SPICE Thermal Model
REV May 2002
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Rev. I60
©2012 Fairchild Semiconductor Corporation
FDB3632_F085 Rev. C1