FDS3672 N-Channel PowerTrench® MOSFET 100V, 7.5A, 22mΩ Features Applications • r DS(ON) = 19mΩ (Typ.), VGS = 10V, ID = 7.5A • DC/DC converters and Off-Line UPS • Qg(tot) = 28nC (Typ.), VGS = 10V • Distributed Power Architectures and VRMs • Low Miller Charge • Primary Switch for 24V and 48V Systems • Low QRR Body Diode • High Voltage Synchronous Rectifier • Optimized efficiency at high frequencies • UIS Capability (Single Pulse and Repetitive Pulse) Formerly developmental type 82763 Branding Dash 5 1 2 3 4 5 4 6 3 7 2 8 1 SO-8 MOSFET Maximum Ratings TA = 25°C unless otherwise noted Symbol VDSS Drain to Source Voltage Parameter Ratings 100 Units V VGS Gate to Source Voltage ±20 V Continuous (TA = 25oC, VGS = 10V, R θJA = 50oC/W) 7.5 A Continuous (TA = 100oC, VGS = 10V, RθJA = 50oC/W) 4.8 A Drain Current ID Pulsed EAS PD TJ, TSTG Figure 4 A Single Pulse Avalanche Energy (Note 1) 416 mJ Power dissipation 2.5 W Derate above 25oC 20 mW/oC Operating and Storage Temperature o -55 to 150 C Thermal Characteristics RθJA Thermal Resistance, Junction to Ambient at 10 seconds (Note 3) 50 oC/W RθJA Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3) 85 o 25 oC/W RθJC Thermal Resistance, Junction to Case (Note 2) C/W Package Marking and Ordering Information Device Marking FDS3672 ©2012 Fairchild Semiconductor Corporation Device FDS3672 Package SO-8 Reel Size 330mm Tape Width 12mm Quantity 2500 units FDS3672 Rev. C2 FDS3672 April 2012 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V 100 - - V - - 1 - - 250 µA VGS = ±20V - - ±100 nA V GS = VDS, ID = 250µA 2 - 4 V ID = 7.5A, VGS = 10V - 0.019 0.023 ID = 6.8A, VGS = 6V - 0.023 0.028 ID = 7.5A, VGS = 10V, TC = 150oC - 0.035 0.043 - 2015 - - 285 - pF - 70 - pF nC VDS = 80V VGS = 0V TC = 150oC On Characteristics VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance Ω Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance VDS = 25V, VGS = 0V, f = 1MHz pF Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V - 28 37 Qg(TH) Threshold Gate Charge VGS = 0V to 2V - 4 6 nC Qgs Gate to Source Gate Charge - 10 - nC Qgs2 Gate Charge Threshold to Plateau - 6.8 - nC Qgd Gate to Drain “Miller” Charge - 6 - nC VDD = 50V ID = 7.5A Ig = 1.0mA Switching Characteristics (VGS = 10V) tON Turn-On Time - - 51 ns td(ON) Turn-On Delay Time - 14 - ns tr Rise Time td(OFF) Turn-Off Delay Time tf tOFF - 20 - ns - 37 - ns Fall Time - 27 - ns Turn-Off Time - - 96 ns V VDD = 50V, ID = 4A VGS = 10V, RGS = 10Ω Drain-Source Diode Characteristics ISD = 7.5A - - 1.25 ISD = 4A - - 1.0 V Reverse Recovery Time ISD= 7.5A, dISD/dt= 100A/µs - - 55 ns Reverse Recovered Charge ISD= 7.5A, dISD/dt= 100A/µs - - 90 nC VSD Source to Drain Diode Voltage trr QRR Notes: 1: Starting TJ = 25°C, L = 13mH, IAS = 8A. 2: RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R θJC is guaranteed by design while RθCA is determined by the user’s board design. 3: RθJA is measured with 1.0 in2 copper on FR-4 board ©2012 Fairchild Semiconductor Corporation FDS3672 Rev. C2 FDS3672 Electrical Characteristics TA = 25°C unless otherwise noted FDS3672 Typical Characteristics TA = 25°C unless otherwise noted 8 1.2 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER VGS = 10V 1.0 0.8 0.6 0.4 6 4 2 0.2 0 0 0 25 50 75 100 125 150 25 50 Figure 1. Normalized Power Dissipation vs Ambient Temperature 2 100 125 0.1 150 Figure 2. Maximum Continuous Drain Current vs Case Temperature DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 1 ZθJA, NORMALIZED THERMAL IMPEDANCE 75 TC, CASE TEMPERATURE (o C) TA , AMBIENT TEMPERATURE (oC) RθJA=50oC/W PDM t1 0.01 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA 0.001 10-5 10 -4 10-3 10-2 10-1 100 t , RECTANGULAR PULSE DURATION (s) 101 102 103 Figure 3. Normalized Maximum Transient Thermal Impedance 1000 TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: IDM, PEAK CURRENT (A) TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION I = I 25 VGS = 10V 150 - TC 125 100 10 5 10-5 10 -4 10-3 10-2 10-1 t , PULSE WIDTH (s) 100 101 102 103 Figure 4. Peak Current Capability ©2012 Fairchild Semiconductor Corporation FDS3672 Rev. C2 FDS3672 Typical Characteristics TA = 25°C unless otherwise noted 300 10 10µs 8 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 100 100µs 10 1ms 1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms 100ms 0.1 SINGLE PULSE TJ = MAX RATED TC = 25o C 6 TJ = 25 oC 4 2 1s 1.0 10.0 100 VDS, DRAIN TO SOURCE VOLTAGE (V) 30 VGS = 10V 20 TJ = 150oC TJ = 25oC VGS = 6V VGS = 5V 20 VGS = 4.5V 10 TA = 25oC TJ = -55oC PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0 0 2.5 3.0 3.5 4.0 4.5 5.0 VGS , GATE TO SOURCE VOLTAGE (V) 0 5.5 Figure 7. Transfer Characteristics 0.5 1.0 1.5 VDS , DRAIN TO SOURCE VOLTAGE (V) 2.0 Figure 8. Saturation Characteristics 24 2.0 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX NORMALIZED DRAIN TO SOURCE ON RESISTANCE DRAIN TO SOURCE ON RESISTANCE (m Ω) 100 Figure 6. Unclamped Inductive Switching Capability ID, DRAIN CURRENT (A) ID , DRAIN CURRENT (A) 10 tAV, TIME IN AVALANCHE (ms) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V 10 1 300 Figure 5. Forward Bias Safe Operating Area 30 TJ = 125 oC 1 0.1 0.01 0.1 TJ = 100 oC VGS = 6V 22 20 VGS = 10V 1.5 1.0 VGS = 10V, I D = 7.5A 18 0.5 0 2 4 ID, DRAIN CURRENT (A) 6 8 Figure 9. Drain to Source On Resistance vs Drain Current ©2012 Fairchild Semiconductor Corporation -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature FDS3672 Rev. C2 FDS3672 Typical Characteristics TA = 25°C unless otherwise noted 1.4 1.10 ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) -80 10 CISS = CGS + CGD COSS ≅ C DS + C GD CRSS = CGD 100 VGS = 0V, f = 1MHz 10 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 160 Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature VGS , GATE TO SOURCE VOLTAGE (V) C, CAPACITANCE (pF) 0.95 160 Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature 1000 1.00 0.90 0.4 5000 1.05 VDD = 50V 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 7.5A ID = 4A 2 0 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 13. Capacitance vs Drain to Source Voltage ©2012 Fairchild Semiconductor Corporation 100 0 5 10 15 20 Qg , GATE CHARGE (nC) 25 30 Figure 14. Gate Charge Waveforms for Constant Gate Currents FDS3672 Rev. C2 FDS3672 Test Circuits and Waveforms VDS BVDSS tP VDS L IAS VDD VARY tP TO OBTAIN + RG REQUIRED PEAK IAS VDD - VGS DUT tP IAS 0V 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS = 10V VGS + VDD VGS - VGS = 2V DUT Qgs2 0 Ig(REF) Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS tf 90% 90% + VGS VDD - 10% 0 10% DUT 90% RGS VGS 50% 50% PULSE WIDTH VGS 0 Figure 19. Switching Time Test Circuit ©2012 Fairchild Semiconductor Corporation 10% Figure 20. Switching Time Waveforms FDS3672 Rev. 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