FAIRCHILD FAN7080M_12

FAN7080_GF085
Half Bridge Gate Driver
Features
Description
• Qualified to AEC Q100
The FAN7080_GF085 is a half-bridge gate drive IC with reset
input and adjustable dead time control. It is designed for high
voltage and high speed driving of MOSFET or IGBT, which
operates up to 600V. Fairchild's high-voltage process and common-mode noise cancellation technique provide stable operation in the high side driver under high-dV/dt noise
circumstances. An advanced level-shift circuit allows high-side
gate driver operation up to VS=-5V (typical) at VBS=15V. Logic
input is compatible with standard CMOS outputs. The UVLO circuits for both channels prevent from malfunction when VCC and
VBS are lower than the specified threshold voltage. Combined
pin function for dead time adjustment and reset shutdown make
this IC packaged with space saving SOIC-8 Package. Minimum
source and sink current capability of output driver is 250mA and
500mA respectively, which is suitable for junction box application and half and full bridge application in the motor drive system.
• Floating channel designed for bootstrap operation fully operational to + 600V
• Tolerance to negative transient voltage on VS pin
• VS-pin dv/dt immune.
• Gate drive supply range from 5.5V to 20V
• Under-voltage lockout
• CMOS Schmitt-triggered inputs with pull-down
• High side output in phase with input
• IN input is 3.3V/5V logic compatible and available on 15V
input
• Matched propagation delay for both channels
• Dead time adjustable
SOIC-8
Typical Applications
• Junction Box
• Half and full bridge application in the motor drive system
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Ordering Information
Device
Package
Operating
Temp.
FAN7080M_GF085
SOIC-8
-40 C ~ 125 C
FAN7080MX_GF085
SOIC-8
-40 C ~ 125 C
X : Tape & Reel type
©2012 Fairchild Semiconductor Corporation
FAN7080_GF085 Rev. 1.0.1
1
www.fairchildsemi.com
FAN7080_GF085 Half Bridge Gate Driver
September 2012
VCC
VB
UVLO
vreg
IN
PULSE
GENERATOR
DEADTIME
CONTROL
500kΩ
PULSE
FILTER
R
R
Q
HO
S
VS
vreg
VCC
VCC
UVLO
SD/DT
LO
DELAY
500kΩ
COM
Pin Assignments
1
2
3
4
VCC
VB
IN
HO
SD/DT
VS
COM
LO
8
7
6
5
Pin Definitions
Pin Number
Pin Name
I/O
1
VCC
P
Pin Function Description
Driver supply voltage
2
IN
I
Logic input for high and low side gate drive output
3
SD/DT
I
Shut down input and dead time setting
4
COM
P
Ground
5
LO
A
Low side gate drive output for MOSFET Gate connection
6
VS
A
High side floating offset for MOSFET Source connection
7
HO
A
High side drive output for MOSFET Gate connection
8
VB
P
Driver output stage supply
©2012 Fairchild Semiconductor Corporation
FAN7080_GF085 Rev. 1.0.1
2
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FAN7080_GF085 Half Bridge Gate Driver
Block Diagrams
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM.
Parameter
Symbol
Min.
Max.
Unit
VS
VB-25
VB+0.3
V
High side floating supply offset voltage
High side floating supply voltage
VB
-0.3
625
V
High side floating output voltage
VHO
Vs-0.3
VB+0.3
V
Low side output voltage
VLO
-0.3
VCC + 0.3
V
Supply voltage
VCC
-0.3
25
V
Input voltage for IN
VIN
-0.3
Vcc+0.3
V
Input injection current. Full function, no latch
up;(Guaranteed by design). Test at 10V and
17V on Eng.Samples
IIN
-
+1
mA
Pd
0.625
W
Thermal resistance, junction to ambient
Power Dissipation
Rthja
200
C/W
Electrostatic discharge voltage
(Human Body Model)
VESD
1K
Charge device model
VCDM
500
Junction Temperature
Tj
Storage Temperature
TS
-55
V
V
150
C
150
C
Note: 1) The thermal resistance and power dissipation rating are measured bellow conditions;
JESD51-2: Integrated Circuit Thermal Test Method Environmental Conditions - Natural convection(StillAir)
JESD51-3 : Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Package
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Parameter
Symbol
High side floating supply voltage(DC)
Min.
Max.
Unit
VS + 6
VS + 20
V
VS
-5
600
V
VHO
Vs
VB
V
VB
1)
Transient:[email protected] 0.1 us
High side floating supply offset voltage(DC)
Transient: -25V(max) @0.1us @VBS<25V
High side floating output voltage
Low side output voltage
VLO
0
VCC
V
dv/dt
-
50
V/ns
Supply voltage for logic part
VCC
5.5
20
V
Logic input voltage
VIN
0
Vcc
V
200
KHz
-40
125
C
Allowable offset voltage Slew Rate
Switching Frequency
2)
3)
Ambient Temperature
Fs
Ta
Note: 1) The Vs offset is tested with all supplies biased at 15V differential.
2) Guaranteed by design.
3) When VDT= 1.2V.
©2012 Fairchild Semiconductor Corporation
FAN7080_GF085 Rev. 1.0.1
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FAN7080_GF085 Half Bridge Gate Driver
Absolute Maximum Ratings
Unless otherwise specified, -40°C <= Ta <=125°C, VCC = 15V, VBS = 15V, VS = 0V, CL = 1nF.
Parameter
Symbol
Conditions
Min.
Typ.
Max. Unit
VCC and VBS supply under voltage
positive going threshold
VCCUV+
VBSUV+
-
-
4.2
5.5
V
VCC and VBS supply under voltage
negative going threshold
VCCUVVBSUV-
-
2.8
3.6
-
V
VCC and VBS supply under voltage
hysteresis
VCCUVH
VBSUVH
-
0.2
0.6
-
V
tduvcc
tduvbs
VCC: 6V-->2.5V or 2.5V-->6V
VBS: 6V-->2.5V or 2.5V-->6V
0.5
0.5
-
20
20
us
us
ILK
VB=VS=600V
-
20
50
uA
Quiescent VBS supply current
IQBS
VIN=0 OR 5V, VSDT = 1.2V
20
75
150
uA
Quiescent Vcc supply current
IQCC
VIN=0 OR 5, VSDT = 1.2V
-
350
1000
uA
2.7
-
-
V
-
-
0.8
V
-
10
50
uA
-
0
2
uA
1.2
-
5
V
Vcc and VBS supply Characteristics
Under voltage lockout response time
Offset supply leakage current
Input Characteristics
High logic level input voltage
VIH
Low logic level input voltage
VIL
High logic level input bias current for IN
IIN+
VIN=5V
Low logic level input bias current for IN
IIN-
VIN=0V
VSDT dead time setting range
VDT
-
0.8
1.2
V
High logic level resistance for SD/DT
RSDT
VSDT=5V
100
500
1100
K
Low logic level input bias current for SD/DT
ISDT-
VSDT=0V
-
1
2
uA
VSDT shutdown threshold voltage
VSD
Output characteristics
High level output voltage, VCC-VHO
VOH(HO)
IO=0
-
-
0.1
V
Low level output voltage, VHO
VOL(HO)
IO=0
-
-
0.1
V
Output high short circuit pulse current
IO+(HO)
250
300
-
mA
Output low short circuit pulse current
IO-(HO)
500
600
-
mA
ROP(HO)
-
-
60

RON(HO)
-
-
30

Equivalent output resistance
High level output voltage, VB-VLO
VOH(LO)
IO=0
-
-
0.1
V
Low level output voltage, VLO
VOL(LO)
IO=0
-
-
0.1
V
Output high short circuit pulse current
IO+(LO)
250
-
-
mA
Output low short circuit pulse current
IO-(LO)
500
-
-
mA
ROP(LO)
-
-
60

RON(LO)
-
-
30

Equivalent output resistance
©2012 Fairchild Semiconductor Corporation
FAN7080_GF085 Rev. 1.0.1
4
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FAN7080_GF085 Half Bridge Gate Driver
Statics Electrical Characteristics
Unless otherwise specified, -40°C <= Ta <=125°C, VCC = 15V, VBS = 15V, VS = 0V, CL = 1nF.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Turn-on propagation delay
ton
VS=0V
-
750
1500
ns
Turn-off propagation delay
toff
VS=0V
-
130
250
ns
Turn -on rising time
tr
-
-
40
150
ns
Turn -off falling time
tf
-
-
25
400
ns
DT
VIN=0 or [email protected] VDT=1.2V
VIN=0 or [email protected] VDT=3.3V
250
1600
650
2100
1200
2600
ns
MDT
DT1 [email protected] VDT=1.2V
DT1 [email protected] VDT=3.3V
-
35
-
110
300
ns
-
Dead time, LS turn-off to HS turn-on
and HS turn-on to LS turn-off
Dead time matching time
Delay Matching, HS and LS turn-on
MTON
VDT=1.2V
Delay Matching, HS and LS turn-off
MTOFF
VDT=1.2V
25
110
ns
15
60
ns
Shutdown propagation delay
Tsd
-
180
330
ns
Switching Frequency
Fs1
VCC=VBS=20V
-
-
200
KHz
Fs2
VCC=VBS=5.5V
-
-
200
KHZ
©2012 Fairchild Semiconductor Corporation
FAN7080_GF085 Rev. 1.0.1
5
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FAN7080_GF085 Half Bridge Gate Driver
Dynamic Electrical Characteristics
Up to 600V
VCC
1
IN
R1
2
VDT
SHUTDOWN
/DEAD TIME
3
4
8
VCC
VB
IN
HO
SD/DT
VS
COM
LO
7
To Load
6
5
R2
VDT = Vdd*R2 / (R1+R2). Vdd is output voltage of Microcontroller.
The operating range that allows a VDT range of 1.2~3.3V.
When pulled lower than VDT [Typ. 0.5V] the device is shutdown.
Care must be taken to avoid below threshold spikes on pin 3 that can cause undesired shut down of the IC.
For this reason the connection of the components between pin 3 and ground has to be as short as possible.
And a capacitor (Typ 0.02uF )between pin3 and COM can prevent this spike. This pin can not be left
floating for the same reason.
©2012 Fairchild Semiconductor Corporation
FAN7080_GF085 Rev. 1.0.1
6
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FAN7080_GF085 Half Bridge Gate Driver
Typical Application Circuit
VCC=VBS=15V, -40C < tj < 125C
3000
Dead Time(ns)
2500
IN
SD/DT
2000
1500
1000
Max.
500
Typ.
0
1.0
HO
1.5
2.0
2.5
3.0
3.5
VDT, Deadtime Voltage(V)
LO
Figure 1. Input/output Timing Diagram
Figure 2. Dead Time VS VDT
SD
IN(LO)
50%
50%
tr
toff
50%
IN(HO)
ton
90%
LO
HO
tsd
tf
10%
90%
HO
LO
90%
10%
Figure 4. Shutdown Waveform Definitions
Figure 3. Switching Time Waveform Definitions
PWM(LO)
50%
50%
PWM(HO)
50%
50%
IN
LO
HO
90%
10%
HO
MTON
MTOFF
LO
90%
10%
HO
Figure 5. Delay Matching Waveform Definitions
FAN7080_GF085 Rev. 1.0.1
DT2
90%
LO
©2012 Fairchild Semiconductor Corporation
10%
DT1
Figure 6. Dead Time Waveform Definitions
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FAN7080_GF085 Half Bridge Gate Driver
Typical Waveforms
1500
1800
1400
Turn-on Delay Time(ns)
Turn-on Delay Time(ns)
VCC=VBS=15V, CL=1nF
1500
1200
Max.
900
Typ.
600
-50
VCC=15V, CL=1nF, ta=25C
1300
1200
Max.
1100
1000
900
Typ.
800
700
600
-25
0
25
50
75
100
500
10
125
12
Temperature( C)
Figure 7a. Turn-On Delay Time of HO vs VBS Temperature
18
20
1500
VCC=VBS=15V, CL=1nF
VCC=15V, CL=1nF, ta=25C
1400
Turn-on Delay Time(ns)
Turn-on Delay Time(ns)
16
Figure 7b. Turn-On Delay Time of HO vs VBS Supply Voltage
1800
1500
1200
Max.
900
14
VBIAS Supply Voltage(V)
o
Typ.
1300
1200
Max.
1100
1000
900
Typ.
800
700
600
600
-50
-25
0
25
50
75
100
500
10
125
12
o
Figure 8a. Turn-On Delay Time of LO vs Temperature
VCC=VBS=15V, CL=1nF
20
VCC=15V, CL=1nF, ta=25C
Turn-off Delay Time(ns)
Turn-off Delay Time(ns)
18
500
400
300
Max.
200
0
-50
16
Figure 8b. Turn-On Delay Time vs of LO VBS Supply Voltage
500
100
14
VBIAS Supply Voltage(V)
Temperature( C)
Typ.
-25
0
25
50
75
100
Max.
200
Typ.
100
12
14
16
18
20
VBIAS Supply Voltage(V)
Temperature( C)
Figure 9a. Turn-Off Delay Time of HO vs Temperature
FAN7080_GF085 Rev. 1.0.1
300
0
10
125
o
©2012 Fairchild Semiconductor Corporation
400
Figure 9b. Turn-Off Delay Time of HO vs VBS Supply Voltage
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FAN7080_GF085 Half Bridge Gate Driver
Performance Graphs (This performance graphs based on ambient temperature -40C ~125C)
500
VCC=15V, CL=1nF, ta=25C
400
Turn-off Delay Time(ns)
Turn-off Delay Time(ns)
VCC=VBS=15V, CL=1nF
300
Max.
200
100
Typ.
0
-50
-25
0
25
50
75
100
400
300
Max.
200
Typ.
100
0
10
125
12
Temperature( C)
Figure 10a. Turn-Off Delay Time of LO vs Temperature
Turn-on Rise Time(ns)
Turn-On Rise Time(ns)
VCC=VBS=15V, CL=1nF
Max.
Typ.
0
-50
-25
0
25
50
75
100
150
Max.
100
Typ.
50
0
10
125
12
Figure 11a. Turn-On Rise Time of HO vs Temperature
16
18
20
Figure 11b. Turn-On Rise Time vs of HO VBS Supply Voltage
250
200
Turn-on Rise Time(ns)
VCC=VBS=15V, CL=1nF
Turn-On Rise Time(ns)
14
VBIAS Supply Voltage(V)
Temperature( C)
150
Max.
50
Typ.
0
-50
20
VCC=15V, CL=1nF, ta=25C
200
o
100
18
250
150
50
16
Figure 10b. Turn-Off Delay Time of LO vs VBS Supply Voltage
200
100
14
VBIAS Supply Voltage(V)
o
-25
0
25
50
75
100
Max.
100
Typ.
50
12
14
16
18
20
VBIAS Supply Voltage(V)
Temperature( C)
Figure 12a. Turn-On Rise Time of LO vs Temperature
FAN7080_GF085 Rev. 1.0.1
150
0
10
125
o
©2012 Fairchild Semiconductor Corporation
VCC=15V, CL=1nF, ta=25C
200
Figure 12b. Turn-On Rise Time of LO vs VBS Supply Voltage
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FAN7080_GF085 Half Bridge Gate Driver
500
Turn-Off Fall Time(ns)
Turn-Off Fall Time(ns)
VCC=VBS=15V, CL=1nF
100
Max.
50
VCC=15V, CL=1nF, ta=25C
200
150
100
Max.
50
Typ.
Typ.
0
-50
-25
0
25
50
75
100
0
10
125
12
Figure 13a. Turn-Off Fall Time of HO vs Temperature
16
18
20
Figure 13b. Turn-Off Fall Time of HO vs VBS Supply Voltage
250
150
Turn-Off Fall Time(ns)
VCC=VBS=15V, CL=1nF
Turn-Off Fall Time(ns)
14
VBIAS Supply Voltage(V)
o
Temperature( C)
100
Max.
50
VCC=15V, CL=1nF, ta=25C
200
150
100
Max.
50
Typ.
Typ.
0
-50
-25
0
25
50
75
100
0
10
125
12
14
16
18
20
VBIAS Supply Voltage(V)
o
Temperature( C)
Figure 14a. Turn-Off Fall Time of LO vs Temperature
Figure 14b. Turn-Off Fall Time of LO vs BS Supply Voltage
5
5
4
4
1
1
0
0
5
2
1
0
0
1
5
7
0
5
5
2
0
5
2
-
o
Temperature( C)
Figure 15a. Logic 0 Input Voltage vs Temperature
FAN7080_GF085 Rev. 1.0.1
Min.
0
5
-
5
2
1
0
0
1
5
7
0
5
5
2
0
5
2
-
0
5
-
o
Temperature( C)
©2012 Fairchild Semiconductor Corporation
Input Voltage(V)
2
2
Input Voltage(V)
3
3
Min.
Figure 15b. Logic 1 Input Voltage vs Temperature
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FAN7080_GF085 Half Bridge Gate Driver
250
150
High Level Output Voltage (V)
High Level Output Voltage(V)
VCC=VBS=15V
0.4
0.3
0.2
0.1
Max.
0.0
-50
-25
0
25
50
75
100
VCC=15V, ta=25C
0.4
0.3
0.2
Max.
0.1
0.0
10
125
12
Temperature( C)
Figure 16a. High Level Output of HO vs Temperature
High Level Output Voltage (V)
High Level Output Voltage(V)
0.4
0.3
0.2
Max.
0.0
-50
-25
0
25
50
75
100
VCC=15V, ta=25C
0.3
0.2
0.1
Max.
0.0
10
125
12
14
16
18
20
VCC Supply Voltage(V)
o
Figure 17a. High Level Output of LO vs Temperature
Figure 17b. High Level Output of LO vs VCC Supply Voltage
0.5
0.5
High Level Output Voltage (V)
VCC=VBS=15V
Low Level Output Voltage(V)
20
0.4
Temperature( C)
0.4
0.3
0.2
0.0
-50
18
0.5
VCC=VBS=15V
0.1
16
Figure 16b. High Level Output of HO vs VBS Supply Voltage
0.5
0.1
14
VBS Supply Voltage(V)
o
Max.
-25
0
25
50
75
100
Temperature( C)
0.3
0.2
0.1
Max.
12
14
16
18
20
VBS Supply Voltage(V)
Figure 18a. Low Level Output of HO vs Temperature
FAN7080_GF085 Rev. 1.0.1
0.4
0.0
10
125
o
©2012 Fairchild Semiconductor Corporation
VCC=15V, ta=25C
Figure 18b. Low Level Output of HO vs VBS Supply Voltage
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FAN7080_GF085 Half Bridge Gate Driver
0.5
0.5
0.5
VCC=15V, ta=25C
Low Level Output Voltage(V)
Low Level Output Voltage(V)
VCC=VBS=15V
0.4
0.3
0.2
0.1
Max.
0.0
-50
-25
0
25
50
75
100
0.4
0.3
0.2
Max.
0.1
0.0
10
125
12
Temperature( C)
Figure 19a. Low Level Output of LO vs Temperature
Offset Supply Leakage Current (uA)
Offset Supply Leakage Current(uA)
160
20
120
80
40
Max.
-25
0
25
50
75
100
VCC=15V, ta=25C
400
300
200
100
Max.
0
125
0
100
200
300
400
500
600
VB Boost Voltage (V)
o
Temperature( C)
Figure 20a. Offset Supply leakage Current vs Temperature
Figure 20b. Offset Supply leakage Current vs VB Boost Voltage
200
1200
VBS=15V
VCC=15V
1000
Max.
VCC Supply Current (uA)
VBS Supply Cureent (uA)
18
500
VB=VS=600V
150
100
Typ.
50
0
-50
16
Figure 19b. Low Level Output of LO vs VCC Supply Voltage
200
0
-50
14
VCC Supply Voltage(V)
o
-25
0
25
50
75
100
o
400
Typ.
200
-25
0
25
50
75
100
125
Temperature ( C)
Figure 21. VBS Supply Current vs Temperature
FAN7080_GF085 Rev. 1.0.1
600
o
Temperature ( C)
©2012 Fairchild Semiconductor Corporation
800
0
-50
125
Max.
Figure 22. VCC Supply Current vs Temperature
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FAN7080_GF085 Half Bridge Gate Driver
0.5
VIN=5V
70
Logic "1" Input Current(A)
Logic "0" Input Current (uA)
VIN=5V
60
50
Max.
40
30
20
Typ.
4
3
Max.
2
1
10
0
-50
-25
0
25
50
75
100
0
-50
125
-25
0
25
50
75
100
125
o
Temperature( C)
o
Temperature ( C)
Figure 23a. Logic 1 Input Current vs Temperature
Figure 23b. Logic 0 Input Current vs Temperature
6
8
6
VCC Supply Voltage (V)
VCC Supply Voltage (V)
7
max
5
4
Typ
3
2
-50
5
4
Typ
3
min
-25
0
25
50
75
100
2
-50
125
-25
0
o
25
50
75
100
125
o
Temperature ( C)
Temperature ( C)
Figure 24a. VCC UnderVoltage Threshold (+) vs Temperature
Figure 24b. VCC UnderVoltage Threshold(-) vs Temperature
8
6
6
VBS Supply Voltage (V)
VBS Supply Voltage (V)
7
max
5
4
Typ
3
2
-50
5
4
Typ
3
min
-25
0
25
50
75
100
2
-50
125
o
FAN7080_GF085 Rev. 1.0.1
0
25
50
75
100
125
Temperature ( C)
Figure 25a. VBS UnderVoltage Threshold (+) vs Temperature
©2012 Fairchild Semiconductor Corporation
-25
o
Temperature ( C)
Figure 25b.VBS UnderVoltage Threshold(-) vs Temperature
13
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FAN7080_GF085 Half Bridge Gate Driver
5
80
VCC=VBS=15V
Typ.
500
Output Sink Cureent (mA)
Output Source Current (mA)
VCC=VBS=15V
Typ.
400
300
Min.
200
100
0
-50
-25
0
25
50
75
100
800
Min.
600
400
200
0
-50
125
-25
0
o
Output Sink Cureent (mA)
Output Source Current (mA)
Typ.
Min.
200
100
-25
0
25
50
75
100
800
Min.
600
400
200
0
-50
125
Typ.
-25
0
o
25
50
75
100
125
o
Temperature ( C)
Temperature ( C)
Figure 27a. Output Source Current of LO vs Temperature
Figure 27b. Output Sink Current of LO vs Temperature
5
2.0
Shutdown threshold voltage (V)
logic 0 input current of SD/DT (uA)
125
VCC=VBS=15V
500
4
3
2
100
1000
VCC=VBS=15V
0
-50
75
Figure 26b. Output Sink Current of HO vs Temperature
600
300
50
Temperature ( C)
Figure 26a. Output Source Current of HO vs Temperature
400
25
o
Temperature ( C)
Max.
1
0
-50
-25
0
25
50
75
100
0.5
-25
0
25
50
75
100
125
o
Temperature( C)
Temperature ( C)
Figure 28. Logic 0 Input Current of SD/DT vs Temperature
FAN7080_GF085 Rev. 1.0.1
1.0
0.0
-50
125
o
©2012 Fairchild Semiconductor Corporation
1.5
Figure 29.Shutdown Threshold of vs Temperature
14
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FAN7080_GF085 Half Bridge Gate Driver
1000
600
VCC=VBS=15V, VDT=1.2V
Dead Time matching time (ns)
VCC=VBS=15V, VDT=1.2V
Dead Time(ns)
1200
900
Max.
600
Typ.
300
-50
-25
0
25
50
75
100
120
90
Max.
60
Typ.
30
0
-50
125
-25
0
o
Delay Matching of turn-off (ns)
Delay Matching of turn-on (ns)
120
Max.
90
60
Typ.
0
-50
125
-25
0
25
50
75
100
VCC=VBS=15V, VDT=1.2V
60
Max.
40
20
Typ.
0
-50
125
-25
0
o
-7
VS Offset Supply Voltage (V)
-6
450
400
350
300
250
200
Typ.
100
50
25
50
75
100
o
125
VCC=VBS=15V
-9
-10
-11
-12
Typ.
-13
-14
-25
0
25
50
75
100
125
o
Temp( C)
Figure 34. Shutdown Propagation Delay vs Temperature
FAN7080_GF085 Rev. 1.0.1
100
-8
-15
-50
125
Temperature( C)
©2012 Fairchild Semiconductor Corporation
75
Figure 33. Turn_Off Delay Matching vs Temperature
500
0
50
Temperature( C)
Figure 32. Turn-On Delay Matching vs Temperature
-25
25
o
Temperature( C)
Shutdown propagation delay (ns)
100
80
VCC=VBS=15V, VDT=1.2V
0
-50
75
Figure 31. Deadtime Matching Time vs Temperature
150
150
50
Temperature( C)
Figure 30. Deadtime vs Temperature
30
25
o
Temperature( C)
Figure35. Maximum VS Negtive Offset of vs Temperature
15
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FAN7080_GF085 Half Bridge Gate Driver
150
1500
5.00
4.80
A
0.65
3.81
8
5
6.20
5.80
PIN ONE
INDICATOR
B
1.75
4.00
3.80
1
5.60
4
1.27
(0.33)
0.25
M
C B A
1.27
LAND PATTERN RECOMMENDATION
0.25
0.10
SEE DETAIL A
1.75 MAX
R0.10
0.10
0.51
0.33
0.50 x 45°
0.25
C
OPTION A - BEVEL EDGE
GAGE PLANE
R0.10
8°
0°
0.90
0.406
0.25
0.19
C
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, 
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
©2012 Fairchild Semiconductor Corporation
FAN7080_GF085 Rev. 1.0.1
16
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FAN7080_GF085 Half Bridge Gate Driver
Package Dimensions
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Datasheet contains the design specifications for product development. Specifications may change
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Rev. I43
©2012 Fairchild Semiconductor Corporation
FAN7080_GF085 Rev. 1.0.1
17
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FAN7080_GF085 Half Bridge Gate Driver
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