E2G0015-17-41 ¡ Semiconductor MSM511666C/CL ¡ Semiconductor This version: Jan. 1998 MSM511666C/CL Previous version: May 1997 65,536-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO (BYTE WRITE) DESCRIPTION The MSM511666C/CL is a 65,536-word ¥ 16-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM511666C/CL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer metal CMOS process. The MSM511666C/CL is available in a 40-pin plastic SOJ or 44/40-pin plastic TSOP. The MSM511666CL (the low-power version) is specially designed for lower-power applications. FEATURES • 65,536-word ¥ 16-bit configuration • Single 5 V power supply, ±10% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 256 cycles/4 ms, 256 cycles/32 ms (L-version) • Byte write and fast page mode with EDO, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • Package options: 40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM511666C/CL-xxJS) 44/40-pin 400 mil plastic TSOP (TSOPII44/40-P-400-0.80-K) (Product : MSM511666C/CL-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) MSM511666C/CL-60 60 ns 30 ns 20 ns 20 ns 110 ns 550 mW 5.5 mW/ MSM511666C/CL-70 70 ns 35 ns 20 ns 20 ns 120 ns 495 mW 1.1 mW (L-version) 1/16 ¡ Semiconductor MSM511666C/CL PIN CONFIGURATION (TOP VIEW) VCC 1 40 VSS DQ1 2 39 DQ16 DQ2 3 38 DQ15 DQ3 4 37 DQ14 DQ4 5 36 DQ13 DQ5 6 35 DQ12 DQ6 7 34 DQ11 DQ7 8 33 DQ10 DQ8 9 32 DQ9 NC 10 31 NC VCC 11 30 VSS UWE 12 29 CAS LWE 13 28 OE RAS 14 27 NC A0 15 26 NC A1 16 25 NC A2 17 24 A7 A3 18 23 A6 A4 19 22 A5 VCC 20 21 VSS VCC DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 NC 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 NC VCC UWE LWE RAS A0 A1 A2 A3 A4 VCC 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 VSS CAS OE NC NC NC A7 A6 A5 VSS 44/40-Pin Plastic TSOP (K Type) 40-Pin Plastic SOJ Pin Name A0 - A7 RAS Row Address Strobe CAS Column Address Strobe DQ1 - DQ16 Data Input/Data Output OE LWE Note : Function Address Input Output Enable Lower Byte Write Enable UWE Upper Byte Write Enable VCC Power Supply (5 V) VSS Ground (0 V) NC No Connection The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/16 ¡ Semiconductor MSM511666C/CL BLOCK DIAGRAM Timing Generator RAS Timing Generator CAS Column Address Buffers 8 8 UWE LWE Write Clock Generator Column Decoders OE 16 Internal Address Counter A0 - A7 Refresh Control Clock Sense Amplifiers 16 I/O Selector Row Address Buffers Row Decoders 8 Word Drivers 16 16 16 16 8 Output Buffers Input Buffers DQ1 - DQ16 16 Memory Cells VCC On Chip VBB Generator VSS FUNCTION TABLE Input Pin DQ Pin Function Mode RAS CAS LWE UWE OE DQ1 - DQ8 DQ9 - DQ16 H * H * * * High-Z High-Z Standby L High-Z Refresh L L * L High-Z DOUT DOUT Word Read Lower Byte Write * H * H L L L H H DIN L L H L H Don't Care Don't Care DIN DIN Word Write High-Z — L L L L H DIN L L H H H High-Z Upper Byte Write *: "H" or "L" 3/16 ¡ Semiconductor MSM511666C/CL ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit VT –1.0 to 7.0 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C Voltage on Any Pin Relative to VSS *: Ta = 25°C Recommended Operating Conditions Parameter Power Supply Voltage (Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input High Voltage VIH 2.4 — 6.5 V Input Low Voltage VIL –1.0 — 0.8 V Capacitance Parameter Input Capacitance (A0 - A7) Input Capacitance (RAS, CAS, UWE, LWE, OE) Output Capacitance (DQ1 - DQ16) (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Symbol Typ. Max. Unit CIN1 — 7 pF CIN2 — 7 pF CI/O — 7 pF 4/16 ¡ Semiconductor MSM511666C/CL DC Characteristics Parameter (VCC = 5 V ±10%, Ta = 0°C to 70°C) Symbol Condition MSM511666 C/CL-60 MSM511666 C/CL-70 Min. Max. Min. Max. Unit Note Output High Voltage VOH IOH = –2.5 mA 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 2.1 mA 0 0.4 0 0.4 V –10 10 –10 10 mA –10 10 –10 10 mA — 100 — 90 mA 1, 2 — 2 — 2 — 1 — 1 — 200 — — 100 — 0 V £ VI £ 6.5 V; Input Leakage Current ILI All other pins not under test = 0 V Output Leakage Current ILO Average Power Supply Current ICC1 (Operating) 0 V £ VO £ 5.5 V RAS, CAS cycling, tRC = Min. RAS, CAS = VIH Power Supply Current (Standby) ICC2 RAS, CAS ≥ VCC –0.2 V mA 1 200 mA 1, 5 — 90 mA 1, 2 5 — 5 mA — 100 — 90 mA 1, 2 — 95 — 85 mA 1, 3 — 300 — 300 mA RAS cycling, Average Power ICC3 CAS = VIH, Supply Current (RAS-only Refresh) tRC = Min. RAS = VIH, Power Supply Current (Standby) ICC5 CAS = VIL, Supply Current ICC6 (CAS before RAS Refresh) 1 DQ = enable Average Power RAS cycling, CAS before RAS RAS = VIL, Average Power ICC7 CAS cycling, Supply Current (Fast Page Mode) tHPC = Min. tRC = 125 ms, Average Power ICC10 CAS before RAS, Supply Current (Battery Backup) Notes : 1. 2. 3. 4. 5. DQ disable tRAS £ 1 ms 1, 4, 5 ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V. L-version. 5/16 ¡ Semiconductor MSM511666C/CL AC Characteristics (1/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Random Read or Write Cycle Time Symbol MSM511666 C/CL-60 MSM511666 C/CL-70 Unit Note Min. Max. Min. Max. — ns ns ns tRC 110 — Read Modify Write Cycle Time tRWC — 120 170 Fast Page Mode Cycle Time tHPC 155 25 — 30 — — tHPRWC 65 — 70 — ns Access Time from RAS tRAC — 60 — 70 ns 4, 5, 6 Access Time from CAS tCAC — 20 — 20 ns 4, 5 Access Time from Column Address Access Time from CAS Precharge tAA tCPA — — 30 35 — — 35 40 ns ns 4, 6 4 Access Time from OE Output Low Impedance Time from CAS tOEA tCLZ — 0 20 — — 0 20 — ns ns 4 4 Data Output Hold After CAS Low Fast Page Mode Read Modify Write Cycle Time tDOH 5 — 5 — ns CAS to Data Output Buffer Turn-off Delay Time tCEZ 0 15 0 15 ns 7, 8 RAS to Data Output Buffer Turn-off Delay Time tREZ OE to Data Output Buffer Turn-off Delay Time tOEZ 0 15 0 15 ns 7, 8 0 15 0 15 ns 7 WE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period tWEZ tT tREF 0 1 — 15 50 4 0 1 — 15 50 4 ns ns ms 7 3 Refresh Period (L-version) tREF — 32 — 32 ms RAS Precharge Time tRP 40 — 40 — ns RAS Pulse Width tRAS 60 10,000 70 10,000 ns RAS Pulse Width (Fast Page Mode with EDO) tRASP 60 100,000 70 100,000 ns RAS Hold Time tRSH 20 tROH 15 — — 20 15 — — ns RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode with EDO) tCP 10 — 10 — ns CAS Pulse Width tCAS 10 10,000 10 10,000 ns CAS Hold Time tCSH — — 55 5 — — ns ns ns CAS to RAS Precharge Time tCRP 50 5 RAS Hold Time from CAS Precharge tRHCP 35 — 40 — ns OE Hold Time from CAS (DQ Disable) tCHO RAS to CAS Delay Time tRCD 5 20 — 40 5 20 — 50 ns ns 5 RAS to Column Address Delay Time tRAD 15 30 15 35 ns 6 RAS to Second CAS Delay Time tRSCD 60 — 70 — ns Row Address Set-up Time tASR 0 — 0 — ns Row Address Hold Time tRAH 10 — 10 — ns Column Address Set-up Time tASC 0 — 0 — ns Column Address Hold Time tCAH 10 — 10 — ns Column Address Hold Time from RAS tAR tRAL 45 30 — — 55 35 — — ns ns Column Address to RAS Lead Time 6/16 ¡ Semiconductor MSM511666C/CL AC Characteristics (2/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Symbol MSM511666 C/CL-60 MSM511666 C/CL-70 Min. Max. Min. Max. Unit Note Read Command Set-up Time tRCS 0 — 0 — ns Read Command Hold Time tRCH 0 — 0 — ns Read Command Hold Time referenced to RAS Write Command Set-up Time tRRH tWCS 0 — 0 — ns 9 0 — 0 — ns 10 Write Command Hold Time Write Command Hold Time from RAS tWCH tWCR 10 40 — — 10 45 — — ns ns Write Command Pulse Width tWP 10 — 10 — ns WE Pulse Width (DQ Disable) OE Command Hold Time OE Precharge Time tWPE tOEH tOEP 7 10 10 — — — 7 10 10 — — — ns ns ns OE Command Hold Time tOCH 10 — 10 — ns Write Command to RAS Lead Time Write Command to CAS Lead Time tRWL tCWL 20 20 — — 20 20 — — ns ns Data-in Set-up Time Data-in Hold Time Data-in Hold Time from RAS OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time tDS tDH tDHR tOED tCWD tAWD tRWD 0 — 0 — ns 10 40 15 40 50 80 — — — — — — 10 45 15 45 60 95 — — — — — — ns ns ns ns ns ns CAS Precharge WE Delay Time tCPWD 55 — 65 — ns CAS Active Delay Time from RAS Precharge tRPC 0 — 0 — ns RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) tCSR tCHR 5 10 — — 5 10 — — ns ns 9 11 11 10 10 10 10 7/16 ¡ Semiconductor Notes: MSM511666C/CL 1. A start-up delay of 100 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 50 pF. The output timing reference levels are VOH = 2.0 V (IOH = –2 mA) and VOL = 0.8 V (IOL = 2 mA). 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 8/16 E2G0095-17-41H , ,, , , ,,,, ,, ¡ Semiconductor MSM511666C/CL TIMING WAVEFORM Read Cycle tRC tRP tRAS RAS VIH – VIL – tAR tCRP tCSH tCRP tRCD VIH – CAS VIL – tRAD tASR Address VIH – VIL – tRSH tCAS tRAH tASC tRAL tCAH Column Row tRCS WE OE VIH – VIL – tAA tROH tREZ tOEA VIH – VIL – tCAC tRAC DQ VOH – tOEZ Open VOL – tRCH tRRH tCEZ Valid Data-out tCLZ "H" or "L" Write Cycle (Early Write) tRC tRP tRAS RAS VIH – VIL – tAR tCRP VIH – CAS VIL – VIH – VIL – tCSH tRCD tRSH tCAS tRAD tRAH tASR Address tCRP tASC Row tCAH Column tWCS WE tRAL VIH – VIL – tWCH tWP tCWL tWCR tRWL VIH – OE VIL – tDS DQ VIH – VIL – tDHR tDH Valid Data-in Open "H" or "L" 9/16 , ,, ¡ Semiconductor MSM511666C/CL Read Modify Write Cycle tRWC tRAS RAS VIH – VIL – tRP tAR tCRP tCSH tCRP tRCD tRSH tCAS VIH – CAS VIL – tASR VIH – Address VIL – WE VIH – VIL – OE VIH – VIL – tRAH tASC tCAH Column Row tRAD tRWD tAA tAWD tRCS tOEA tOED tCAC tRAC DQ VI/OH– VI/OL– tCWL tRWL tWP tCWD tCLZ tOEZ Valid Data-out tOEH tDS tDH Valid Data-in "H" or "L" 10/16 ,,,, , , ¡ Semiconductor MSM511666C/CL Fast Page Mode Read Cycle (Part-1) tRASP RAS VIH – VIL – tAR tCRP CAS VIH VIL WE tRHCP tHPC tRCD tCP tCP tCAS – – tCAS tCAS tRAD tASR Address tRP tRSCD VIH – VIL – tASC tRAH Row tCSH tCAH tASC Column tASC tCAH Column Column tRCS tRRH VIH – VIL – tCHO DQ tOCH tRAC tAA OE tCAH tOEP tCPA tOEA tCAC VOH – VOL – tCLZ tOEZ tCAC Valid Data-out Valid Data-out tOEA tOEA tCAC tDOH tOEP tAA tAA VIH – VIL – tOEZ Valid* Data-out * : Same Data, tREZ Valid* Data-out "H" or "L" Fast Page Mode Read Cycle (Part-2) tRASP RAS VIH – VIL – tAR WE OE DQ VIH – VIL – VIH – VIL – tRCD tCP tCAS tCAS tRAD tRAH tCSH tASC tCAH Row tASC Column tCAH Column tRCS tASC tCAH Column tRCS tRAC tAA VIH – VIL – VOH – VOL – tCRP tCP tCAS VIH – VIL – tASR Address tRHCP tHPC tCRP CAS tRP tRSCD tRCH tWPE tAA tAA tCPA tOEA tCAC tCLZ tWEZ Valid Data-out tCAC tDOH tCAC Valid Data-out tCEZ Valid Data-out "H" or "L" 11/16 ,,, , , ¡ Semiconductor MSM511666C/CL Fast Page Mode Write Cycle (Early Write) tRP tRASP tRSCD RAS VIH – VIL – tAR CAS tRAD tRAH tASR Address WE VIH – VIL – OE VIH – VIL – tASC Column tWCS DQ tCP tCAS tCSH tASC tCAH Row tDHR tHPC tCP tCAS VIH – VIL – VIH – VIL – tHPC tRCD tCRP VIH – VIL – tCAH tWCS tDH Valid Data-in Column tWCH tDS tRSH tCAH tASC Column tWCH tDS tCAS tDH Valid Data-in tWCS tWCH tDS tDH Valid Data-in "H" or "L" Fast Page Mode Read Modify Write Cycle tRASP tRSCD RAS tRWD VIH – VIL – tAR tCRP CAS VIH – VIL – VIH – VIL – tCWD tRAD tASR Address tCP tRCD Row tCWL tCAH tRCS tAWD VIH – VIL – tAWD tDS tWP VIH – VIL – tCAC VI/OH – VI/OL – tOED tOEZ Valid Data-out tCLZ tRWL tCWD tRAC tOEA DQ tCPA tCAH Column tAA OE tASC Column tRCS WE tCPWD tHPRWC tRAH tASC tAA tOEH tDS tOED tOEA tCAC tDH Valid Data-in tOEZ Valid Data-out tCLZ tWP tOEH tDH Valid Data-in "H" or "L" 12/16 , ¡ Semiconductor MSM511666C/CL RAS-Only Refresh Cycle tRC RAS CAS Address VIL – VIH – VIL – tRP tRAS VIH – tCRP tRPC tASR VIH – tRAH Row VIL – tCEZ DQ VOH – Open VOL – Note: WE, OE = "H" or "L" "H" or "L" CAS before RAS Refresh Cycle tRC tRP RAS VIH – VIL – DQ VIH – VIL – VOH – VOL – tRP tRPC tRPC tCP CAS tRAS tCSR tCHR tCEZ Open Note: WE, OE, Address = "H" or "L" 13/16 , ,, ,, , ,, ¡ Semiconductor MSM511666C/CL Hidden Refresh Read Cycle tRC tRAS RAS CAS VIH – VIL – tCRP VIH – VIL – WE OE VIH – VIL – tRSH tRCD tRAD tASC Row Column tRCS tRRH tRAL VIH – VIL – tAA tROH tOEA VIH – VIL – VOH – VOL – tCHR tCAH tRAH tCEZ tCAC tCLZ tRAC DQ tRP tAR tASR Address tRC tRAS tRP tOEZ Open tREZ Valid Data-out "H" or "L" Hidden Refresh Write Cycle tRC tRAS RAS CAS Address VIH – VIL – VIH – VIL – VIH – VIL – VIH – VIL – OE VIH – VIL – DQ VIH – VIL – tRP tAR tCRP tASR tRCD tRSH tRAD tASC tCAH tRAH tCHR tRAL Column Row tRWL tWCH tWCS WE tRC tRAS tRP tWP tWCR tDS tDH Valid Data-in tDHR "H" or "L" 14/16 ¡ Semiconductor MSM511666C/CL PACKAGE DIMENSIONS (Unit : mm) SOJ40-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.70 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/16 ¡ Semiconductor MSM511666C/CL (Unit : mm) TSOPII44/40-P-400-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.49 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/16