ONSEMI Z0107MNT1G

Z0103MN, Z0107MN,
Z0109MN
Sensitive Gate Triac Series
Silicon Bidirectional Thyristors
Designed for use in solid state relays, MPU interface, TTL logic and
other light industrial or consumer applications. Supplied in surface
mount package for use in automated manufacturing.
http://onsemi.com
TRIAC
1.0 AMPERE RMS
600 VOLTS
Features
•
•
•
•
•
Sensitive Gate Trigger Current in Four Trigger Modes
Blocking Voltage to 600 V
Glass Passivated Surface for Reliability and Uniformity
Surface Mount Package
These are Pb−Free Devices
MT2
MT1
G
MARKING
DIAGRAM
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Peak Repetitive Off−State Voltage (Note 1)
(Sine Wave, 50 to 60 Hz, Gate Open,
TJ = −40 to +125°C)
VDRM,
VRRM
600
V
On−State Current RMS (TC = 80°C)
(Full Sine Wave 50 to 60 Hz)
IT(RMS)
1.0
A
ITSM
8.0
A
I2t
0.4
A2s
Average Gate Power (TC = 80°C, t v 8.3 ms)
PG(AV)
1.0
W
Peak Gate Current (t v 20 ms, TJ = +125°C)
IGM
1.0
A
Operating Junction Temperature Range
TJ
−40 to
+125
°C
Storage Temperature Range
Tstg
−40 to
+150
°C
Peak Non−repetitive Surge Current (One Full
Cycle Sine Wave, 60 Hz, TC = 25°C)
Circuit Fusing Considerations
(Pulse Width = 8.3 ms)
SOT−223
CASE 318E
STYLE 11
AYW
10XMN G
G
1
2
3
A
Y
W
10XMN
= Assembly Location
= Year
= Work Week
= Device Code
x = 3, 7, 9
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. VDRM and VRRM for all types can be applied on a continuous basis. Blocking
voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
THERMAL CHARACTERISTICS
1
Main Terminal 1
2
Main Terminal 2
3
Gate
4
Main Terminal 2
ORDERING INFORMATION
Package
Shipping†
Z0103MNT1G
SOT−223
(Pb−Free)
1000/Tape & Reel
°C/W
Z0107MNT1G
SOT−223
(Pb−Free)
1000/Tape & Reel
°C
Z0109MNT1G
SOT−223
(Pb−Free)
1000/Tape & Reel
Characteristic
Symbol
Max
Unit
Thermal Resistance, Junction−to−Ambient PCB
Mounted per Figure 1
RqJA
156
°C/W
Thermal Resistance, Junction−to−Tab Measured on MT2 Tab Adjacent to Epoxy
RqJT
25
TL
260
Maximum Device Temperature for
Soldering Purposes for 10 Secs Maximum
4
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2009
June, 2009 − Rev. 3
1
Publication Order Number:
Z0103MN/D
Z0103MN, Z0107MN, Z0109MN
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted; Electricals apply in both directions)
Characteristic
Symbol
Min
Typ
Max
Unit
IDRM, IRRM
−
−
−
−
5.0
500
mA
mA
VTM
−
−
1.56
V
OFF CHARACTERISTICS
Peak Repetitive Blocking Current
(VD = Rated VDRM, VRRM; Gate Open)
TJ = 25°C
TJ = +125°C
ON CHARACTERISTICS
Peak On−State Voltage
(ITM = "1.4 A Peak; Pulse Width v 2.0 ms, Duty Cycle v 2.0%)
Gate Trigger Current (Continuous dc)
(VD = 12 Vdc, RL = 30 Ohms)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
MT2(−), G(+)
Z0103MN
Gate Trigger Current (Continuous dc)
(VD = 12 Vdc, RL = 30 Ohms)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
MT2(−), G(+)
Z0107MN
Gate Trigger Current (Continuous dc)
(VD = 12 Vdc, RL = 30 Ohms)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
MT2(−), G(+)
Z0109MN
Latching Current (VD = 12 V, IG = 1.2 x IGT)
MT2(+), G(+) All Types
MT2(+), G(−) All Types
MT2(−), G(−) All Types
MT2(−), G(+) All Types
Z0103MN
Latching Current (VD = 12 V, IG = 1.2 x IGT)
MT2(+), G(+) All Types
MT2(+), G(−) All Types
MT2(−), G(−) All Types
MT2(−), G(+) All Types
Z0107MN
Latching Current (VD = 12 V, IG = 1.2 x IGT)
MT2(+), G(+) All Types
MT2(+), G(−) All Types
MT2(−), G(−) All Types
MT2(−), G(+) All Types
Z0109MN
IGT
mA
0.15
0.15
0.15
0.25
−
−
−
−
3.0
3.0
3.0
5.0
IGT
mA
0.15
0.15
0.15
0.25
−
−
−
−
5.0
5.0
5.0
7.0
IGT
IL
IL
IL
mA
0.15
0.15
0.15
0.25
−
−
−
−
10
10
10
10
−
−
−
−
−
−
−
−
7.0
15
7.0
7.0
−
−
−
−
−
−
−
−
10
20
10
10
−
−
−
−
−
−
−
−
15
25
15
15
mA
mA
mA
Gate Trigger Voltage (Continuous dc) (VD = 12 Vdc, RL = 30 Ohms)
VGT
−
−
1.3
V
Gate Non−Trigger Voltage (VD = 12 V, RL = 30 Ohms, TJ = 125°C)
All Four Quadrants
VGD
0.2
−
−
V
IH
−
−
−
−
7.0
10
mA
di/dt(c)
1.6
−
−
A/ms
10
20
50
30
60
75
−
−
−
−
−
20
Holding Current
(VD = 12 Vdc, Initiating Current = 50 mA, Gate Open)
(Z0103MA)
(Z0107MA, Z0109MA)
DYNAMIC CHARACTERISTICS
Rate of Change of Commutating Current
(VD = 400 V, ITM = 0.84 A, Commutating dv/dt = 1.5 V/ms, Gate Open,
TJ = 110°C, f = 250 Hz, with Snubber)
Critical Rate of Rise of Off−State Voltage (VD = 67% Rated VDRM, Exponential
Waveform, Gate Open, TJ = 110°C)
Z0103MN
Z0107MN
Z0109MN
dv/dt
Repetitive Critical Rate of Rise of On−State Current, TJ = 125°C
Pulse Width = 20 ms, IPKmax = 15 A, diG/dt = 1 A/ms, f = 60 Hz
di/dt
http://onsemi.com
2
V/ms
A/ms
Z0103MN, Z0107MN, Z0109MN
Voltage Current Characteristic of Triacs
(Bidirectional Device)
+ Current
Symbol
Parameter
VTM
VDRM
Peak Repetitive Forward Off State Voltage
IDRM
Peak Forward Blocking Current
VRRM
Peak Repetitive Reverse Off State Voltage
IRRM
Peak Reverse Blocking Current
VTM
Maximum On State Voltage
IH
Holding Current
on state
IRRM at VRRM
IH
Quadrant 3
MainTerminal 2 −
IH
off state
VTM
Quadrant Definitions for a Triac
MT2 POSITIVE
(Positive Half Cycle)
+
(+) MT2
Quadrant II
(+) MT2
(−) IGT
GATE
Quadrant I
(+) IGT
GATE
MT1
MT1
REF
REF
IGT −
+ IGT
(−) MT2
Quadrant III
(−) MT2
Quadrant IV
(+) IGT
GATE
(−) IGT
GATE
MT1
MT1
REF
REF
−
MT2 NEGATIVE
(Negative Half Cycle)
All polarities are referenced to MT1.
With in−phase signals (using standard AC lines) quadrants I and III are used.
http://onsemi.com
3
Quadrant 1
MainTerminal 2 +
+ Voltage
IDRM at VDRM
Z0103MN, Z0107MN, Z0109MN
0.15
3.8
0.079
2.0
0.091
2.3
0.091
2.3
0.244
6.2
0.079
2.0
0.984
25.0
0.059
1.5
0.096
2.44
0.059
1.5
0.059
1.5
0.096
2.44
0.059
1.5
inches
mm
BOARD MOUNTED VERTICALLY IN CINCH 8840 EDGE CONNECTOR.
BOARD THICKNESS = 65 MIL., FOIL THICKNESS = 2.5 MIL.
MATERIAL: G10 FIBERGLASS BASE EPOXY
0.096
2.44
0.059
1.5
0.472
12.0
Figure 1. PCB for Thermal Impedance and Power Testing of SOT-223
http://onsemi.com
4
10
Rθ JA , JUNCTION TO AMBIENT THERMAL
RESISTANCE, ° C/W
IT, INSTANTANEOUS ON‐STATE CURRENT (AMPS)
Z0103MN, Z0107MN, Z0109MN
1.0
0.1
TYPICAL AT TJ = 110°C
MAX AT TJ = 110°C
MAX AT TJ = 25°C
0.01
0
1.0
2.0
3.0
4.0
vT, INSTANTANEOUS ON‐STATE VOLTAGE (VOLTS)
5.0
160
150
140
130
120
110
100
90
80
70
60
50
40
30
DEVICE MOUNTED ON
FIGURE 1 AREA = L2
T A , MAXIMUM ALLOWABLE AMBIENT TEMPERATURE ( °C)
L
4
PCB WITH TAB AREA
AS SHOWN
1 2 3
MINIMUM
FOOTPRINT = 0.076 cm2
0
2.0
Figure 2. On-State Characteristics
4.0
6.0
FOIL AREA (cm2)
8.0
10
Figure 3. Junction to Ambient Thermal
Resistance versus Copper Tab Area
110
110
α
30°
90
100
α
60°
90°
80
T A , MAXIMUM ALLOWABLE
AMBIENT TEMPERATURE ( °C)
100
α = CONDUCTION
ANGLE
dc
70
α = 180°
60
120°
50
MINIMUM FOOTPRINT
50 OR 60 Hz
40
α = 180°
60
120°
1.0 cm2 FOIL AREA
50
20
α
50 OR 60 Hz
40
30
0.5
dc
70
20
0.4
0.1
0.2
0.3
IT(RMS), RMS ON‐STATE CURRENT (AMPS)
60°
90°
80
30
0
30°
90
α
α = CONDUCTION
ANGLE
0
0.1
Figure 4. Current Derating, Minimum Pad Size
Reference: Ambient Temperature
0.2
0.3
0.4
0.5
0.6
IT(RMS), RMS ON‐STATE CURRENT (AMPS)
0.7
Figure 5. Current Derating, 1.0 cm Square Pad
Reference: Ambient Temperature
110
110
α
100
30°
60°
90
dc
30°
α
105
α = CONDUCTION
90°
60°
dc
100
ANGLE
α = 180°
120°
80
T(tab) , MAXIMUM ALLOWABLE
TAB TEMPERATURE ( °C)
T A , MAXIMUM ALLOWABLE AMBIENT TEMPERATURE ( °C)
L
TYPICAL
MAXIMUM
70
4.0 cm2 FOIL AREA
60
α = 180°
95
90°
120°
90
REFERENCE:
FIGURE 1
85
α
α
α = CONDUCTION
50
0
0.1
0.2
0.3
0.4
0.5
0.6
IT(RMS), RMS ON‐STATE CURRENT (AMPS)
0.7
80
0.8
ANGLE
0
Figure 6. Current Derating, 2.0 cm Square Pad
Reference: Ambient Temperature
0.1
0.2
0.3
0.4
0.5
0.6
IT(RMS), ON‐STATE CURRENT (AMPS)
Figure 7. Current Derating
Reference: MT2 Tab
http://onsemi.com
5
0.7
0.8
Z0103MN, Z0107MN, Z0109MN
1.0
1.0
α
α
r(t), TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
P(AV) , MAXIMUM AVERAGE
POWER DISSIPATION (WATTS)
0.9
0.8
α = CONDUCTION
0.7
ANGLE
0.6
120°
0.5
30°
0.4
α = 180°
0.3
60°
dc
90°
0.2
0.1
0.1
0
0
0.1
0.2
0.3
0.4
0.5
0.6
IT(RMS), RMS ON‐STATE CURRENT (AMPS)
0.7
0.01
0.0001
0.8
0.001
Figure 8. Power Dissipation
0.01
0.1
1.0
t, TIME (SECONDS)
LL
1N4007
TRIGGER CONTROL
MEASURE
I
CHARGE
100
Figure 9. Thermal Response, Device
Mounted on Figure 1 Printed Circuit Board
200 VRMS
ADJUST FOR
ITM, 60 Hz VAC
TRIGGER
10
CHARGE
CONTROL
NON‐POLAR
CL
RS
ADJUST FOR +
dv/dt(c)
CS
MT2
1N914 51 W
200 V
MT1
G
Note: Component values are for verification of rated (dv/dt)c. See AN1048 for additional information.
Figure 10. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Voltage (dv/dt)c
10
10
60 Hz
60°
80°
180 Hz
COMMUTATING dv/dt
dv/dt c , (V/ μ S)
COMMUTATING dv/dt
dv/dt c , (V/ μ S)
400 Hz
110°
ITM
100°
tw
f=
1.0
1.0
VDRM
1
2 tw
6fI
TM
(dińdt) c + 1000
1.0
60
10
300 Hz
VDRM = 200 V
70
80
90
100
di/dtc, RATE OF CHANGE OF COMMUTATING CURRENT (A/mS)
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Typical Commutating dv/dt versus
Current Crossing Rate and Junction Temperature
Figure 12. Typical Commutating dv/dt versus
Junction Temperature at 0.8 Amps RMS
http://onsemi.com
6
110
Z0103MN, Z0107MN, Z0109MN
60
10
STATIC dv/dt (V/ μs)
50
I GT , GATE TRIGGER CURRENT (mA)
600 Vpk
TJ = 110°C
MAIN TERMINAL #2
POSITIVE
40
30
MAIN TERMINAL #1
POSITIVE
20
10
100
1000
RG, GATE - MAIN TERMINAL 1 RESISTANCE (OHMS)
IGT2
IGT4
IGT1
1.0
0.1
-40
10,000
Figure 13. Exponential Static dv/dt versus
Gate − Main Terminal 1 Resistance
40
60
0
20
TJ, JUNCTION TEMPERATURE (°C)
80
100
1.1
VGT , GATE TRIGGER VOLTAGE (VOLTS)
IH , HOLDING CURRENT (mA)
-20
Figure 14. Typical Gate Trigger Current Variation
6.0
5.0
4.0
MAIN TERMINAL #2
POSITIVE
3.0
2.0
MAIN TERMINAL #1
POSITIVE
1.0
0
-40
IGT3
-20
0
20
40
60
80
0.3
-40
100
TJ, JUNCTION TEMPERATURE (°C)
VGT3
VGT4
VGT2
VGT1
-20
0
20
40
60
80
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. Typical Holding Current Variation
Figure 16. Gate Trigger Voltage Variation
http://onsemi.com
7
100
Z0103MN, Z0107MN, Z0109MN
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE L
D
b1
DIM
A
A1
b
b1
c
D
E
e
e1
L1
HE
4
HE
E
1
2
3
b
e1
e
q
C
q
A
0.08 (0003)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
A1
L1
MIN
1.50
0.02
0.60
2.90
0.24
6.30
3.30
2.20
0.85
1.50
6.70
0°
MILLIMETERS
NOM
MAX
1.63
1.75
0.06
0.10
0.75
0.89
3.06
3.20
0.29
0.35
6.50
6.70
3.50
3.70
2.30
2.40
0.94
1.05
1.75
2.00
7.00
7.30
10°
−
MIN
0.060
0.001
0.024
0.115
0.009
0.249
0.130
0.087
0.033
0.060
0.264
0°
INCHES
NOM
0.064
0.002
0.030
0.121
0.012
0.256
0.138
0.091
0.037
0.069
0.276
−
MAX
0.068
0.004
0.035
0.126
0.014
0.263
0.145
0.094
0.041
0.078
0.287
10°
STYLE 11:
PIN 1. MT 1
2. MT 2
3. GATE
4. MT 2
SOLDERING FOOTPRINT*
3.8
0.15
2.0
0.079
2.3
0.091
2.3
0.091
6.3
0.248
2.0
0.079
1.5
0.059
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderl[email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
8
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
Z0103MN/D