SG6741 Highly Integrated Green-Mode PWM Controller Features Description The highly integrated SG6741 PWM controller provides several features to enhance the performance of flyback converters. High-Voltage Startup Low Operating Current: 4mA Linearly Decreasing PWM Frequency to 22kHz Frequency Hopping to Reduce EMI Emission Peak-Current-Mode Control Cycle-by-Cycle Current Limiting Leading-Edge Blanking Synchronized Slope Compensation Gate Output Maximum Voltage Clamp: 18V VDD Over-Voltage Protection (Auto Restart) VDD Under-Voltage Lockout (UVLO) Internal Open-Loop Protection Constant Power Limit (Full AC Input Range) Applications General-purpose switch-mode power supplies and flyback power converters, including: Power Adapters Open-Frame SMPS The highly integrated SG6741 series of PWM controllers provides several features to enhance the performance of flyback converters. To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to linearly decrease the switching frequency at light-load conditions. To avoid acoustic-noise problems, the minimum PWM frequency is set above 22KHz. This green-mode function enables the power supply to meet international power conservation requirements. With the internal high-voltage startup circuitry, the power loss due to bleeding resistors is also eliminated. To further reduce power consumption, SG6741 is manufactured using the BiCMOS process, which allows an operating current of only 4mA. SG6741 — Highly Integrated Green-Mode PWM Controller October 2008 SG6741 integrates a frequency-hopping function that helps reduce EMI emission of a power supply with minimum line filters. Its built-in synchronized slope compensation achieves stable peak-current-mode control. The proprietary internal line compensation ensures constant output power limit over a wide range of AC input voltages, from 90VAC to 264VAC. SG6741 provides many protection functions. In addition to cycle-by-cycle current limiting, the internal open-loop protection circuit ensures safety when an open-loop or output short-circuit failure occurs. PWM output is disabled until VDD drops below the UVLO lower limit; then the controller starts again. As long as VDD exceeds about 26V, the internal OVP circuit is triggered. SG6741 is available in an 8-pin SOP package. Ordering Information Part Number Operating Temperature Range Package SG6741SZ -40 to +105°C 8-Lead Small Outline Package (SOP) Green Tape & Reel SG6741SY -40 to +105°C 8-Lead Small Outline Package (SOP) Green Tape & Reel Eco Status Packing Method For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2008 Fairchild Semiconductor Corporation SG6741 • Rev. 1.3.3 www.fairchildsemi.com 1 Figure 1. Typical Application Internal Block Diagram SG6741 — Highly Integrated Green-Mode PWM Controller Application Diagram Figure 2. Functional Block Diagram © 2008 Fairchild Semiconductor Corporation SG6741 • Rev. 1.3.3 www.fairchildsemi.com 2 SG6741 — Highly Integrated Green-Mode PWM Controller Marking Information T: S = SOP P: Z =Lead Free Null=regular package XXXXXXXX: Wafer Lot Y: Year; WW: Week V: Assembly Location SG6741TP XXXXXXXXYWWV Marking for SG6741SZ F: Fairchild logo Z: Plant code X: 1 digit year code Y: 1 digit week code TT: 2 digits die run code T: Package type (S = SOP) P: Y=Green package M: Manufacture flow code ZXYTT 6741 TPM Marking for SG6741SY Figure 3. Top Mark Pin Configuration GND GATE FB VDD NC SENSE HV RI Figure 4. Pin Configuration (Top View) Pin Definitions Pin # Name Description 1 GND 2 FB The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is determined in response to the signal on this pin and the current-sense signal on the SENSE pin. 3 NC No connection. 4 HV For startup, this pin is pulled high to the line input or bulk capacitor via resistors. 5 RI A resistor connected from the RI pin to GND pin provides the SG6741 with a constant current source. This determines the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26KΩ resistor (RI) results in a 65kHz center PWM frequency. 6 SENSE Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle current limiting. 7 VDD Power supply. The internal protection circuit disables PWM output as long as VDD exceeds the OVP trigger point. 8 GATE Ground. The totem-pole output driver. Soft driving waveform is implemented for improved EMI. © 2008 Fairchild Semiconductor Corporation SG6741 • Rev. 1.3.3 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are given with respect to the ground pin. Symbol Parameter Min. Max. Unit (1, 2) VVDD DC Supply Voltage 30 V VFB FB Pin Input Voltage -0.3 7.0 V SENSE Pin Input Voltage -0.3 7.0 V -0.3 VSENSE VRI RI Pin Input Voltage 7.0 V VHV HV Pin Input Voltage 500 V PD Power Dissipation (TA＜50°C) 400 mW Thermal Resistance (Junction-to-Air) 141 °C/W θ JA TJ TSTG TL ESD Operating Junction Temperature -40 +125 °C Storage Temperature Range -55 +150 °C +260 °C Lead Temperature (Wave Soldering or IR, 10 Seconds) Electrostatic Discharge Capability, Human Body Model, JESD22-A114 All Pins Except HV Pin 4 kV Electrostatic Discharge Capability, Machine Model, JESD22-A115 All Pins Except HV Pin 200 V Notes: 1. All voltage values, except differential voltages, are given with respect to the network ground terminal. 2. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. © 2008 Fairchild Semiconductor Corporation SG6741 • Rev. 1.3.3 SG6741 — Highly Integrated Green-Mode PWM Controller Absolute Maximum Ratings www.fairchildsemi.com 4 VDD=15V, TA=25°C, unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units 22 V V VDD Section VOP VDD-ON VDD-OFF Continuously Operating Voltage Start Threshold Voltage Minimum Operating Voltage IDD-ST Startup Current VDD-ON – 0.16V IDD-OP Operating Supply Current VDD=15V, GATE Open VDD-OLP +0.1V 15.5 16.5 17.5 9.5 10.5 11.5 V 30 µA 5 mA 4 IDD-OLP Internal Sink Current 50 70 90 µA VTH-OLP IDD-OLP off Voltage 6.5 7.5 8.0 V VDD-OVP VDD Over-Voltage Protection 25 26 27 V tD-VDDOVP VDD Over-Voltage Protection Debounce Time 100 180 260 µs HV Section IHV IHV-LC Supply Current from HV Pin VAC=90V (VDC=120V), VDD=10µF Leakage Current After Startup HV=500V, VDD=VDDOFF+1V mA 2.0 1 20 62 65 68 ±3.7 ±4.2 ±4.7 µA Oscillator Section fOSC Frequency in Nominal Mode tHOP Hopping Period fOSC-G Center Frequency Hopping Range 4.4 Green-Mode Frequency 16 18 KHz SG6741 — Highly Integrated Green-Mode PWM Controller Electrical Characteristics ms 21 KHz fDV Frequency Variation vs. VDD Deviation VDD=11V to 22V 5 % fDT Frequency Variation vs. Temperature Deviation TA=-40 to 105°C 5 % Continued on the following page… PWM Frequency fOSC fOSC-G VFB-ZDC VFB-G VFB-N VFB Figure 5. VFB vs. PWM Frequency © 2008 Fairchild Semiconductor Corporation SG6741 • Rev. 1.3.3 www.fairchildsemi.com 5 VDD=15V, TA=25°C, unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units 1/3.75 1/3.20 1/2.75 V/V 7 kΩ 4.3 V Feedback Input Section AV Input Voltage to Current-Sense Attenuation ZFB Input Impedance VFB-OPEN Output High Voltage VFB-OLP FB Open-Loop Trigger Level tD-OLP Delay Time of FB Pin Open-Loop Protection VFB-N Green-Mode Entry FB Voltage VFB-G Green-Mode Ending FB Voltage VFB-ZDC 4 FB Pin Open 5.5 3.7 RI=26kΩ 50 56 62 ms 1.9 2.1 2.3 V VFB-G 0.25 Zero Duty-Cycle Input Voltage V 4.0 VFB-N0.5 V VFB-G - VFB-G 0.20 0.10 V Current-Sense Section ZSENSE Input Impedance VSTHFL Current Limit Flatten Threshold Voltage VSTHVA Current Limit Valley Threshold Voltage tPD tLEB 12 VSTHFL–VSTHVA 0.90 0.93 0.30 0.34 0.38 V 100 200 ns 350 425 ns Delay to Output Leading-Edge Blanking Time KΩ 0.87 275 V VS-SCP Threshold Voltage for SENSE Short-Circuit Protection 0.15 V tD-SSCP Delay Time for SENSE Short-Circuit Protection 180 µs VSENSE<0.15V, RI=26kΩ SG6741 — Highly Integrated Green-Mode PWM Controller Electrical Characteristics (Continued) GATE Section DCYMAX Maximum Duty Cycle VGATE-L Gate Low Voltage VDD=15V, IO=50mA VGATE-H Gate High Voltage VDD=12.5V, IO=50mA tr Gate Rising Time VDD=15V, CL=1nF 150 250 350 ns tf Gate Falling Time VDD=15V, CL=1nF 30 50 90 ns Gate Source Current VDD=15V, GATE=6V 250 Gate Output Clamping Voltage VDD=22V IGATESOURCE VGATECLAMP 70 75 80 % 1.5 V 8 V mA 18 V Notes: 3. When activated, the output is disabled and the latch is turned off. 4. The threshold temperature for enabling the output again and resetting the latch after OTP has been activated. © 2008 Fairchild Semiconductor Corporation SG6741 • Rev. 1.3.3 www.fairchildsemi.com 6 5.0 20 4.0 IDD-OP (mA) IDD-ST (µA) Operating Supply Current (IDD-OP) vs Temperature 25 15 10 5 3.0 2.0 1.0 0.0 0 -40 -25 -10 5 20 35 50 65 80 95 110 -40 125 -25 -10 5 35 50 65 80 95 110 125 Figure 7. Operation Supply Current (IDD-OP) vs. Temperature Figure 6. Startup Current (IDD-ST) vs. Temperature Minimum Operating Voltage (VDD-OFF) vs Temperature Start Threshold Voltage (VDD-ON) vs Temperature 20.0 13.0 19.0 12.0 VDD-OFF (V) VDD-ON (V) 20 Temperature (℃) Temperature (℃) 18.0 17.0 16.0 11.0 10.0 9.0 15.0 8.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 Temperature (℃) 20 35 50 65 80 95 110 125 Temperature (℃) Figure 8. Start Threshold Voltage (VDD-ON) vs. Temperature SG6741 — Highly Integrated Green-Mode PWM Controller Typical Performance Characteristics Figure 9. Minimum Operating Voltage (VDD-OFF) vs. Temperature 10 4.0 8 3.0 6 IHV-LC (µA) IHV (mA) Supply current drawn from pin HV (IHV) vs Temperature 5.0 2.0 1.0 4 2 0.0 0 -40 -25 -10 5 20 35 50 65 80 95 110 -40 125 -25 -10 5 20 35 50 65 80 95 110 125 Te m pe ratur e (℃ ) Temperature (℃) Figure 10. Supply Current Drawn from HV Pin (IHV) vs. Temperature Figure 11. HV Pin Leakage Current After Startup (IHV-LC) vs. Temperature Maximum Duty Cycle (DCYMAX) vs Temperature 70 70.0 68.0 66 DCYMAX (%) f OSC (kHz) 68 64 66.0 64.0 62 62.0 60 -40 -25 -10 5 20 35 50 65 80 95 110 60.0 125 -40 Temperature (℃) -25 -10 5 20 35 50 65 80 95 110 125 Temperature (℃) Figure 12. Frequency in Nominal Mode (fOSC) vs. Temperature © 2008 Fairchild Semiconductor Corporation SG6741 • Rev. 1.3.3 Figure 13. Maximum Duty Cycle (DCYMAX) vs. Temperature www.fairchildsemi.com 7 Startup Current Leading-Edge Blanking (LEB) For startup, the HV pin is connected to the line input or bulk capacitor through an external resistor, RHV, which is recommended as 100KΩ. Typical startup current drawn from pin HV is 2mA and it charges the hold-up capacitor through the resistor RHV. When the VDD capacitor level reaches VDD-ON, the startup current switches off. At that moment, the VDD capacitor only supplies the SG6741 to maintain the VDD before the auxiliary winding of the main transformer to carry on provide the operating current. Each time the power MOSFET is switched on, a turn-on spike occurs on the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver. Under-Voltage Lockout (UVLO) The turn-on and turn-off thresholds are fixed internally at 16.5V/10.5V. During startup, the hold-up capacitor must be charged to 16.5V through the startup resistor so that IC is enabled. The hold-up capacitor continues to supply VDD before the energy can be delivered from auxiliary winding of the main transformer. VDD must not drop below 10.5V during this startup process. This UVLO hysteresis window ensures that hold-up capacitor is adequate to supply VDD during startup. Operating Current Operating current is around 4mA. The low operating current enables better efficiency and reduces the requirement of VDD hold-up capacitance. Green-Mode Operation The patented green-mode function provides an off-time modulation to reduce switching frequency in light-load and no-load conditions. The on time is limited for better abnormal or brownout protection. VFB, which is derived from the voltage feedback loop, is used as the reference. Once VFB is lower than the threshold voltage, switching frequency is continuously decreased to the minimum green-mode frequency, around 22KHz (RI=26KΩ). Gate Output / Soft Driving The SG6741 BiCMOS output stage is a fast totem pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 18V Zener diode to protect power MOSFET transistors against undesirable gate over-voltage. A soft driving waveform is implemented to minimize EMI. Oscillator Operation Built-in Slope Compensation A resistor connected from the RI pin to the GND pin generates a constant current source for the controller. This current is used to determine the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26KΩ resistor RI results in a corresponding 65KHz PWM frequency. The relationship between RI and the switching frequency is: The sensed voltage across the current-sense resistor is used for peak-current-mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillation. SG6741 inserts a synchronized positive-going ramp at every switching cycle. fPWM = 1690 (KHz) RI (KΩ ) Constant Output Power Limit (1) When the SENSE voltage, across the sense resistor RS, reaches the threshold voltage around 0.9V, the output GATE drive is turned off after a small delay, tPD. This delay introduces an additional current, proportional to tPD • VIN / LP. The delay is nearly constant, regardless of the input voltage VIN. Higher input voltage results in a larger additional current and the output power limit is also higher than that under low input line voltage. To compensate this variation for wide AC input range, a sawtooth power-limiter is designed to solve the unequal power-limit problem. The power limiter is designed as a positive ramp signal and is fed to the inverting input of the OCP comparator. This results in a lower current limit at high-line inputs than at low-line inputs. The range of the PWM oscillation frequency is designed as 47kHz ~ 109kHz. Current Sensing / PWM Current Limiting Peak-current-mode control is utilized in SG6741 to regulate output voltage and provide pulse-by-pulse current limiting. The switch current is detected by a sense resistor into the SENSE pin. The PWM duty cycle is determined by this current-sense signal and VFB, the feedback voltage. When the voltage on the SENSE pin reaches around VCOMP = (VFB–1.2)/3.2, the switch cycle is terminated immediately. VCOMP is internally clamped to a variable voltage around 0.85V for output power limit. © 2008 Fairchild Semiconductor Corporation SG6741 • Rev. 1.3.3 SG6741 — Highly Integrated Green-Mode PWM Controller Functional Description www.fairchildsemi.com 8 VDD Over-Voltage Protection (OVP) Noise Immunity VDD over-voltage protection has been built in to prevent damage due to abnormal conditions. Once the VDD voltage is over the VDD over-voltage protection voltage (VDD-OVP), and lasts for tD-VDDOVP, the PWM pulses is disabled until the VDD voltage drops below the UVLO, then starts up again. Over-voltage conditions are usually caused by open feedback loops. Noise on the current sense or control signal may cause significant pulse width jitter, particularly in the continuous-conduction mode. Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near to the SG6741, and increasing the power MO gate resistance improves performance. Limited Power Control The FB voltage increases every time the output of the power supply is shorted or overloaded. If the FB voltage remains higher than a built-in threshold for longer than tD-OLP, PWM output is turned off. As PWM output is turned off, the supply voltage VDD begins decreasing. When VDD goes below the turn-off threshold (eg, 10.5V) the controller totally shuts down. VDD is charged up to the turn-on threshold voltage of 16V through the startup resistor until PWM output is restarted. This protection is activated as long as the overloading condition persists. This prevents the power supply from overheating. © 2008 Fairchild Semiconductor Corporation SG6741 • Rev. 1.3.3 SG6741 — Highly Integrated Green-Mode PWM Controller Functional Description (Continued) www.fairchildsemi.com 9 2 R2 T1 1 VZ1 1 2 3 C6 4 2 L1 4 2 BD1 CN1 C1 4 C2 1 4 T2 8 2 3 + 5 R1 C5 Q1 1 L4 VO+ 1 + 4 2 1 6 2 2 3 VO+ 2 C4 C3 2 1 1 3 2 3 CN1 L2 + D1 C8 2 7 3 1 1 1 1 C7 3 D2 2 VO- 2 R3 R4 Q2 3 1 D3 2 2 1 + SG6741 U1 GND GATE 8 1 1 C9 3 VDD NC SENSE HV RI 7 R5 6 5 R6 C10 R7 4 4 FB R8 1 2 C12 U2 VO+ R9 3 K 2 R10 C11 R U3 A R11 Figure 14. 60W Flyback 12V/5A Application Circuit BOM Designator Part Type Designator Part Type BD1 BD 4A/600V Q2 MOS 7A/600V C1 XC 0.68µF/300V R1 R 100KΩ 1/2W C2 XC 0.1µF/300V R2 R 47Ω 1/4W C3 YC 2200pF/Y1 R3 R 100KΩ 1/2W C4 EC 120µF/400V R4 R 20Ω 1/8W C5 CC 0.01µF/500V R5 R 100Ω 1/8W C6 CC 1000pF/100V R6 R 33KΩ 1/8W C7 EC 1000µF/25V R7 R 0.3Ω 2W C8 EC 470µF/25V R8 R 680Ω 1/8W C9 EC 22µF/50V R9 R 4.7KΩ 1/8W C10 CC 470pF/50V R10 R 150KΩ 1/8W C11 CC 2200pF/50V R11 R 39KΩ 1/8W C12 CC 0.01µF/50V THER1 Thermistor TTC104 D1 Zener Diode 15V 1/2W (option) T1 10mH D2 BYV95C T2 600µH(PQ2620) D3 FR103 U1 IC SG6741 F1 FUSE 4A/250V U2 IC PC817 L1 Inductor (900µH) U3 IC TL431 Q1 STP20-100CT VZ1 VZ 9G © 2008 Fairchild Semiconductor Corporation SG6741 • Rev. 1.3.3 SG6741 — Highly Integrated Green-Mode PWM Controller Applications Information www.fairchildsemi.com 10 5.00 4.80 A 0.65 3.81 5 8 B 6.20 5.80 PIN ONE INDICATOR 1.75 4.00 3.80 1 5.60 4 1.27 (0.33) 0.25 M 1.27 C B A LAND PATTERN RECOMMENDATION 0.25 0.10 SEE DETAIL A 1.75 MAX 0.25 0.19 C 0.10 0.51 0.33 0.50 x 45° 0.25 R0.10 SG6741 — Highly Integrated Green-Mode PWM Controller Physical Dimensions C OPTION A - BEVEL EDGE GAGE PLANE R0.10 OPTION B - NO BEVEL EDGE 0.36 NOTES: UNLESS OTHERWISE SPECIFIED 8° 0° 0.90 0.406 A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 15. 8-Pin Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2008 Fairchild Semiconductor Corporation SG6741 • Rev. 1.3.3 www.fairchildsemi.com 11 SG6741 — Highly Integrated Green-Mode PWM Controller © 2008 Fairchild Semiconductor Corporation SG6741 • Rev. 1.3.3 www.fairchildsemi.com 12