POWERINT TOP269KG

TOP264-271
TOPSwitch-JX Family
™
Integrated Off-Line Switcher with EcoSmart Technology
for Highly Efficient Power Supplies
™
Product Highlights
EcoSmart – Energy Efficient
• Ideal for applications from 10 W to 245 W
• Energy efficient over entire load range
• No-load consumption below 100 mW at 265 VAC
• Up to 750 mW standby output power for 1 W input at 230 VAC
High Design Flexibility for Low System Cost
• Multi-mode PWM control maximizes efficiency at all loads
• 132 kHz operation reduces transformer and power supply size
• 66 kHz option for highest efficiency requirements
• Accurate programmable current limit
• Optimized line feed-forward for line ripple rejection
• Frequency jittering reduces EMI filter cost
• Fully integrated soft-start for minimum start-up stress
• 725 V rated MOSFET
• Simplifies meeting design derating requirements
Extensive Protection Features
• Auto-restart limits power delivery to <3% during overload faults
• Output short-circuit protection (SCP)
• Output over-current protection (OCP)
• Output overload protection (OPP)
• Output overvoltage protection (OVP)
• User programmable for hysteretic/latching shutdown
• Simple fast AC reset
• Primary or secondary sensed
• Line undervoltage (UV) detection prevents turn-off glitches
• Line overvoltage (OV) shutdown extends line surge withstand
• Accurate thermal shutdown with large hysteresis (OTP)
Advanced Package Options
• eDIP™-12 package:
• 43 W / 117 W universal input power output capability with
PCB / metal heat sink
• Low profile horizontal orientation for ultra-slim designs
• Heat transfer to both PCB and heat sink
• Optional external heat sink provides thermal impedance
equivalent to a TO-220
• eSIP™-7C package:
• 177 W universal input output power capability
• Vertical orientation for minimum PCB footprint
• Simple heat sink mounting using clip provides thermal
impedance equivalent to a TO-220
• eSOP™-12 package:
• 66 W universal input output power capability
• Low profile surface mounted for ultra-slim designs
• Heat transfer to PCB via exposed pad and SOURCE pins
• Supports wave or reflow soldering
• Extended creepage to DRAIN pin
• Heat sink is connected to SOURCE for low EMI
www.powerint.com +
DC
OUT
-
AC
IN
V
D
CONTROL
TOPSwitch-JX
S
X
C
F
PI-5578-090309
Figure 1.
Typical Flyback Application.
eSIP-7C (E Package)
Figure 2.
eSOP-12 (K Package)
eDIP-12 (V Package)
Package Options.
Description
TOPSwitch-JX cost effectively incorporates a 725 V power
MOSFET, high-voltage switched current source, multi-mode
PWM control, oscillator, thermal shutdown circuit, fault
protection and other control circuitry onto a monolithic device.
Typical Applications
• Notebook or laptop adapter
• Generic adapter
• Printer
• LCD monitor
• Set-top box
• PC or LCD TV standby
• Audio amplifier
Output Power Ratings
See next page.
October 2011
TOP264-271
Output Power Table
Product5
TOP264VG
PCB Copper Area1
230 VAC ±15%4
85-265 VAC
Open
Open
2
Adapter2
Adapter
Frame3
Frame3
21 W
34 W
12 W
22.5 W
TOP264KG
30 W
49 W
16 W
30 W
TOP265VG
22.5 W
36 W
15 W
25 W
TOP265KG
33 W
53 W
20 W
34 W
TOP266VG
24 W
39 W
17 W
28.5 W
TOP266KG
36 W
58 W
23 W
39 W
TOP267VG
27.5 W
44 W
19 W
32 W
TOP267KG
40 W
65 W
26 W
45 W
TOP268VG
30 W
48 W
21.5 W
36 W
TOP268KG
46 W
73 W
30 W
50 W
TOP269VG
32 W
51 W
22.5 W
37.5 W
TOP269KG
50 W
81 W
33 W
55 W
TOP270VG
34 W
55 W
24.5 W
41 W
TOP270KG
56 W
91 W
36 W
60 W
TOP271VG
36 W
59 W
26 W
43 W
TOP271KG
63 W
102 W
40 W
66 W
Product5
Metal Heat Sink1
230 VAC ±15% 4
85-265 VAC
Open
Open
2
Adapter2
Adapter
Frame3
Frame3
TOP264EG/VG
30 W
62 W
20 W
43 W
TOP265EG/VG
40 W
81 W
26 W
57 W
TOP266EG/VG
60 W
119 W
40 W
86 W
TOP267EG/VG
85 W
137 W
55 W
103 W
TOP268EG/VG
105 W
148 W
70 W
112 W
TOP269EG/VG
128 W
162 W
80 W
120 W
TOP270EG/VG
147 W
190 W
93 W
140 W
TOP271EG/VG
177 W
244 W
118 W
177 W
Table 1. Output Power Table.
Notes:
1. See Key Application Considerations section for more details.
2. Maximum continuous power in a typical non-ventilated enclosed adapter measured at +50 °C ambient temperature.
3. Maximum continuous power in an open frame design at +50 °C ambient temperature.
4. 230 VAC or 110/115 VAC with doubler.
5. Packages: E: eSIP-7C, V: eDIP-12, K: eSOP-12. See Part Ordering Information section.
2
Rev. E 10/11
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TOP264-271
DRAIN (D)
0
VC
CONTROL (C)
INTERNAL
SUPPLY
1
ZC
-
SHUNT REGULATOR/
ERROR AMPLIFIER
+
5.8 V
4.8 V
+
-
INTERNAL UV
COMPARATOR
5.8 V
IFB
+
SOFT START
KPS(UPPER)
+
VI (LIMIT)
CURRENT
LIMIT
ADJUST
EXTERNAL CURRENT
LIMIT (X)
SHUTDOWN/
AUTO-RESTART
VOLTAGE
MONITOR (V)
STOP LOGIC
OVP OV/
UV
DCMAX
FREQUENCY (F)
CURRENT LIMIT
COMPARATOR
HYSTERETIC
THERMAL
SHUTDOWN
1V
LINE
SENSE
+
VBG + VT
V
KPS(LOWER)
÷ 16
ON/OFF
STOP
DCMAX
SOFT
START
OSCILLATOR
WITH JITTER
66k/132k
SOURCE (S)
CONTROLLED
TURN-ON
GATE DRIVER
DMAX
CLOCK
F REDUCTION
S
Q
R
LEADING
EDGE
BLANKING
F REDUCTION
KPS(UPPER)
KPS(LOWER)
SOFT START
IFB
PWM
IPS(UPPER)
IPS(LOWER)
OFF
PI-4511-012810
SOURCE (S)
Figure 3. Functional Block Diagram.
Pin Functional Description
DRAIN (D) Pin:
High-voltage power MOSFET DRAIN pin. The internal start-up
bias current is drawn from this pin through a switched highvoltage current source. Internal current limit sense point for
drain current.
CONTROL (C) Pin:
Error amplifier and feedback current input pin for duty cycle
control. Internal shunt regulator connection to provide internal
bias current during normal operation. It is also used as the
connection point for the supply bypass and auto-restart/
compensation capacitor.
EXTERNAL CURRENT LIMIT (X) Pin:
Input pin for external current limit adjustment remote ON/OFF
and device reset. A connection to SOURCE pin disables all
functions on this pin. This pin should not be left floating.
VOLTAGE MONITOR (V) Pin:
Input for OV, UV, line feed forward with DCMAX reduction, output
overvoltage protection (OVP), remote ON/OFF. A connection to
the SOURCE pin disables all functions on this pin. This pin should
not be left floating.
FREQUENCY (F) Pin:
Input pin for selecting switching frequency 132 kHz if connected
to SOURCE pin and 66 kHz if connected to CONTROL pin. This
pin should not be left floating.
SOURCE (S) Pin:
Output MOSFET source connection for high-voltage power return.
Primary side control circuit common and reference point.
NO CONNECTION (NC) Pin:
Internally not connected, floating potential pin.
E Package
(eSIP-7C)
Exposed Pad
(Hidden)
Internally
Connected to
SOURCE Pin
12345 7
VXCF S D
Exposed Pad Internally
Connected to SOURCE Pin
V Package
(eDIP-12)
S 12
1V
S 11
2X
S 10
3C
S9
4F
S8
S7
Exposed Pad (On Bottom)
Internally Connected to
SOURCE Pin
6D
K Package
(eSOP-12)
V1
12 S
X2
11 S
C3
10 S
F4
9S
8S
D6
7S
PI-5568-061011
Figure 4. Pin Configuration (Top View).
3
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Rev. E 10/11
DC
Input
Voltage
CONTROL
S
-
V
D
X
RIL
12 kΩ
For RLS = 4 MΩ
VUV = 102.8 VDC
VOV = 451 VDC
[email protected] VDC = 76%
[email protected] VDC = 41%
C
78
Slope = PWM Gain
For RIL = 12 kΩ
ILIMIT = 61%
CONTROL
Current
See Figure 37 for
other resistor values
(RIL) to select different
ILIMIT values.
Figure 5. Package Line Sense and Externally Set Current Limit.
TOP264-271 Functional Description
Like TOPSwitch-HX, TOP264-271 is an integrated switched
mode power supply chip that converts a current at the control
input to a duty cycle at the open drain output of a high-voltage
power MOSFET. During normal operation the duty cycle of the
power MOSFET decreases linearly with increasing CONTROL
pin current as shown in Figure 6.
In addition to the three terminal TOPSwitch features, such as
the high-voltage start-up, the cycle-by-cycle current limiting,
loop compensation circuitry, auto-restart and thermal shutdown, the TOP264-271 incorporates many additional functions
that reduce system cost, increase power supply performance
and design flexibility. A patented high-voltage CMOS technology
allows both the high-voltage power MOSFET and all the low
voltage control circuitry to be cost effectively integrated onto a
single monolithic chip.
Three terminals, FREQUENCY, VOLTAGE-MONITOR, and
EXTERNAL CURRENT LIMIT have been used to implement
some of the new functions. These terminals can be connected
to the SOURCE pin to operate the TOP264-271 in a TOPSwitchlike three terminal mode. However, even in this three terminal
mode, the TOP264-271 offers many transparent features that do
not require any external components:
1. A fully integrated 17 ms soft-start significantly reduces or
eliminates output overshoot in most applications by sweeping
both current limit and frequency from low to high to limit the
peak currents and voltages during start-up.
2. A maximum duty cycle (DCMAX) of 78% allows smaller input
storage capacitor, lower input voltage requirement and/or
higher power capability.
3. Multi-mode operation optimizes and improves the power
supply efficiency over the entire load range while maintaining
good cross regulation in multi-output supplies.
4. Switching frequency of 132 kHz reduces the transformer size
with no noticeable impact on EMI.
5. Frequency jittering reduces EMI in the full frequency mode at
high load condition.
Drain Peak Current
To Current Limit Ratio (%)
4 MΩ
RLS
Auto-Restart
Duty Cycle (%)
VUV = IUV × RLS + VV (IV = IUV)
VOV = IOV × RLS + VV (IV = IOV)
100
55
25
CONTROL
Current
Full Frequency Mode
132
Frequency (kHz)
+
PI-5579-111210
TOP264-271
Low
Frequency
Mode
Variable
Frequency
Mode
66
Multi-Cycle
Modulation
Jitter
30
ICD1 IB
IC01
IC02
IC03 ICOFF CONTROL
Current
PI-5665-110609
Figure 6. Control Pin Characteristics (Multi-Mode Operation).
6. Hysteretic over-temperature shutdown ensures thermal fault
protection.
7. Packages with omitted pins and lead forming provide large
drain creepage distance.
8. Reduction of the auto-restart duty cycle and frequency to
improve the protection of the power supply and load during
open loop fault, short-circuit, or loss of regulation.
9. Tighter tolerances on I2f power coefficient, current limit
reduction, PWM gain and thermal shutdown threshold.
The VOLTAGE-MONITOR (V) pin is usually used for line sensing
by connecting a 4 MW resistor from this pin to the rectified DC
high-voltage bus to implement line overvoltage (OV), undervoltage (UV) and dual-slope line feed-forward with DCMAX
reduction. In this mode, the value of the resistor determines the
OV/UV thresholds and the DCMAX is reduced linearly with a dual
slope to improve line ripple rejection. In addition, it also
provides another threshold to implement the latched and
4
Rev. E 10/11
www.powerint.com
TOP264-271
hysteretic output overvoltage protection (OVP). The pin can
also be used as a remote ON/OFF using the IUV threshold.
The EXTERNAL CURRENT LIMIT (X) pin can be used to reduce
the current limit externally to a value close to the operating peak
current, by connecting the pin to SOURCE through a resistor.
This pin can also be used as a remote ON/OFF input.
The FREQUENCY (F) pin sets the switching frequency in the full
frequency PWM mode to the default value of 132 kHz when
connected to SOURCE pin. A half frequency option of 66 kHz
can be chosen by connecting this pin to the CONTROL pin
instead. Leaving this pin open is not recommended.
CONTROL (C) Pin Operation
The CONTROL pin is a low impedance node that is capable of
receiving a combined supply and feedback current. During
normal operation, a shunt regulator is used to separate the
feedback signal from the supply current. CONTROL pin voltage
VC is the supply voltage for the control circuitry including the
MOSFET gate driver. An external bypass capacitor closely
connected between the CONTROL and SOURCE pins is
required to supply the instantaneous gate drive current. The
total amount of capacitance connected to this pin also sets the
auto-restart timing as well as control loop compensation.
When rectified DC high-voltage is applied to the DRAIN pin
during start-up, the MOSFET is initially off, and the CONTROL
pin capacitor is charged through a switched high-voltage
current source connected internally between the DRAIN and
CONTROL pins. When the CONTROL pin voltage VC reaches
approximately 5.8 V, the control circuitry is activated and the
soft-start begins. The soft-start circuit gradually increases the
drain peak current and switching frequency from a low starting
value to the maximum drain peak current at the full frequency
over approximately 17 ms. If no external feedback/supply
current is fed into the CONTROL pin by the end of the soft-start,
the high-voltage current source is turned off and the CONTROL
pin will start discharging in response to the supply current
drawn by the control circuitry. If the power supply is designed
properly, and no fault condition such as open loop or shorted
output exists, the feedback loop will close, providing external
CONTROL pin current, before the CONTROL pin voltage has
had a chance to discharge to the lower threshold voltage of
approximately 4.8 V (internal supply undervoltage lockout
threshold). When the externally fed current charges the CONTROL
pin to the shunt regulator voltage of 5.8 V, current in excess of
the consumption of the chip is shunted to SOURCE through an
NMOS current mirror as shown in Figure 3. The output current
of that NMOS current mirror controls the duty cycle of the
power MOSFET to provide closed loop regulation. The shunt
regulator has a finite low output impedance ZC that sets the gain
of the error amplifier when used in a primary feedback
configuration. The dynamic impedance ZC of the CONTROL pin
together with the external CONTROL pin capacitance sets the
dominant pole for the control loop.
When a fault condition such as an open loop or shorted output
prevents the flow of an external current into the CONTROL pin,
the capacitor on the CONTROL pin discharges towards 4.8 V.
At 4.8 V, auto-restart is activated, which turns the output
MOSFET off and puts the control circuitry in a low current
standby mode. The high-voltage current source turns on and
charges the external capacitance again. A hysteretic internal
supply undervoltage comparator keeps VC within a window of
typically 4.8 V to 5.8 V by turning the high-voltage current
source on and off as shown in Figure 8. The auto-restart circuit
has a divide-by-sixteen counter, which prevents the output
MOSFET from turning on again until sixteen discharge/charge
cycles have elapsed. This is accomplished by enabling the
output MOSFET only when the divide-by-sixteen counter
reaches the full count (S15). The counter effectively limits
TOP264-271 power dissipation by reducing the auto-restart
duty cycle to typically 2%. Auto-restart mode continues until
output voltage regulation is again achieved through closure of
the feedback loop.
Oscillator and Switching Frequency
The internal oscillator linearly charges and discharges an
internal capacitance between two voltage levels to create a
triangular waveform for the timing of the pulse width modulator.
This oscillator sets the pulse width modulator/current limit latch
at the beginning of each cycle.
The nominal full switching frequency of 132 kHz was chosen to
minimize transformer size while keeping the fundamental EMI
frequency below 150 kHz. The FREQUENCY pin, when shorted
to the CONTROL pin, lowers the full switching frequency to
66 kHz (half frequency), which may be preferable in some cases
such as noise sensitive video applications or a high efficiency
standby mode. Otherwise, the FREQUENCY pin should be
connected to the SOURCE pin for the default 132 kHz.
To further reduce the EMI level, the switching frequency in the
full frequency PWM mode is jittered (frequency modulated) by
approximately ±2.5 kHz for 66 kHz operation or ±5 kHz for
132 kHz operation at a 250 Hz (typical) rate as shown in Figure 7.
The jitter is turned off gradually as the system is entering the
variable frequency mode with a fixed peak drain current.
Pulse Width Modulator
The pulse width modulator implements multi-mode control by
driving the output MOSFET with a duty cycle inversely
proportional to the current into the CONTROL pin that is in
excess of the internal supply current of the chip (see Figure 6).
The feedback error signal, in the form of the excess current, is
filtered by an RC network with a typical corner frequency of
7 kHz to reduce the effect of switching noise in the chip supply
current generated by the MOSFET gate driver.
To optimize power supply efficiency, four different control
modes are implemented. At maximum load, the modulator
operates in full frequency PWM mode; as load decreases, the
modulator automatically transitions, first to variable frequency
PWM mode, then to low frequency PWM mode. At light load,
the control operation switches from PWM control to multi-cyclemodulation control, and the modulator operates in multi-cyclemodulation mode. Although different modes operate differently
to make transitions between modes smooth, the simple
relationship between duty cycle and excess CONTROL pin
current shown in Figure 6 is maintained through all three PWM
5
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Rev. E 10/11
Switching
Frequency
PI-4530-041107
TOP264-271
fOSC +
fOSC 4 ms
VDRAIN
Time
Figure 7. Switching Frequency Jitter (Idealized VDRAIN Waveforms).
modes. Please see the following sections for the details of the
operation of each mode and the transitions between modes.
Full Frequency PWM mode: The PWM modulator enters full
frequency PWM mode when the CONTROL pin current (IC)
reaches IB. In this mode, the average switching frequency is
kept constant at fOSC (pin selectable 132 kHz or 66 kHz). Duty
cycle is reduced from DCMAX through the reduction of the on-time
when IC is increased beyond IB. This operation is identical to the
PWM control of all other TOPSwitch families. TOP264-271 only
operates in this mode if the cycle-by-cycle peak drain current
stays above kPS(UPPER) × ILIMIT(set), where kPS(UPPER) is 55% (typical)
and ILIMIT(set) is the current limit externally set via the X pin.
Variable Frequency PWM mode: When peak drain current is
lowered to kPS(UPPER) × ILIMIT(set) as a result of power supply load
reduction, the PWM modulator initiates the transition to variable
frequency PWM mode, and gradually turns off frequency jitter.
In this mode, peak drain current is held constant at kPS(UPPER) ×
ILIMIT(set) while switching frequency drops from the initial full
frequency of fOSC (132 kHz or 66 kHz) towards the minimum
frequency of fMCM(MIN) (30 kHz typical). Duty cycle reduction is
accomplished by extending the off-time.
Low Frequency PWM mode: When switching frequency
reaches fMCM(MIN) (30 kHz typical), the PWM modulator starts to
transition to low frequency mode. In this mode, switching
frequency is held constant at fMCM(MIN) and duty cycle is reduced,
similar to the full frequency PWM mode, through the reduction
of the on-time. Peak drain current decreases from the initial
value of kPS(UPPER) × ILIMIT(set) towards the minimum value of
kPS(LOWER) × ILIMIT(set), where kPS(LOWER) is 25% (typical) and ILIMIT(set)
is the current limit externally set via the X pin.
Multi-Cycle-Modulation mode: When peak drain current is
lowered to kPS(LOWER) × ILIMIT(set), the modulator transitions to
multi-cycle-modulation mode. In this mode, at each turn-on,
the modulator enables output switching for a period of TMCM(MIN)
at the switching frequency of fMCM(MIN) (4 or 5 consecutive pulses
at 30 kHz) with the peak drain current of kPS(LOWER) × ILIMIT(set),
and stays off until the CONTROL pin current falls below IC(OFF).
This mode of operation not only keeps peak drain current low
but also minimizes harmonic frequencies between 6 kHz and
30 kHz. By avoiding transformer resonant frequency this way,
all potential transformer audible noises are greatly suppressed.
Maximum Duty Cycle
The maximum duty cycle, DCMAX, is set at a default maximum
value of 78% (typical). However, by connecting the VOLTAGEMONITOR to the rectified DC high-voltage bus through a resistor
with appropriate value (4 MW typical), the maximum duty cycle
can be made to decrease from 78% to 40% (typical) when input
line voltage increases from 88 V to 380 V, with dual gain slopes.
Error Amplifier
The shunt regulator can also perform the function of an error
amplifier in primary side feedback applications. The shunt
regulator voltage is accurately derived from a temperaturecompensated bandgap reference. The CONTROL pin dynamic
impedance ZC sets the gain of the error amplifier. The CONTROL
pin clamps external circuit signals to the VC voltage level. The
CONTROL pin current in excess of the supply current is
separated by the shunt regulator and becomes the feedback
current IFB for the pulse width modulator.
On-Chip Current Limit with External Programmability
The cycle-by-cycle peak drain current limit circuit uses the
output MOSFET ON-resistance as a sense resistor. A current
limit comparator compares the output MOSFET on-state drain
to source voltage VDS(ON) with a threshold voltage. High drain
current causes VDS(ON) to exceed the threshold voltage and turns
the output MOSFET off until the start of the next clock cycle.
The current limit comparator threshold voltage is temperature
compensated to minimize the variation of the current limit due
to temperature related changes in RDS(ON) of the output MOSFET.
The default current limit of TOP264-271 is preset internally.
However, with a resistor connected between EXTERNAL
CURRENT LIMIT (X) pin and SOURCE pin, current limit can be
programmed externally to a lower level between 30% and 100%
of the default current limit. By setting current limit low, a larger
TOP264-271 than necessary for the power required can be used
to take advantage of the lower RDS(ON) for higher efficiency/
smaller heat sinking requirements. With a second resistor
connected between the EXTERNAL CURRENT LIMIT (X) pin
and the rectified DC high-voltage bus, the current limit is
reduced with increasing line voltage, allowing a true power
limiting operation against line variation to be implemented. When
using an RCD clamp, this power limiting technique reduces
maximum clamp voltage at high line. This allows for higher
reflected voltage designs as well as reducing clamp dissipation.
The leading edge blanking circuit inhibits the current limit
comparator for a short time after the output MOSFET is turned
on. The leading edge blanking time has been set so that, if a
power supply is designed properly, current spikes caused by
primary-side capacitances and secondary-side rectifier reverse
recovery time should not cause premature termination of the
switching pulse. The current limit is lower for a short period
after the leading edge blanking time. This is due to dynamic
characteristics of the MOSFET. During start-up and fault
conditions the controller prevents excessive drain currents by
reducing the switching frequency.
Line Undervoltage Detection (UV)
At power up, UV keeps TOP264-271 off until the input line
voltage reaches the undervoltage threshold. At power down,
6
Rev. E 10/11
www.powerint.com
TOP264-271
~
~
~
~
VUV
~
~
~
~
~
~
VLINE
0V
S15 S14
S13
S12
S0
S14
S15
S13
S12
~
~
S0
S0
S15
S15
5.8 V
4.8 V
~
~
~
~
0V
S13 S12
~
~
S14
~
~
S15
VC
~
~
VDRAIN
0V
VOUT
1
2
3
~
~
~
~
~
~
0V
2
Note: S0 through S15 are the output states of the auto-restart counter
4
PI-4531-121206
Figure 8. Typical Waveforms for (1) Power Up (2) Normal Operation (3) Auto-Restart (4) Power Down.
UV prevents auto-restart attempts after the output goes out of
regulation. This eliminates power down glitches caused by slow
discharge of the large input storage capacitor present in
applications such as standby supplies. A single resistor
connected from the VOLTAGE-MONITOR pin to the rectified DC
high-voltage bus sets UV threshold during power up. Once the
power supply is successfully turned on, the UV threshold is
lowered to 44% of the initial UV threshold to allow extended
input voltage operating range (UV low threshold). If the UV low
threshold is reached during operation without the power supply
losing regulation, the device will turn off and stay off until UV
(high threshold) has been reached again. If the power supply
loses regulation before reaching the UV low threshold, the
device will enter auto-restart. At the end of each auto-restart
cycle (S15), the UV comparator is enabled. If the UV high
threshold is not exceeded, the MOSFET will be disabled during
the next cycle (see Figure 8). The UV feature can be disabled
independent of the OV feature.
Line Overvoltage Shutdown (OV)
The same resistor used for UV also sets an overvoltage
threshold, which, once exceeded, will force TOP264-271 to
stop switching instantaneously (after completion of the current
switching cycle). If this condition lasts for at least 100 ms, the
TOP264-271 output will be forced into off state. When the line
voltage is back to normal with a small amount of hysteresis
provided on the OV threshold to prevent noise triggering, the
state machine sets to S13 and forces TOP264-271 to go
through the entire auto-restart sequence before attempting to
switch again. The ratio of OV and UV thresholds is preset at
4.5, as can be seen in Figure 9. When the MOSFET is off, the
rectified DC high-voltage surge capability is increased to the
voltage rating of the MOSFET (725 V), due to the absence of the
reflected voltage and leakage spikes on the drain. The OV
feature can be disabled independent of the UV feature.
In order to reduce the no-load input power of TOP264-271
designs, the V pin operates at very low currents. This requires
careful layout considerations when designing the PCB to avoid
noise coupling. Traces and components connected to the V pin
should not be adjacent to any traces carrying switching currents.
These include the drain, clamp network, bias winding return or
power traces from other converters. If the line sensing features
are used, then the sense resistors must be placed within 10 mm
of the V pin to minimize the V pin node area. The DC bus
should then be routed to the line sense resistors. Note that
external capacitance must not be connected to the V pin as this
may cause misoperation of the V pin related functions.
Hysteretic or Latching Output Overvoltage Protection (OVP)
The detection of the hysteretic or latching output overvoltage
protection (OVP) is through the trigger of the line overvoltage
threshold. The V pin voltage will drop by 0.5 V, and the
controller measures the external attached impedance immediately
after this voltage drops. If IV exceeds IOV(LS) (336 mA typical)
longer than 100 ms, TOP264-271 will latch into a permanent off
state for the latching OVP. It only can be reset if IX exceeds IX(TH)
= -27 mA (typ) or VC goes below the power-up-reset threshold
(VC(RESET)) and then back to normal. If IV does not exceed IOV(LS) or
exceeds no longer than 100 ms, TOP264-271 will initiate the line
overvoltage and the hysteretic OVP. Their behavior will be
identical to the line overvoltage shutdown (OV) that has been
described in detail in the previous section. During a fault
condition resulting from loss of feedback, output voltage will
rapidly rise above the nominal voltage. The increase in output
voltage will also result in an increase in the voltage at the output
of the bias winding. A voltage at the output of the bias winding
that exceeds of the sum of the voltage rating of the Zener diode
connected from the bias winding output to the V pin and V pin
voltage, will cause a current in excess of IV to be injected into
the V pin, which will trigger the OVP feature.
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Rev. E 10/11
TOP264-271
If the power supply is operating under heavy load or low input
line conditions when an open loop occurs, the output voltage
may not rise significantly. Under these conditions, a latching
shutdown will not occur until load or line conditions change.
Nevertheless, the operation provides the desired protection by
preventing significant rise in the output voltage when the line or
load conditions do change. Primary side OVP protection with
the TOP264-271 in a typical application will prevent a nominal
12 V output from rising above approximately 20 V under open
loop conditions. If greater accuracy is required, a secondary
sensed OVP circuit is recommended.
Remote ON/OFF
TOP264-271 can be turned on or off by controlling the current
into the VOLTAGE-MONITOR pin or out from the EXTERNAL
CURRENT LIMIT pin. In addition, the VOLTAGE-MONITOR pin
has a 1 V threshold comparator connected at its input. This
voltage threshold can also be used to perform remote ON/OFF
control.
When a signal is received at the VOLTAGE-MONITOR pin or the
EXTERNAL CURRENT LIMIT pin to disable the output through
any of the pin functions such as OV, UV and remote ON/OFF,
TOP264-271 always completes its current switching cycle before
the output is forced off.
Line Feed-Forward with DCMAX Reduction
The same resistor used for UV and OV also implements line voltage
feed-forward, which minimizes output line ripple and reduces
power supply output sensitivity to line transients. Note that for the
same CONTROL pin current, higher line voltage results in smaller
operating duty cycle. As an added feature, the maximum duty
cycle DCMAX is also reduced from 78% (typical) at a voltage slightly
lower than the UV threshold to 36% (typical) at the OV threshold.
DCMAX of 36% at high line was chosen to ensure that the power
capability of the TOP264-271 is not restricted by this feature under
normal operation. TOP264-271 provides a better fit to the ideal
feed-forward by using two reduction slopes: -1% per mA for all bus
voltage less than 195 V (typical for 4 MW line impedance) and
-0.25% per mA for all bus voltage more than 195 V.
As seen above, the remote ON/OFF feature can also be used as
a standby or power switch to turn off the TOP264-271 and keep
it in a very low power consumption state for indefinitely long
periods. If the TOP264-271 is held in remote off state for long
enough time to allow the CONTROL pin to discharge to the
internal supply undervoltage threshold of 4.8 V (approximately
32 ms for a 47 µF CONTROL pin capacitance), the CONTROL
pin goes into the hysteretic mode of regulation. In this mode,
the CONTROL pin goes through alternate charge and discharge
cycles between 4.8 V and 5.8 V (see CONTROL pin operation
Voltage Monitor and External Current Limit Pin Table*
Figure Number
13
Three Terminal Operation
3
Line Undervoltage (UV)
Line Overvoltage (OV)
Line Feed-Forward (DCMAX)
Output Overvoltage Protection (OVP)
14
15
16
3
3
3
3
3
3
3
3
17
18
20
21
3
Overload Power Limiting (OPP)
External Current Limit
19
3
Remote ON/OFF
Device Reset
3
3
3
3
3
3
3
Fast AC Reset
AC Brownout
22
23
3
3
3
3
3
3
3
3
3
3
24
3
3
3
*This table is only a partial list of many VOLTAGE MONITOR and EXTERNAL CURRENT LIMIT Pin Configurations that are possible.
Table 2.
VOLTAGE MONITOR (V) Pin and EXTERNAL CURRENT LIMIT (X) Pin Configuration Options.
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TOP264-271
X Pin
V Pin
IUV
IREM(N)
IOV
IOV(LS)
(Enabled)
Output
MOSFET
Switching
(Non-Latching)
(Latching)
(Disabled)
Disabled when supply
output goes out of
regulation
I
ILIMIT (Default)
Current
Limit
I
DCMAX (78%)
Maximum
Duty Cycle
I
VBG
Pin Voltage
-250
-200
-150
-100
-50
0
25
50
75
100
125
336
I
X and V Pins Current (µA)
Note: This figure provides idealized functional characteristics with typical performance values. Please refer to the parametric
table and typical performance characteristics sections of the data sheet for measured data. For a detailed description of
each functional pin operation refer to the Functional Description section of the data sheet.
PI-5528-060409
Figure 9.
VOLTAGE MONITOR and EXTERNAL CURRENT LIMIT Pin Characteristics.
section above) and runs entirely off the high-voltage DC input,
but with very low power consumption (<100 mW typical at
230 VAC with X pin open). When the TOP264-271 is remotely
turned on after entering this mode, it will initiate a normal
start-up sequence with soft-start the next time the CONTROL
pin reaches 5.8 V. In the worst case, the delay from remote-on
to start-up can be equal to the full discharge/charge cycle time
of the CONTROL pin, which is approximately 125 ms for a
47 µF CONTROL pin capacitor. This reduced consumption
remote off mode can eliminate expensive and unreliable in-line
mechanical switches. It also allows for microprocessor
controlled turn-on and turn-off sequences that may be required
in certain applications such as inkjet and laser printers.
Soft-Start
The 17 ms soft-start sweeps the peak drain current and switching
frequency linearly from minimum to maximum value by operating
through the low frequency PWM mode and the variable
frequency mode before entering the full frequency mode. In
addition to start-up, soft-start is also activated at each restart
attempt during auto-restart and when restarting after being in
hysteretic regulation of CONTROL pin voltage (VC), due to
remote OFF or thermal shutdown conditions. This effectively
minimizes current and voltage stresses on the output MOSFET,
the clamp circuit and the output rectifier during start-up. This
feature also helps minimize output overshoot and prevents
saturation of the transformer during start-up.
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Rev. E 10/11
TOP264-271
Shutdown/Auto-Restart (for OCP, SCP, OPP)
To minimize TOP264-271 power dissipation under fault
conditions such as over current (OC), short-circuit (SC) or over
power (OP), the shutdown/auto-restart circuit turns the power
supply on and off at an auto-restart duty cycle of typically 2% if
an out of regulation condition persists. Loss of regulation
interrupts the external current into the CONTROL pin. VC
regulation changes from shunt mode to the hysteretic autorestart mode as described in CONTROL pin operation section.
When the fault condition is removed, the power supply output
becomes regulated, VC regulation returns to shunt mode, and
normal operation of the power supply resumes.
Hysteretic Over-Temperature Protection (OTP)
Temperature protection is provided by a precision analog circuit
that turns the output MOSFET off when the junction temperature
exceeds the thermal shutdown temperature (142 °C typical).
When the junction temperature cools to below the lower
hysteretic temperature point, normal operation resumes, thus
providing automatic recovery. A large hysteresis of 75 °C
(typical) is provided to prevent overheating of the PC board due
to a continuous fault condition. VC is regulated in hysteretic
mode, and a 4.8 V to 5.8 V (typical) triangular waveform is
present on the CONTROL pin while in thermal shutdown.
Bandgap Reference
All critical TOP264-271 internal voltages are derived from a
temperature-compensated bandgap reference. This voltage
reference is used to generate all other internal current references,
which are trimmed to accurately set the switching frequency,
MOSFET gate drive current, current limit, and the line OV/UV/
OVP thresholds. TOP264-271 has improved circuitry to
maintain all of the above critical parameters within very tight
absolute and temperature tolerances.
High-Voltage Bias Current Source
This high-voltage current source biases TOP264-271 from the
DRAIN pin and charges the CONTROL pin external capacitance
during start-up or hysteretic operation. Hysteretic operation
occurs during auto-restart, remote OFF and over-temperature
shutdown. In this mode of operation, the current source is
switched on and off, with an effective duty cycle of approximately 35%. This duty cycle is determined by the ratio of
CONTROL pin charge (IC) and discharge currents (ICD1 and ICD2).
This current source is turned off during normal operation when
the output MOSFET is switching. The effect of the current
source switching will be seen on the DRAIN voltage waveform
as small disturbances and is normal.
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TOP264-271
CONTROL (C)
200 µA
(Negative Current Sense - ON/OFF,
Current Limit Adjustment, OVP Latch Reset)
VBG + VT
EXTERNAL CURRENT LIMIT (X)
(Voltage Sense, ON/OFF)
VOLTAGE MONITOR (V)
VREF
1V
(Positive Current Sense - Undervoltage,
Overvoltage, ON/OFF, Maximum Duty
Cycle Reduction, Output Overvoltage Protection)
400 µA
PI-5567-030910
Figure 10. VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pin Input Simplified Schematic.
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Rev. E 10/11
TOP264-271
Typical Uses of FREQUENCY (F) Pin
+
+
DC
Input
Voltage
DC
Input
Voltage
D
CONTROL
S
C
D
CONTROL
S
F
-
F
PI-2655-071700
PI-2654-071700
Figure 11. Full Frequency Operation (132 kHz).
C
Figure 12. Half Frequency Operation (66 kHz).
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Rev. E 10/11
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TOP264-271
Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins
V Package (eDIP-12)
+
E Package
(eSIP-7C)
VXC FS
DC
Input
Voltage
S 12
1V
2X
S 11
D
S 10
S9
S8
3C
4F
S7
6D
S
C
V
D
CONTROL
S
-
X
D C
K Package (eSOP-12)
S D
1V
VUV = IUV × RLS + VV (IV = IUV)
VOV = IOV × RLS + VV (IV = IOV)
RLS
4 MΩ
-
PI-4717-120307
Figure 14. Line-Sensing for Undervoltage, Overvoltage and Line Feed-Forward.
+
VUV = RLS × IUV + VV (IV = IUV)
ROVP
DCMAX @ 100 VDC = 76%
DCMAX @ 375 VDC = 41%
4 MΩ
DC
Input
Voltage
40 kΩ
D
C
V
CONTROL
6.2 V
ROVP >3kΩ
S
For Values Shown
VUV = 103.8 VDC
RLS
V
CONTROL
C
S
-
For RLS = 4 MΩ
VUV = 102.8 VDC
VOV = 451 VDC
Sense Output Voltage
VROVP
D
V
CONTROL
PI-6119-061011
Figure 13. Three Terminal Operation (VOLTAGE MONITOR and EXTERNAL CURRENT LIMIT Features Disabled. FREQUENCY Pin Tied to SOURCE or CONTROL Pin.)
DC
Input
Voltage
For RLS = 4 MΩ
VUV = 102.8 VDC
VOV = 451 VDC
[email protected] VDC = 76%
[email protected] VDC = 41%
D
S
C D
4 MΩ
DC
Input
Voltage
S7
6D
+
RLS
S 11
S 10
S9
S8
4F
F
VUV = IUV × RLS + VV (IV = IUV)
VOV = IOV × RLS + VV (IV = IOV)
S 12
2X
3C
C
+
-
C
S
PI-4720-120307
PI-4719-120307
Figure 15. Line-Sensing for Undervoltage, Overvoltage, Line Feed-Forward and Hysteretic Output Overvoltage Protection.
+
RLS
DC
Input
Voltage
VOV = IOV × RLS + VV (IV = IOV)
4 MΩ
For Values Shown
VOV = 457.2 VDC
CONTROL
-
1N4148
V
+
For RIL = 12 kΩ
ILIMIT = 61%
For RIL = 19 kΩ
ILIMIT = 37%
DC
Input
Voltage
55 kΩ
D
Figure 16. Line Sensing for Undervoltage Only (Overvoltage Disabled).
C
CONTROL
S
S
PI-4721-120307
Figure 17. Line-Sensing for Overvoltage Only (Undervoltage Disabled). Maximum Duty Cycle Reduced at Low Line and Further Reduction with Increasing Line Voltage.
See Figure 37 for other
resistor values (RIL).
D
C
X
RIL
PI-5580-111210
Figure 18. External Set Current Limit.
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Rev. E 10/11
TOP264-271
Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins (cont.)
+
RLS
DC
Input
Voltage
+
ILIMIT = 100% @ 100 VDC
ILIMIT = 53% @ 300 VDC
2.5 MΩ
DC
Input
Voltage
D
CONTROL
S
D
CONTROL
C
X
S
RIL
6 kΩ
-
QR can be an optocoupler
output or can be replaced by
a manual switch.
X
ON/OFF
QR
-
C
47 KΩ
PI-5465-061009
PI-5466-061009
Figure 19. Current Limit Reduction with Line Voltage.
+
Figure 20. Active-on (Fail Safe) Remote ON/OFF, and Latch Reset.
+
QR can be an optocoupler
output or can be replaced
by a manual switch.
VUV = IUV × RLS + VV (IV = IUV)
VOV = IOV × RLS + VV (IV = IoV)
4 MΩ [email protected] VDC = 76%
[email protected] VDC = 41%
RLS
For RIL = 12 kΩ
DC
Input
Voltage
ILIMIT = 61%
D
CONTROL
S
DC
Input
Voltage
For RIL = 19 kΩ
ILIMIT = 37%
C
X
CONTROL
S
RIL
-
QR
16 kΩ
QR can be an optocoupler
output or can be replaced
by a manual switch.
V
D
For RIL = 12 kΩ
ILIMIT = 61%
X
RIL
ON/OFF
C
-
QR
16 kΩ
PI-5531-072309
PI-5467-061009
Figure 22. Active-on Remote ON/OFF with Line Sense and External Current Limit, and Latch Reset.
VUV = IUV x RLS + VV (IV = IUV)
VOV = IOV x RLS + VV (IV = IoV)
4 MΩ
RLS
DC
Input
Voltage
CONTROL
S
-
V
D
X
RIL
12 kΩ
For RLS = 4 MΩ
PI-5565-111210
Figure 21. Active-on Remote ON/OFF with Externally Set Current Limit,
and Latch Reset
+
+
VUV = 102.8 VDC
VOV = 451 VDC
DCMAX @ 100 VDC = 76%
DCMAX @ 375 VDC = 41%
C
Figure 23. Line Sensing and Externally Set Current Limit.
Typ. 65 VAC brownout threshold.
<3 s AC latch reset time.
Higher gain QR allows increasing R1/
decreasing C1 for lower no-load input
power.
D
DC
Input
Voltage
CONTROL
S
For RIL = 12 kΩ
ILIMIT = 61%
See Figure 37 for
other resistor values
(RIL) to select different
ILIMIT values.
ON/OFF
X
RIL
-
C
QR
R1
4 MΩ 1N4007
R2
39 kΩ
AC
C1 Input
47 nF
PI-5652-110609
Figure 24. Externally Set Current Limit, Fast AC Latch Reset and Brownout.
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Rev. E 10/11
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TOP264-271
Application Example
device size often results in the same or lower efficiency due to
the larger switching losses associated with a larger MOSFET.
Low No-load, High Efficiency, 65 W, Universal Input
Adapter Power Supply
Line Sense Resistor Values
• Increasing line sensing resistance from 4 MΩ to 10.2 MΩ to
reduce no-load input power dissipation by 16 mW
The circuit shown in Figure 25 shows a 90 VAC to 265 VAC
input, 19 V, 3.42 A output power supply, designed for operation
inside a sealed adapter case type. The goals of the design were
highest full load efficiency, highest average efficiency (average of
25%, 50%, 75% and 100% load points), and very low no-load
consumption. Additional requirements included latching output
overvoltage shutdown and compliance to safety agency limited
power source (LPS) limits. Measured efficiency and no-load
performance is summarized in the table shown in the schematic
which easily exceed current energy efficiency requirements.
Line sensing is provided by resistors R3 and R4 and sets the
line undervoltage and overvoltage thresholds. The combined
value of these resistors was increased from the standard 4 MΩ
to 10.2 MΩ. This reduced the resistor dissipation, and therefore
contribution to no-load input power, from ~26 mW to ~10 mW. To
compensate the resultant change in the UV (turn-on) threshold
resistor R20 was added between the CONTROL and VOLTAGEMONITOR pins. This adds a DC current equal to ~16 µA into the
V pin, requiring only 9 µA to be provided via R3 and R4 to reach
the V pin UV (turn-on) threshold current of 25 µA and setting the
UV threshold to 95 VDC.
In order to meet these design goals the following key design
decisions were made.
PI Part Selection
• One device size larger selected than required for power
delivery to increase efficiency
This technique does effectively disable the line OV feature as
the resultant OV threshold is raised from ~450 VDC to ~980 VDC.
However in this design there was no impact as the value of
input capacitance (C2) was sufficient to allow the design to
withstand differential line surges greater than 2 kV without the
peak drain voltage reaching the BVDSS rating of U1.
The current limit programming feature of TOPSwitch-JX allows
the selection of a larger device than needed for power delivery.
This gives higher full load, low line efficiency by reducing the
MOSFET conduction losses (IRMS2 × RDS(ON)) but maintains the
overload power, transformer and other components size as if a
smaller device had been used.
Specific guidelines and detailed calculations for the value of
R20 may be found in the TOPSwitch-JX Application Note (AN-47).
Clamp Configuration – RZCD vs RCD
• An RZCD (Zener bleed) was selected over an RCD clamp to
give higher light load efficiency and lower no-load consumption
For this design one device size larger than required for power
delivery (as recommended by the power table) was selected.
This typically gives the highest efficiency. Further increases in
Input Voltage (VAC)
90
115
230
Full Power Efficiency (%)
86.6
88.4
89.1
89.8
89.5
59.7
86.7
Average Efficiency (%)
No-load Input Power (mW)
57.7
C11
1 nF
250 VAC
VR2
SMAJ250A
D1
GBU8J
600 V
R6
150 Ω
R11
300 Ω
R3
5.1 MΩ
R7
10 MΩ
L3
12 mH
R1
R2
2.2 MΩ 2.2 MΩ
C2
120 µF
400 V
R4
5.1 MΩ
R8
10 MΩ
C5
2.2 nF
1 kV
Q1
MMBT4403
C9
220 nF
25 V
R20
191 kΩ
1%
L4
200 µH
TOPSwitch-JX
U1
TOP269EG
F1
4A
S
L
90 - 265
VAC
CONTROL
R9
11 kΩ
1%
X
F
D4
BAV21WS7-F
4
C10
56 µF
35 V
R22
1.6 kΩ
R16
20 kΩ
C19
6.8 nF
50 V
C15
470 pF
50 V
R14
20 Ω
R12
4.7 kΩ
VR1
ZMM5244B-7
V
D
5
R10
100 Ω
D3
BAV19WS
C1
330 nF
275 VAC
N
RTN
D2
RS1K
R24
2.2 Ω
19 V, 3.42 A
C21
10 nF
50 V
D5
V30100C
FL2
R28
300 Ω
1
R29
300 Ω
C13
C14
470 µF 470 µF
25 V
25 V
T1
3 RM10 FL1
C4
1000 pF
630 V
R5
300 Ω
C12
1 nF R15
100 V 33 Ω
R25
20 Ω
1/8 W
C
C6
100 nF
50 V
U3B
PS25011-H-A
Q2
MMBT3904
C16
22 nF
50 V
R13
6.8 Ω
1/8 W
C7
47 µF
16 V
R17
147 kΩ
1%
R27
10 kΩ
U3A
PS25011-H-A
R19
20 kΩ
C22
100 nF
50 V
U2
LMV431AIMF
1%
R18
10 kΩ
1%
PI-5667-030810
Figure 25. Schematic of High Efficiency 19 V, 65 W, Universal Input Flyback Supply With Low No-load.
15
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Rev. E 10/11
TOP264-271
The clamp network is formed by VR2, C4, R5, R6, R11, R28,
R29 and D2. It limits the peak drain voltage spike caused by
leakage inductance to below the BVDSS rating of the internal
TOPSwitch-JX MOSFET. This arrangement was selected over a
standard RCD clamp to improve light load efficiency and
no-load input power.
In a standard RCD clamp C4 would be discharged by a parallel
resistor rather than a resistor and series Zener. In an RCD clamp
the resistor value is selected to limit the peak drain voltage
under full load and overload conditions. However under light or
no-load conditions this resistor value now causes the capacitor
voltage to discharge significantly as both the leakage inductance
energy and switching frequency are lower. As the capacitor has
to be recharged to above the reflected output voltage each
switching cycle the lower capacitor voltage represents wasted
energy. It has the effect of making the clamp dissipation
appear as a significant load just as if it were connected to the
output of the power supply.
The RZCD arrangement solves this problem by preventing the
voltage across the capacitor discharging below a minimum
value (defined by the voltage rating of VR2) and therefore
minimizing clamp dissipation under light and no-load conditions.
Resistors R6 and R28 provide damping of high frequency
ringing to reduce EMI. Due to the resistance in series with VR2,
limiting the peak current, standard power Zeners vs a TVS type
may be used for lower cost (although a TVS type was selected
due to availability of a SMD version). Diode D2 was selected to
have an 800 V vs the typical 600 V rating due to its longer
reverse recovery time of 500 ns. This allows some recovery of
the clamp energy during the reverse recovery time of the diode
improving efficiency. Multiple resistors were used in parallel to
share dissipation as SMD components were used.
Feedback Configuration
• A Darlington connection formed together with optocoupler
transistor to reduce secondary side feedback current and
therefore no-load input power
• Low voltage, low current voltage reference IC used on
secondary side to reduce secondary side feedback current
and therefore no-load input power
• Bias winding voltage tuned to ~9 V at no-load, high line to
reduce no-load input power
Typically the feedback current into the CONTROL pin at high
line is ~3 mA. This current is both sourced from the bias
winding (voltage across C10) and directly from the output. Both
of these represent a load on the output of the power supply.
To minimize the dissipation from the bias winding under no-load
conditions the number of bias winding turns and value of C10
was adjusted to give a minimum voltage across C10 of ~9 V.
This is the minimum required to keep the optocoupler biased.
To minimize the dissipation of the secondary side feedback
circuit Q2 was added to form a Darlington connection with U3B.
This reduced the feedback current on the secondary to ~1 mA.
The increased loop gain (due to the hFE of the transistor) was
compensated by increasing the value of R16 and the addition of
R25. A standard 2.5 V TL431 voltage reference was replaced
with the 1.24 V LMV431 to reduce the supply current requirement
from 1 mA to 100 µA.
Output Rectifier Choice
• Higher current rating, low VF Schottky rectifier diode selected
for output rectifier
A dual 15 A, 100 V Schottky rectifier diode with a VF of 0.455 V
at 5 A was selected for D5. This is a higher current rating than
required to reduce resistive and forward voltage losses to improve
both full load and average efficiency. The use of a 100 V Schottky
was possible due to the high transformer primary to secondary
turns ratio (VOR = 110 V) which was in turn possible due to the
high-voltage rating of the TOPSwitch-JX internal MOSFET.
Increased Output Overvoltage Shutdown Sensitivity
• Transistor Q1 and VR1 added to improve the output overvoltage shutdown sensitivity
During an open loop condition the output and therefore bias
winding voltage will rise. When this exceeds the voltage of VR1
plus a VBE voltage drop Q1 turns on and current is fed into the
V pin. The addition of Q1 ensures that the current into the V pin
is sufficient to exceed the latching shutdown threshold even
when the output is fully loaded while the supply is operating at
low line as under this condition the output voltage overshoot is
relatively small
Output overload power limitation is provided via the current limit
programming feature of the X pin and R7, R8 and R9. Resistors
R8 and R9 reduce the device current limit as a function of
increasing line voltage to provide a roughly flat overload power
characteristic, below the 100 VA limited power source (LPS)
requirement. In order to still meet this under a single fault condition
(such as open circuit of R8) the rise in the bias voltage that occurs
during an overload condition is also used to trigger a latching
shutdown.
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Rev. E 10/11
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TOP264-271
Very Low No-load, High Efficiency, 30 W, Universal Input,
Open Frame, Power Supply
The size of the magnetic core is a function of the switching
frequency. The choice of the higher switching frequency of
132 kHz allowed for the use of a smaller core size. The higher
switching frequency does not negatively impact the efficiency in
TOPSwitch-JX designs due its small drain to source capacitance
(COSS) as compared to that of discrete MOSFETs.
The circuit shown in Figure 26 below shows an 85 VAC to
265 VAC input, 12 V, 2.5 A output power supply. The goals of
the design were highest full load efficiency, average efficiency
(average of 25%, 50%, 75% and 100% load points), very low noload consumption. Additional requirements included latching
output overvoltage shutdown and compliance to safety agency
limited power source (LPS) limits. Actual efficiency and no-load
performance is summarized in the table shown in the schematic
which easily exceed current energy efficiency requirements.
Line Sense Resistor Values
• Increasing line sensing resistance from 4 MΩ to 10.2 MΩ to
reduce no-load input power dissipation by 16 mW
Line sensing is provided by resistors R1 and R2 and sets the
line undervoltage and overvoltage thresholds. The combined
value of these resistors was increased from the standard 4 MW
to 10.2 MW. This reduces the current into the V pin, and
therefore contribution to no-load input power, from ~26 mW to ~
10 mW. To compensate the resultant change in the UV
threshold resistor R12 was added between the CONTROL and
VOLTAGE-MONITOR pins. This adds a DC current equal to ~16
mA into the V pin, requiring only 9 mA to be provided via R1 and
R2 to reach the V pin UV threshold current of 25 mA and setting
the UV threshold to approximately 95 VDC.
In order to meet these design goals the following key design
decisions were made.
PI part selection
• Ambient of 40 °C allowed one device size smaller than
indicated by the power table
The device selected for this design was based on the 85-265 VAC,
Open Frame, PCB heat sinking column of power table (Table 1).
One device size smaller was selected (TOP266V vs TOP267V)
due to the ambient specification of 40 °C (vs the 50°C assumed
in the power table) and the optimum PCB area and layout for
the device heat sink. The subsequent thermal and efficiency
data confirmed this choice. The maximum device temperature
was 107°C at full load, 40 °C, 85 VAC, 47 Hz (worst case
conditions) and average efficiency exceeded 83% ENERGY
STAR and EuP Tier 2 requirements.
This technique does effectively disable the line OV feature as
the resultant OV threshold is raised from ~450 VDC to ~980 VDC.
However in this design there was no impact as the value of
input capacitance (C3) was sufficient to allow the design to
withstand differential line surges greater than 1 kV without the
peak drain voltage reaching the BVDSS rating of U1.
Specific guidelines and detailed calculations for the value of R12
may be found in the TOPSwitch-JX Application Note.
Transformer Core Selection
• 132 kHz switching frequency allowed the selection of smaller
core for lower cost
Input Voltage (VAC)
85
115
230
Full Load Efficiency (%)
81.25 83.94 86.21
Average Efficiency (%)
84.97 85.13
No-load Input Power (mW)
60.8
D1
1N4007
C11
1 nF
250 VAC
61.98 74.74
VR1
P6KE180A
6
D2
1N4007
R3
10 MΩ
2
R2
5.1 MΩ
R9
10 Ω
VR3
ZMM5245B-7
R4
10 MΩ
D3
1N4007
F1
3.15 A
L
85 - 264
VAC
N
CONTROL
S
R15
14.3 kΩ
1%
R19
470 Ω
D10
LL4148
R21
86.6 kΩ
1%
U2A
LTV817D
V
D
TOPSwitch-JX
U1
TOP266VG
C1
100 nF
275 VAC
R18
110 Ω
U2B
LTV817D
R12
191 kΩ
1%
D4
1N4007
12 V, 2.5 A
RTN
C18
47 nF
50 V
D6
BAV19WS
L1
14 mH
C16
100 µF
25 V
D7
BAV21WS7-F
T1
EF25
C3
82 µF
400 V
L2
3.3 µH
C7
47 µF
25 V
1
NC NC
D5
FR107
C15
680 µF
25 V
D8,9
SB560
11,12
4
R1
5.1 MΩ
C14
680 µF
25 V
7,8
C4
4.7 nF
1 kV
R5
10 kΩ
1/2 W
C12
1 nF R17
200 V 22 Ω
X
F
C
C9
100 nF
50 V
R16
6.8 Ω
1/8 W
C10
47 µF
25 V
C20
33 nF
50 V
U3
LMV431A
1%
R23
10 kΩ
1%
PI-5775-030810
Figure 26. Schematic of High Efficiency 12 V, 30 W, Universal Input Flyback Supply With Very Low No-load.
17
www.powerint.com
Rev. E 10/11
TOP264-271
Clamp Configuration – RZCD vs RCD
• An RZCD (Zener bleed) was selected over RCD to give higher
light load efficiency and lower no-load consumption
The clamp network is formed by VR1, C4, R5 and D5. It limits
the peak drain voltage spike caused by leakage inductance to
below the BVDSS rating of the internal TOPSwitch-JX MOSFET.
This arrangement was selected over a standard RCD clamp to
improve light load efficiency and no-load input power.
In a standard RCD clamp C4 would be discharged by a parallel
resistor rather than a resistor and series Zener. In an RCD
clamp the resistor value of R5 is selected to limit the peak drain
voltage under full load and over-load conditions. However
under light or no-load conditions this resistor value now causes
the capacitor voltage to discharge significantly as both the
leakage inductance energy and switching frequency are lower.
As the capacitor has to be recharged to above the reflected
output voltage each switching cycle the lower capacitor voltage
represents wasted energy. It has the effect of making the
clamp dissipation appear as a significant load just as if it were
connected to the output of the power supply.
The RZCD arrangement solves this problem by preventing the
voltage across the capacitor discharging below a minimum
value (defined by the voltage rating of VR1) and therefore
minimizing clamp dissipation under light and no-load conditions.
Zener VR1 is shown as a high peak dissipation capable TVS
however a standard lower cost Zener may also be used due to
the low peak current that component experiences.
In many designs a resistor value of less than 50 W may be used
in series with C4 to damp out high frequency ringing and
improve EMI but this was not necessary in this case.
Feedback Configuration
• A high CTR optocoupler was used to reduce secondary bias
currents and no-load input power
• Low voltage, low current voltage reference IC used on
secondary side to reduce secondary side feedback current
and no-load input power
• Bias winding voltage tuned to ~9 V at no-load, high line to
reduce no-load input power
Typically the feedback current into the CONTROL pin at high
line is ~3 mA. This current is both sourced from the bias
winding (voltage across C10) and directly from the output. Both
of these represent a load on the output of the power supply.
To minimize the dissipation from the bias winding under no-load
conditions the number of bias winding turns and value of C7
was adjusted to give a minimum voltage across C7 of ~9 V.
This is the minimum required to keep the optocoupler biased
and the output in regulation.
To minimize the dissipation of the secondary side feedback
circuit a high CTR (CTR of 300 – 600%) optocoupler type was
used. This reduces the secondary side opto-led current from
~3 mA to <~1 mA and therefore the effective load on the output.
A standard 2.5 V TL431 voltage reference was replaced with the
1.24 V LMV431 to reduce the supply current requirement of this
component from 1 mA to 100 mA.
Output Rectifier Choice
• Use of high VOR allows the use of a 60 V Schottky diode for
high efficiency and lower cost
The higher BVDSS rating of the TOPSwitch-JX of 725 V
(compared to 600 V or 650 V rating of typical power MOSFETs)
allowed a higher transformer primary to secondary turns ratio
(reflected output voltage or VOR). This reduced the output diode
voltage stress and allowed the use of cheaper and more efficient
60 V (vs 80 V or 100 V) Schottky diodes. The efficiency
improvement occurs due the lower forward voltage drop of the
lower voltage diodes. Two parallel connected axial 5 A, 60 V
Schottky rectifier diodes were selected for both low cost and
high efficiency. This allowed PCB heat sinking of the diode for
low cost while maintaining efficiency compared to a single
higher current TO-220 packaged diode mounted on a heat sink.
For this configuration the recommendation is that each diode is
rated at twice the output current and that the diodes share a
common cathode PCB area for heat sinking so that their
temperatures track. In practice the diodes current share quite
effectively as can be demonstrated by monitoring their
individual temperatures.
Output Inductor Post Filter Soft-Finish
• Inductor L2 used to provide an output soft-finish and eliminate
a capacitor
To prevent output overshoot during start-up the voltage
appearing across L2 is used to provide a soft-finish function.
When the voltage across L2 exceeds the forward drop of U2A
and D10 current flows though the optocoupler LED and
provides feedback to the primary. This arrangement acts to
limit the rate of rise of the output voltage until it reaches
regulation and eliminates the capacitor that is typically placed
across U3 to provide the same function.
Key Application Considerations
TOPSwitch-JX vs. TOPSwitch-HX
Table 3 compares the features and performance differences
between TOPSwitch-JX and TOPSwitch-HX. Many of the new
features eliminate the need for additional discrete components.
Other features increase the robustness of design, allowing cost
savings in the transformer and other power components.
TOP264-271 Design Considerations
Power Table
The data sheet power table (Table 1) represents the maximum
practical continuous output power based on the following
conditions:
1. 12 V output.
2. Schottky or high efficiency output diode.
3. 135 V reflected voltage (VOR) and efficiency estimates.
4. A 100 VDC minimum DC bus for 85-265 VAC and 250 VDC
minimum for 230 VAC.
5. Sufficient heat sinking to keep device temperature ≤110 °C.
18
Rev. E 10/11
www.powerint.com
TOP264-271
TOPSwitch-HX vs. TOPSwitch-JX
Function
TOPSwitch-HX
TOPSwitch-JX
TOPSwitch-JX Advantages
CONTROL current IC(OFF) at
0% duty cycle
IC(OFF) = IB + 3.4 mA
(TOP256-258)
IB = External bias current
IC(OFF) = IB + 1.6 mA
(TOP266-268)
• Reduced CONTROL current
Not available
Available
eDIP-12 / eSOP-12
packages
• Better no-load performance (<0.1 W)
• Better standby performance
• 66/132 kHz frequency option for DIP style heat sink
less designs
• Better thermal performance for increased power
capability over DIP-8 / SMD-8 packages
Breakdown voltage BVDSS
Min. 700 V at TJ = 25 °C
Min. 725 V at TJ = 25 °C
• Simplifies meeting customer derating requirements
(e.g. 80%)
• Extended line surge withstand
Fast AC reset
Table 3.
3 external transistor circuits
using the V pin
1 external transistor circuit
using the X pin
• Saves 5 components
Comparison Between TOPSwitch-HX and TOPSwitch-JX.
6. Power levels shown in the power table for the V package
device assume 6.45 cm2 of 610 g/m2 copper heat sink area
in an enclosed adapter, or 19.4 cm2 in an open frame.
The provided peak power depends on the current limit for the
respective device.
TOP264-271 Selection
Selecting the optimum TOP264-271 depends upon required
maximum output power, efficiency, heat sinking constraints,
system requirements and cost goals. With the option to
externally reduce current limit, TOP264-271 may be used for
lower power applications where higher efficiency is needed or
minimal heat sinking is available.
Input Capacitor
The input capacitor must be chosen to provide the minimum
DC voltage required for the TOP264-271 converter to maintain
regulation at the lowest specified input voltage and maximum
output power. Since TOP264-271 has a high DCMAX limit and an
optimized dual slope line feed forward for ripple rejection, it is
possible to use a smaller input capacitor. For TOP264-271, a
capacitance of 2 mF per watt is possible for universal input with
an appropriately designed transformer.
Primary Clamp and Output Reflected Voltage VOR
A primary clamp is necessary to limit the peak TOP264-271 drain
to source voltage. A Zener clamp requires few parts and takes
up little board space. For good efficiency, the clamp Zener
should be selected to be at least 1.5 times the output reflected
voltage VOR, as this keeps the leakage spike conduction time
short. When using a Zener clamp in a universal input application,
a VOR of less than 135 V is recommended to allow for the absolute
tolerances and temperature variations of the Zener. This will
ensure efficient operation of the clamp circuit and will also keep
the maximum drain voltage below the rated breakdown voltage
of the TOP264-271 MOSFET. A high VOR is required to take full
advantage of the wider DCMAX of TOP264-271. An RCD (or
RCDZ) clamp provides tighter clamp voltage tolerance than a
Zener clamp and allows a VOR as high as 150 V. RCD clamp
dissipation can be minimized by reducing the external current
limit as a function of input line voltage (see Figure 19). The RCD
clamp is more cost effective than the Zener clamp but requires
more careful design (see Quick Design Checklist).
Output Diode
The output diode is selected for peak inverse voltage, output
current, and thermal conditions in the application (including heat
sinking, air circulation, etc.). The higher DCMAX of TOP264-271,
along with an appropriate transformer turns ratio, can allow the
use of a 80 V Schottky diode for higher efficiency on output
voltages as high as 15 V.
Bias Winding Capacitor
Due to the low frequency operation at no-load, a bias winding
capacitance of 10 mF minimum is recommended. Ensure a
minimum bias winding voltage of >9 V at zero load for correct
operation and output voltage regulation.
Soft-Start
Generally, a power supply experiences maximum stress at
start-up before the feedback loop achieves regulation. For a
period of 17 ms, the on-chip soft-start linearly increases the
drain peak current and switching frequency from their low
starting values to their respective maximum values. This
causes the output voltage to rise in an orderly manner, allowing
time for the feedback loop to take control of the duty cycle.
This reduces the stress on the TOP264-271 MOSFET, clamp
circuit and output diode(s), and helps prevent transformer
saturation during start-up. Also, soft-start limits the amount of
output voltage overshoot and, in many applications, eliminates
the need for a soft-finish capacitor. Note that as soon as the
loop closes the soft-start function ceases even if this is prior to
the end of the 17 ms soft-start period.
EMI
The frequency jitter feature modulates the switching frequency
over a narrow band as a means to reduce conducted EMI peaks
associated with the harmonics of the fundamental switching
19
www.powerint.com
Rev. E 10/11
TOP264-271
Standby Consumption
Frequency reduction can significantly reduce power loss at light
or no-load, especially when a Zener clamp is used. For very
low secondary power consumption, use a TL431 regulator for
feedback control. A typical TOP264-271 circuit automatically
enters MCM mode at no-load and the low frequency mode at
light load, which results in extremely low losses under no-load
or standby conditions.
High Power Designs
The TOP264-271 family contains parts that can deliver up to
162 W. High power designs need special considerations.
Guidance for high power designs can be found in the Design
Guide for TOP264-271 (AN-47).
70
60
40
30
20
-10
EN55022B (QP)
EN55022B (AV)
-10
-20
0.15
1
10
Frequency (MHz)
80
70
TOPSwitch-JX (with jitter)
60
50
40
30
20
-10
0
EN55022B (QP)
EN55022B (AV)
-10
-20
0.15
1
10
Frequency (MHz)
Figure 28. TOPSwitch-JX Full Range EMI Scan (132 kHz With Jitter) With Identical Circuitry and Conditions.
20
Rev. E 10/11
30
Figure 27. Fixed Frequency Operation Without Jitter.
Amplitude (dBµV)
Primary Side Connections
Use a single point (Kelvin) connection at the negative terminal of
the input filter capacitor for the SOURCE pin and bias winding
return. This improves surge capabilities by returning surge
currents from the bias winding directly to the input filter capacitor.
The CONTROL pin bypass capacitor should be located as
close as possible to the SOURCE and CONTROL pins, and its
SOURCE connection trace should not be shared by the main
MOSFET switching currents. All SOURCE pin referenced
components connected to the VOLTAGE MONITOR (V pin) or
EXTERNAL CURRENT LIMIT (X pin) pins should also be located
50
0
TOP264-271 Layout Considerations
The TOP264-271 has multiple pins and may operate at high
power levels. The following guidelines should be carefully
followed.
PI-2576-010600
80
PI-5583-090309
Transformer Design
It is recommended that the transformer be designed for
maximum operating flux density of 3000 Gauss and a peak flux
density of 4200 Gauss at maximum current limit. The turns ratio
should be chosen for a reflected voltage (VOR) no greater than
135 V when using a Zener clamp or 150 V (max) when using an
RCD clamp with current limit reduction with line voltage (overload
protection). For designs where operating current is significantly
lower than the default current limit, it is recommended to use an
externally set current limit close to the operating peak current to
reduce peak flux density and peak power (see Figure 18).
closely between their respective pin and SOURCE. Once again,
the SOURCE connection trace of these components should not
be shared by the main MOSFET switching currents. It is very
critical that SOURCE pin switching currents are returned to the
input capacitor negative terminal through a separate trace that is
not shared by the components connected to CONTROL,
VOLTAGE MONITOR or EXTERNAL CURRENT LIMIT pins. This
is because the SOURCE pin is also the controller ground
reference pin. Any traces to the V, X or C pins should be kept
as short as possible and away from the DRAIN trace to prevent
noise coupling. VOLTAGE MONITOR resistors (RLS in Figures
14, 15, 19, 22, 23, 26, 30) and primary side OVP circuit
components V ZOV/ROV in Figures (29, 30) should be located
close to the V pin to minimize the trace length on the V pin side.
Resistors connected to the V or X pin should be connected as
close to the bulk cap positive terminal as possible while routing
these connections away from the power switching circuitry. In
addition to the 47 μF CONTROL pin capacitor, a high frequency
bypass capacitor (CBP) in parallel should be used for better noise
immunity. The feedback optocoupler output should also be
Amplitude (dBµV)
frequency. This is particularly beneficial for average detection
mode. As can be seen in Figures 27 and 28, the benefits of jitter
increase with the order of the switching harmonic due to an
increase in frequency deviation. The FREQUENCY pin offers a
switching frequency option of 132 kHz or 66 kHz. In applications
that require heavy snubber on the drain node for reducing high
frequency radiated noise (for example, video noise sensitive
applications such as VCRs, DVDs, monitors, TVs, etc.), operating
at 66 kHz will reduce snubber loss, resulting in better efficiency.
Also, in applications where transformer size is not a concern, use
of the 66 kHz option will provide lower EMI and higher efficiency.
Note that the second harmonic of 66 kHz is still below 150 kHz,
above which the conducted EMI specifications get much tighter.
For 10 W or below, it is possible to use a simple inductor in place
of a more costly AC input common mode choke to meet
worldwide conducted EMI limits.
www.powerint.com
30
TOP264-271
located close to the CONTROL and SOURCE pins of TOP264-271
and away from the drain and clamp component traces. The
primary side clamp circuit should be positioned such that the loop
area from the transformer end (shared with DRAIN) and the clamp
capacitor is minimized. The bias winding return node should be
connected via a dedicated trace directly to the bulk capacitor
and not to the SOURCE pins. This ensures that surge currents
are routed away from the SOURCE pins of the TOPSwitch-JX.
Y Capacitor
The Y capacitor should be connected close to the secondary
output return pin(s) and the positive primary DC input pin of the
transformer. If the Y capacitor is returned to the negative end of
the input bulk capacitor (rather than the positive end) a dedicated
trace must be used to make this connection. This is to “steer”
leakage currents away from the SOURCE pins in case of a
common-mode surge event.
Heat Sinking
The exposed pad of the E package (eSIP-7C), K package
(eSOP-12) and the V package (eDIP-12) are internally electrically
tied to the SOURCE pin. To avoid circulating currents, a heat
sink attached to the exposed pad should not be electrically tied
to any primary ground/source nodes on the PC board. On
double sided boards, topside and bottom side areas connected
with vias can be used to increase the effective heat sinking
area. The K package exposed pad may be directly soldered to
a copper area for optimum thermal transfer. In addition,
sufficient copper area should be provided at the anode and
cathode leads of the output diode(s) for heat sinking. In Figure 29,
a narrow trace is shown between the output rectifier and output
filter capacitor. This trace acts as a thermal relief between the
rectifier and filter capacitor to prevent excessive heating of the
capacitor.
Quick Design Checklist
In order to reduce the no-load input power of TOP264-271
designs, the V pin operates at very low current. This requires
careful layout considerations when designing the PCB to avoid
noise coupling. Traces and components connected to the V pin
should not be adjacent to any traces carrying switching currents.
These include the drain, clamp network, bias winding return or
power traces from other converters. If the line sensing features
are used, then the sense resistors must be placed within 10 mm
of the V pin to minimize the V pin node area. The DC bus
should then be routed to the line sense resistors. Note that
external capacitance must not be connected to the V pin as this
may cause misoperaton of the V pin related functions. As with
any power supply design, all TOP264-271 designs should be
verified on the bench to make sure that components specifications are not exceeded under worst-case conditions. The
following minimum set of tests is strongly recommended:
1. Maximum drain voltage – Verify that peak VDS does not
exceed 675 V at highest input voltage and maximum
overload output power. Maximum overload output power
occurs when the output is overloaded to a level just before
the power supply goes into auto-restart (loss of regulation).
2. Maximum drain current – At maximum ambient temperature,
maximum input voltage and maximum output load, verify
drain current waveforms at start-up for any signs of transformer saturation and excessive leading edge current spikes.
TOP264-271 has a leading edge blanking time of 220 ns to
prevent premature termination of the ON-cycle. Verify that
the leading edge current spike is below the allowed current
limit envelope (see Figure 34) for the drain current waveform
at the end of the 220 ns blanking period.
3. Thermal check – At maximum output power, both minimum
and maximum voltage and ambient temperature; verify that
temperature specifications are not exceeded for TOP264271, transformer, output diodes and output capacitors.
Enough thermal margin should be allowed for the part-topart variation of the RDS(ON) of TOP264-271, as specified in
the data sheet. The margin required can either be calculated
from the values in the parameter table or it can be accounted
for by connecting an external resistance in series with the
DRAIN pin and attached to the same heat sink, having a
resistance value that is equal to the difference between the
measured RDS(ON) of the device under test and the worst case
maximum specification.
Design Tools
Up-to-date information on design tools can be found at the
Power Integrations website: www.powerint.com
21
www.powerint.com
Rev. E 10/11
TOP264-271
DC
– OUT
+
Maximize Copper Area
for Optimum Heat Sinking
RLS1
J2
RPL1
CB
U1
RLS2
RPL2
ROV
U2
U3
T1
DB
C16
VZOV
R12
RIL
CBP
C18
Output Filter
Capacitors
R16
Transformer
C10
L2
C17
Output
Rectifiers
D8
–
J1
HF LC
Post-Filter
D5
+
DC
IN
VR1
C3
C4
D9
R5
YCapacitor
C11
Clamp Circuit
Input Filter
Capacitor
PI-5752-061311
Figure 29. Layout Considerations for TOPSwitch-JX Using V Package and Operating at 132 kHz.
DC
– OUT
+
Maximize Copper Area
for Optimum Heat Sinking
RLS1
J2
RPL1
U1
RLS2
RPL2
CB+
ROV
U2
U3
T1
DB
VZOV
R12
RIL
RIL
CBP
Output Filter
Capacitors
CBP R16
C16
C18
Transformer
C10
Output
Rectifiers
L2
C17
D8
–
J1
HF LC
Post-Filter
D5
+
DC
IN
C4
Input Filter
Capacitor
C3
D9
R5
VR1
YCapacitor
C11
Clamp Circuit
PI-6173-061311
Figure 30. Layout Considerations for TOPSwitch-JX Using K Package and Operating at 132 kHz.
22
Rev. E 10/11
www.powerint.com
TOP264-271
Clamp
Circuit
Isolation Barrier
Input Filter
Capacitor
+
HV
-
J1
YCapacitor
C6 R7
T1
R6
HS1
C16
R12
D5
C4
D8
HS2
CBP
S
D
C9
F
X
C
RLS2
Transformer
VR1
U1
Output Filter
Capacitors
C17
RIL
L3
V
HF LC
Post-Filter
RLS1
RPL1
ROV
R8
RPL2
VZOV
Output
Rectifier
CB
DB
C18
U4
R10
R9
JP2
C19
C21
R20
J2
R17
U2
R13
R15
R21
- DC +
OUT
PI-5793-030910
Figure 31. Layout Considerations for TOPSwitch-JX Using E Package and Operating at 132 kHz.
23
www.powerint.com
Rev. E 10/11
TOP264-271
Absolute Maximum Ratings(2)
DRAIN Pin Peak Voltage...................................... -0.3 V to 725 V
DRAIN Pin Peak Current: TOP264.................................... 2.08 A
DRAIN Pin Peak Current: TOP265.................................... 2.72 A
DRAIN Pin Peak Current: TOP266.................................... 4.08 A
DRAIN Pin Peak Current: TOP267.................................... 5.44 A
DRAIN Pin Peak Current: TOP268.................................... 6.88 A
DRAIN Pin Peak Current: TOP269.................................... 7.73 A
DRAIN Pin Peak Current: TOP270.................................... 9.00 A
DRAIN Pin Peak Current: TOP271.................................. 11.10 A
CONTROL Pin Voltage............................................. -0.3 V to 9 V
CONTROL Pin Current................................................... 100 mA
VOLTAGE MONITOR Pin Voltage............................ -0.3 V to 9 V
CURRENT LIMIT Pin Voltage............................... -0.3 V to 4.5 V
FREQUENCY Pin Voltage ......................................-0.3 V to 9 V
Storage Temperature .......................................-65 °C to 150 °C
Operating Junction Temperature.......................-40 °C to 150 °C
Lead Temperature(1).........................................................260 °C
Notes:
1. 1/16 in. from case for 5 seconds.
2. Maximum ratings specified may be applied one at a time without causing permanent damage to the product. Expo
sure to Absolute Maximum Rating conditions for extended
periods of time may affect product reliability.
Thermal Resistance
Thermal Resistance: E Package
(qJA)........................................... 105 °C/W(1)
(qJC)............................................... 2 °C/W(2)
V Package
(qJA)............................68 °C/W(3), 58 °C/W(4)
(qJC)............................................... 2 °C/W(2)
K Package
(qJA) ...........................45 °C/W(3), 38 °C/W(4)
(qJC)............................................... 2 °C/W(2)
Parameter
Symbol
Notes:
1. Free standing with no heat sink.
2. Measured at the back surface of tab.
3. Soldered (including exposed pad for K package) to typical
application PCB with a heat sinking area of 0.36 sq. in.
(232mm2), 2 oz. (610 g/m2) copper clad.
4. Soldered (including exposed pad for K package) to typical
application PCB with a heat sinking area of 1 sq. in. (645 mm2),
2 oz. (610 g/m2) copper clad.
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 35
(Unless Otherwise Specified)
Min
Typ
Max
119
132
145
59.4
66
72.6
Units
Control Functions
Switching Frequency
in Full Frequency
Mode (average)
fOSC
Frequency Jitter
Deviation
Df
Frequency Jitter
Modulation Rate
fM
Maximum Duty Cycle
Soft-Start Time
PWM Gain
DCMAX
TJ = 25 °C
IC = ICD1
tSOFT
DCREG
PWM Gain
Temperature Drift
External Bias Current
FREQUENCY Pin
Connected to SOURCE
FREQUENCY Pin
Connected to CONTROL
132 kHz Operation
66 kHz Operation
IV ≤ IV(DC)
VV = 0 V
75
IV = 95 mA
30
TJ = 25 °C
IB
±5
±2.5
kHz
250
Hz
78
83
17
TOP264-265
-62
-50
-40
TOP266-268
-54
-44
-34
TOP269-271
-50
-40
-30
TJ = 25 °C
IC ≥ IC01
See Note A
TOP264-265
-61
-51
-41
TOP266-268
-60
-50
-40
TOP269-271
-57
-48
-38
66 kHz Operation
%
ms
TJ = 25 °C
IB < IC < IC01
See Note C
See Note B
kHz
-0.01
%/mA
%/mA/°C
TOP264-265
0.8
1.4
2.0
TOP266-268
0.9
1.5
2.1
TOP269-271
1.0
1.6
2.2
mA
24
Rev. E 10/11
www.powerint.com
TOP264-271
Parameter
Symbol
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
0.9
1.2
1.5
1.5
1.8
2.1
2.9
3.1
3.3
3.1
3.4
3.8
2.1
2.4
2.8
3.9
4.1
4.3
4.1
4.4
4.8
21
25
Units
Control Functions (cont.)
External Bias Current
IB
132 kHz Operation
66 kHz Operation
CONTROL Current at
0% Duty Cycle
IC(OFF)
132 kHz Operation
Dynamic Impedance
ZC
TOP264-265
TOP266-268
TOP269-271
TOP264-265
TOP266-268
TOP269-271
TOP264-265
TOP266-268
TOP269-271
IC = 2.5 mA; TJ = 25 °C, See Figure 33
13
Dynamic Impedance
Temperature Drift
CONTROL Pin Internal
Filter Pole
mA
mA
W
0.18
%/°C
7
kHz
Upper Peak Current to
Set Current Limit Ratio
kPS(UPPER)
TJ = 25 °C
See Note C
Lower Peak Current to
Set Current Limit Ratio
kPS(LOWER)
TJ = 25 °C
See Note C
25
%
Multi-CycleModulation Switching
Frequency
fMCM(MIN)
TJ = 25 °C
30
kHz
Minimum Multi-CycleModulation On Period
TMCM(MIN)
TJ = 25 °C
135
ms
50
55
60
%
Shutdown/Auto-Restart
CONTROL Pin
Charging Current
IC(CH)
TJ = 25 °C
Charging Current
Temperature Drift
VC = 0 V
-5.0
-3.5
-1.0
VC = 5 V
-3.0
-1.8
-0.6
See Note B
Auto-Restart
Upper Threshold
Voltage
VC(AR)U
Auto-Restart Lower
Threshold Voltage
VC(AR)L
mA
0.5
%/°C
5.8
V
4.5
4.8
0.8
1.0
5.1
V
Voltage Monitor (V) and External Current Limit (X) Inputs
Auto-Restart
Hysteresis Voltage
VC(AR)HYST
Auto-Restart
Duty Cycle
DCAR
2
Auto-Restart
Frequency
fAR
0.5
Line Undervoltage
Threshold Current and
Hysteresis (V Pin)
IUV
TJ = 25 °C
Line Overvoltage
Threshold Current and
Hysteresis (V Pin)
IOV
TJ = 25 °C
Threshold
22
Hysteresis
Threshold
Hysteresis
25
V
4
Hz
27
14
107
112
4
%
mA
mA
117
mA
mA
25
www.powerint.com
Rev. E 10/11
TOP264-271
Parameter
Symbol
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
Voltage Monitor (V) and External Current Limit (X) Inputs (cont.)
Output Overvoltage
Latching Shutdown
Threshold Current
IOV(LS)
TJ = 25 °C
269
336
403
mA
V Pin Remote
ON/OFF Voltage
VV(TH)
TJ = 25 °C
0.8
1.0
1.6
V
X Pin Remote ON/OFF
and Latch Reset
Negative Threshold
Current and Hysteresis
-35
-27
-20
IREM(N)
V Pin Short-Circuit
Current
IV(SC)
TJ = 25 °C
X Pin Short-Circuit
Current
IX(SC)
VX = 0 V
VV
IV = IOV
V Pin Voltage
(Positive Current)
V Pin Voltage Hysteresis
(Positive Current)
X Pin Voltage
(Negative Current)
Maximum Duty Cycle
Reduction Onset
Threshold Current
Threshold
TJ = 25 °C
mA
Hysteresis
VV = VC
300
400
500
Normal Mode
-260
-200
-140
Auto-Restart Mode
-95
-75
-55
TOP264-TOP271
2.83
3.0
3.25
IV = IOV
0.2
0.5
IX = -50 mA
1.23
1.30
1.37
IX = -150 mA
1.15
1.22
1.29
18.9
22.0
24.2
VV(HYST)
VX
IV(DC)
Maximum Duty Cycle
Reduction Slope
IC ≥ IB, TJ = 25 °C
TJ = 25 °C
5
-1.0
IV ≥48 mA
-0.25
X or V Pin Floating
0.6
1.0
V Pin Shorted to
CONTROL
1.0
1.6
ID(RMT)
VDRAIN = 150 V
Remote-ON Delay
tR(ON)
From Remote-ON to Drain
Turn-On
See Note C
Remote-OFF
Set-up Time
tR(OFF)
Minimum Time Before Drain
Turn-On to Disable Cycle
See Note C
mA
V
V
IV(DC) < IV <48 mA
Remote-OFF DRAIN
Supply Current
mA
V
mA
%/mA
mA
66 kHz
3.0
132 kHz
1.5
66 kHz
3.0
132 kHz
1.5
ms
ms
Frequency Input
FREQUENCY Pin
Threshold Voltage
VF
FREQUENCY Pin
Input Current
IF
See Note B
TJ = 25 °C
2.9
VF = VC
10
55
V
90
mA
26
Rev. E 10/11
www.powerint.com
TOP264-271
Parameter
Symbol
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
Circuit Protection
Self Protection
Current Limit
(See Note C)
ILIMIT
Initial Current Limit
IINIT
Power Coefficient
PCOEFF
Leading Edge
Blanking Time
tLEB
Current Limit Delay
tIL(D)
TOP264
TJ = 25 °C
di/dt = 270 mA/ms
1.209
1.30
1.391
TOP265
TJ = 25 °C
di/dt = 350 mA/ms
1.581
1.70
1.819
TOP266
TJ = 25 °C
di/dt = 530 mA/ms
2.371
2.55
2.728
TOP267
TJ = 25 °C
di/dt = 625 mA/ms
2.800
3.01
3.222
TOP268
TJ = 25 °C
di/dt = 675 mA/ms
3.023
3.25
3.478
TOP269
TJ = 25 °C
di/dt = 720 mA/ms
3.236
3.48
3.723
TOP270
TJ = 25 °C
di/dt = 870 mA/ms
3.906
4.20
4.494
TOP271
TJ = 25 °C
di/dt = 1065 mA/ms
4.808
5.17
5.532
A
See Note C
TJ = 25 °C,
See Note E
0.70 ×
ILIMIT(MIN)
IX ≤ - 165 mA
0.9 × I2f
I2f
1.2 × I2f
IX ≤ - 117 mA
0.9 × I2f
I2f
1.2 × I2f
TJ = 25 °C, See Figure 34
Thermal Shutdown
Temperature
135
Thermal Shutdown
Hysteresis
Power-Up Reset
Threshold Voltage
A
220
ns
100
ns
142
150
75
VC(RESET)
Figure 35 (S1 Open Condition)
1.75
A2kHz
3.0
°C
°C
4.25
V
27
www.powerint.com
Rev. E 10/11
TOP264-271
Parameter
Symbol
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
Output
ON-State
Resistance
RDS(ON)
TOP264
ID = 150 mA
TJ = 25 °C
5.4
6.25
TJ = 100 °C
8.35
9.70
TOP265
ID = 200 mA
TJ = 25 °C
4.1
4.70
TJ = 100 °C
6.3
7.30
TOP266
ID = 300 mA
TJ = 25 °C
2.8
3.20
TJ = 100 °C
4.1
4.75
TOP267
ID = 400 mA
TJ = 25 °C
2.0
2.30
TJ = 100 °C
3.1
3.60
TOP268
ID = 500 mA
TJ = 25 °C
1.7
1.95
TJ = 100 °C
2.5
2.90
TOP269
ID = 600 mA
TJ = 25 °C
1.45
1.70
TJ = 100 °C
2.25
2.60
TOP270
ID = 700 mA
TJ = 25 °C
1.20
1.40
TJ = 100 °C
1.80
2.10
TJ = 25 °C
1.05
1.20
1.55
1.80
TOP271
ID = 800 mA
DRAIN Supply Voltage
OFF-State Drain
Leakage Current
Breakdown
Voltage
TJ = 100 °C
TJ ≤ 85 °C, See Note F
18
V
36
IDSS
VV = Floating, Device Not Switching,
VDS = 580 V, TJ = 125 °C
BVDSS
VV = Floating, Device Not Switching,
TJ = 25 °C, See Note G
Rise Time
tR
Fall Time
tF
470
mA
V
725
Measured in a Typical Flyback
Converter Application
W
100
ns
50
ns
Supply Voltage Characteristics
Control Supply/
Discharge Current
ICD1
ICD2
Output
MOSFET
Enabled
VX, VV =
0V
66 kHz
Operation
132 kHz
Operation
TOP264-265
0.6
1.2
2.0
TOP266-268
0.9
1.4
2.3
TOP269-271
1.1
1.6
2.5
TOP264-265
0.8
1.4
2.1
TOP266-268
1.2
1.7
2.4
TOP269-271
1.5
2.1
2.9
0.3
0.5
1.2
Output MOSFET Disabled
VX, VV = 0 V
mA
28
Rev. E 10/11
www.powerint.com
TOP264-271
NOTES:
A. Derived during test from the parameters DCMAX, IB and IC(OFF) at 132 kHz.
B. For specifications with negative values, a negative temperature coefficient corresponds to an increase in magnitude with increasing temperature, and a positive temperature coefficient corresponds to a decrease in magnitude with increasing temperature.
C. Guaranteed by characterization. Not tested in production.
D. For externally adjusted current limit values, please refer to Figures 36 and 37 (Current Limit vs. External Current Limit Resistance)
in the Typical Performance Characteristics section. The tolerance specified is only valid at full current limit.
E. I2f calculation is based on typical values of ILIMIT and fOSC, i.e. ILIMIT(TYP)2 × fOSC, where fOSC = 66 kHz or 132 kHz depending on F pin
connection. See fOSC specification for detail.
F. The device will start up at 18 VDC drain voltage. The capacitance of electrolytic capacitors drops significantly at temperatures
below 0 °C. For reliable start up at 18 V in sub zero temperatures, designers must ensure that circuit capacitors meet recommended capacitance values.
G. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up to but not
exceeding minimum BVDSS.
29
www.powerint.com
Rev. E 10/11
TOP264-271
t2
HV
t1
90%
90%
DRAIN
VOLTAGE
D=
t1
t2
10%
0V
PI-2039-033001
100
DRAIN Current (normalized)
PI-4737-061207
CONTROL Pin Current (mA)
120
80
60
40
Dynamic
1
=
Impedance Slope
20
0
5
6
7
8
PI-4758-061407
Figure 32. Duty Cycle Measurement.
tLEB (Blanking Time)
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
IINIT(MIN)
0
9
0
1
2
3
CONTROL Pin Voltage (V)
4
5
6
7
8
Time (µs)
Figure 33. CONTROL Pin I-V Characteristic.
Figure 34. Drain Current Operating Envelope.
(X and V Pins)
S1
470 Ω
5W
0-300 kΩ
5-50 V
40 V
V
470 Ω
C
D
CONTROL
C
S2
S4
0-15 V
47 µF
0.1 µF
F
X
S
S3
0-60 kΩ
NOTES: 1. This test circuit is not applicable for current limit or output characteristic measurements.
PI-5534-072409
Figure 35. TOPSwitch-JX General Test Circuit.
30
Rev. E 10/11
www.powerint.com
TOP264-271
Typical Performance Characteristics
PI-5581-090309
1.1
1
1
Maximum
0.9
0.9
0.8
0.8
0.7
0.7
Typical
0.6
0.6
0.5
0.5
Minimum
0.4
0.4
Normalized
Current Limit
0.3
2. T J = 0
0.1
O
C to 125
O
t
0.3
Notes:
1. Maximum and Minimum levels are
based on characterization.
0.2
Normalized di/dt
Normalized Current Limit
1.1
0.2
C.
0.1
0
0
-200
-150
-100
-50
0
I X ( µA )
Figure 36. Normalized Current Limit vs. X Pin Current.
PI-5582-090309
1.1
Notes:
1. Maximum and Minimum levels are
based on characterization.
1
1
2. T J = 0 OC to 125 OC.
3. Includes the variation of X pin voltage.
0.9
0.9
0.8
0.8
s)
µ
Maximum
0.7
0.7
0.6
0.6
Typical
0.5
0.5
0.4
0.4
0.3
Normalized
Current Limit (A)
Normalized di/dt
Normalized Current Limit
1.1
0.3
0.2
Normalized di
0.2
Minimum
0.1
0.1
0
0
0
5
10
15
20
25
30
35
40
45
RIL ( kΩ )
Figure 37. Normalized Current Limit vs. External Current Limit Resistance.
31
www.powerint.com
Rev. E 10/11
TOP264-271
Typical Performance Characteristics (cont.)
1.0
PI-4759-061407
1.2
Output Frequency
(Normalized to 25 °C)
PI-176B-033001
1.0
0.8
0.6
0.4
0.2
0
0.9
-50 -25
0
25
50
-50 -25
75 100 125 150
0.6
0.4
0.2
0.8
0.6
0.4
0.2
0
50
75 100 125 150
Junction Temperature (°C)
Figure 40. Internal Current Limit vs. Temperature.
PI-4761-061407
Overvoltage Threshold
(Normalized to 25 °C)
1.2
1.0
-50 -25
0
25
50
75 100 125 150
Junction Temperature (ϒC)
Figure 41. External Current Limit vs. Temperature with RIL = 10.5 kW.
0.8
0.6
0.4
0.2
1.2
Undervoltage Threshold
(Normalized to 25 °C)
25
PI-4739-061507
1.0
0
0
75 100 125 150
1.2
Current Limit
(Normalized to 25 ϒC)
0.8
-50 -25
50
Figure 39. Frequency vs. Temperature.
PI-4760-061407
Current Limit
(Normalized to 25 °C)
1.0
25
Junction Temperature (°C)
Junction Temperature (°C)
Figure 38. Breakdown Voltage vs. Temperature.
1.2
0
PI-4762-100610
Breakdown Voltage
(Normalized to 25 °C)
1.1
1.0
0.8
0.6
0.4
0.2
0
0
-50 -25
0
25
50
75 100 125 150
Junction Temperature (°C)
Figure 42. Overvoltage Threshold vs. Temperature.
-50 -25
0
25
50
75 100 125 150
Junction Temperature (°C)
Figure 43. Undervoltage Threshold vs. Temperature.
32
Rev. E 10/11
www.powerint.com
TOP264-271
4.5
4
3.5
3
2.5
200
300
400
VOLTAGE-MONITOR Pin Current (µA)
0.8
0.6
0.4
0.2
0
-200
-100
-50
0
Figure 45. EXTERNAL CURRENT LIMIT Pin Voltage vs. Current.
PI-4763-072208
1.2
1.0
0.8
0.6
0.4
0.2
1.2
1.0
0.8
0.6
0.4
0.2
0
0
0
25
50
-50 -25
75 100 125 150
PI-5569-110409
4
3
2
1
TCASE = 25 °C
TCASE = 100 °C
Scaling Factors:
TOP271 1.62
TOP270 1.42
TOP269 1.17
TOP268 1.00
TOP267 0.85
TOP266 0.61
TOP265 0.42
TOP264 0.32
0
0
2
4
6
8 10 12 14 16 18 20
Drain Voltage (V)
Figure 48. Output Characteristics.
25
50
75 100 125 150
Figure 47. Maximum Duty Cycle Reduction Onset Threshold
Current vs. Temperature.
1
CONTROL Pin Current (mA)
Figure 46. Control Current Out at 0% Duty Cycle vs. Temperature.
5
0
Junction Temperature (°C)
Junction Temperature (°C)
PI-4744-072208
-50 -25
DRAIN Current (A)
-150
EXTERNAL CURRENT LIMIT Pin Current (µA)
Figure 44. VOLTAGE-MONITOR Pin vs. Current.
CONTROL Current
(Normalized to 25 °C)
1.0
500
Onset Threshold Current
(Normalized to 25 °C)
100
VX = 1.354 - 1147.5 × IX + 1.759 × 106 ×
(IX)2 with -180 µA < IX < -25 µA
1.2
2
0
PI-4741-110907
5
1.4
PI-4764-061407
5.5
1.6
EXTERNAL CURRENT LIMIT
Pin Voltage (V)
6
PI-4740-060607
VOLTAGE MONITOR Pin Voltage (V)
Typical Performance Characteristics (cont.)
VC = 5 V
0.5
0
-0.5
-1
-1.5
-2
-2.5
0
20
40
60
80
100
Drain Pin Voltage (V)
Figure 49. IC vs. DRAIN Voltage.
33
www.powerint.com
Rev. E 10/11
TOP264-271
Typical Performance Characteristics (cont.)
1000
Scaling Factors:
TOP271 1.62
TOP270 1.42
TOP269 1.17
TOP268 1.00
TOP267 0.85
TOP266 0.61
TOP265 0.42
TOP264 0.32
400
100
300
PI-5571-090309
500
Power (mW)
Scaling Factors:
TOP271 1.62
TOP270 1.42
TOP269 1.17
TOP268 1.00
TOP267 0.85
TOP266 0.61
TOP265 0.42
TOP264 0.32
PI-5570-090309
DRAIN Capacitance (pF)
10000
132 kHz
200
66 kHz
100
10
0
100
200
300
400
500
0
600
0
100 200 300 400 500 600 700
Drain Pin Voltage (V)
Drain Pin Voltage (V)
Figure 51. DRAIN Capacitance Power.
1.2
PI-4745-061407
Remote OFF DRAIN Supply Current
(Normalized to 25 °C)
Figure 50. COSS vs. DRAIN Voltage.
1.0
0.8
0.6
0.4
0.2
0
-50 -25
0
25
50
75 100 125 150
Junction Temperature (°C)
Figure 52. Remote OFF DRAIN Supply Current vs. Temperature.
34
Rev. E 10/11
www.powerint.com
TOP264-271
eSIP-7C (E Package)
C
2
A
0.403 (10.24)
0.397 (10.08)
0.264 (6.70)
Ref.
0.081 (2.06)
0.077 (1.96)
B
Detail A
2
0.290 (7.37)
Ref.
0.519 (13.18)
Ref.
0.325 (8.25)
0.320 (8.13)
Pin #1
I.D.
0.140 (3.56)
0.120 (3.05)
3
0.207 (5.26)
0.187 (4.75)
0.016 (0.41)
Ref.
3
0.047 (1.19)
0.070 (1.78) Ref.
0.050 (1.27)
0.198 (5.04) Ref.
0.016 (0.41) 6×
0.011 (0.28)
0.020 M 0.51 M C
FRONT VIEW
0.118 (3.00)
SIDE VIEW
4
0.033 (0.84) 6×
0.028 (0.71)
0.010 M 0.25 M C A B
0.100 (2.54)
BACK VIEW
0.100 (2.54)
10° Ref.
All Around
0.021 (0.53)
0.019 (0.48)
0.050 (1.27)
0.020 (0.50)
0.060 (1.52)
Ref.
0.050 (1.27)
PIN 1
0.378 (9.60)
Ref.
0.048 (1.22)
0.046 (1.17)
0.019 (0.48) Ref.
0.059 (1.50)
0.155 (3.93)
0.023 (0.58)
END VIEW
PIN 7
0.027 (0.70)
0.059 (1.50)
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions noted are determined at the outermost
extremes of the plastic body exclusive of mold flash,
tie bar burrs, gate burrs, and interlead flash, but including
any mismatch between the top and bottom of the plastic
body. Maximum mold protrusion is 0.007 [0.18] per side.
DETAIL A
0.100 (2.54)
0.100 (2.54)
MOUNTING HOLE PATTERN
(not to scale)
3. Dimensions noted are inclusive of plating thickness.
4. Does not include inter-lead flash or protrusions.
5. Controlling dimensions in inches (mm).
PI-4917-061510
35
www.powerint.com
Rev. E 10/11
TOP264-271
eDIP-12B (V Package)
0.004 [0.10] C A
Seating Plane
0.325 [8.26]
Max.
Pin #1 I.D.
(Laser Marked)
10
2X
0.004 [0.10] C B
1
2 3 4
0.010 [0.25] Ref.
0.120 [3.05]
Ref.
6
0.412 [10.46]
Ref.
0.306 [7.77]
Ref.
10
2
0.225 [5.72]
Max.
0.350 [8.89]
B
2
C
12 11 10 9 8
0.016 [0.41]
11×
0.011 [0.28]
6
TOP VIEW
0.104 [2.65] Ref.
5 °± 4°
0.059 [1.50]
Ref, typ.
12
3 4
0.023 [0.58]
11×
0.018 [0.46]
BOTTOM VIEW
0.092 [2.34]
0.086 [2.18]
0.049 [1.23]
0.046 [1.16]
0.022 [0.56]
Ref.
0.020 [0.51]
Ref.
0.070 [1.78]
SIDE VIEW
0.07 [1.78]
8
0.192 [4.87]
Ref.
H
0.031 [0.80]
0.028 [0.72]
0.059 [1.50]
Ref, typ.
0.010 [0.25] M C A B
END VIEW
0.019 [0.48]
Ref.
1
0.436 [11.08]
0.406 [10.32]
7
Detail A
A
7
0.400 [10.16]
7
0.356 [9.04]
Ref.
0.400 [10.16]
0.03 [0.76]
0.028 [0.71]
Ref.
DETAIL A (Scale = 9X)
Mounting
Hole Pattern
Dimensions
0.400 [10.16]
Drill Hole
0.03 [0.76]
Round Pad 0.05 [1.27]
Solder Mask 0.056 [1.42]
Notes:
1. Dimensioning and tolerancing per
ASME Y14.5M-1994.
2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of
mold flash, tie bar burrs, gate burrs, and interlead
flash, but including any mismatch between the
top and bottom of the plastic body. Maximum
mold protrusion is 0.007 [0.18] per side.
3. Dimensions noted are inclusive of plating
thickness.
4. Does not include inter-lead flash or protrusions.
5. Controlling dimensions in inches [mm].
6. Datums A and B to be determined at Datum H.
7. Measured with the leads constrained to be
perpendicular to Datum C.
8. Measured with the leads unconstrained.
9. Lead numbering per JEDEC SPP-012.
10. Exposed pad is nominally located at the centerline of Datums A and B. “Max” dimensions
noted include both size and positional tolerances.
PI-5556a-100311
36
Rev. E 10/11
www.powerint.com
TOP264-271
eSOP-12B (K Package)
0.356 [9.04]
Ref.
0.004 [0.10] C A 2X
2
0.400 [10.16]
Pin #1 I.D.
(Laser Marked)
0.325 [8.26]
Max. 7
2X
7
0.004 [0.10] C B
0.059 [1.50]
Ref, Typ
0.460 [11.68]
0.059 [1.50]
Ref, Typ
0.008 [0.20] C 1
2X, 5/6 Lead Tips
2
3
4
6
Gauge Plane
2
4
Seating Plane
0°- 8°
0.225 [5.72]
Max. 7
6
1
0.120 [3.05] Ref
BOTTOM VIEW
0.020 [0.51]
Ref.
0.092 [2.34]
0.086 [2.18]
0.032 [0.80]
0.029 [0.72]
0.006 [0.15]
0.000 [0.00]
Seating plane to
package bottom
standoff
0.004 [0.10] C
C
Seating
Plane
Detail A
0.217 [5.51]
0.022 [0.56]
Ref.
0.016 [0.41]
0.011 [0.28]
11×
END VIEW
Land Pattern
Dimensions
1
12
2
11
3
10
0.028 [0.71]
0.321 [8.15]
9
4
3
0.019 [0.48]
Ref.
0.306 [7.77]
Ref.
SIDE VIEW
0.067 [1.70]
0.049 [1.23]
0.046 [1.16]
0.028 [0.71]
Ref.
0.070 [1.78]
TOP VIEW
0.098 [2.49]
0.086 [2.18]
C
0.034 [0.85]
0.026 [0.65]
DETAIL A (Scale = 9X)
B
3
H
0.010 [0.25]
12
0.350 [8.89]
0.023 [0.58]
11×
0.018 [0.46]
0.010 (0.25) M C A B
0.010 [0.25]
Ref.
0.055 [1.40] Ref.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions noted are determined at the outermost
extremes of the plastic body exclusive of mold flash,
tie bar burrs, gate burrs, and interlead flash, but
including any mismatch between the top and bottom of
the plastic body. Maximum mold protrusion is 0.007
[0.18] per side.
3. Dimensions noted are inclusive of plating thickness.
4. Does not include interlead flash or protrusions.
5. Controlling dimensions in inches [mm].
6
0.429 [10.90]
8
6. Datums A and B to be determined at Datum H.
7
7. Exposed pad is nominally located at the centerline of
Datums A and B. “Max” dimensions noted include both
size and positional tolerances.
PI-5748a-100311
37
www.powerint.com
Rev. E 10/11
TOP264-271
Part Ordering Information
• TOPSwitch Product Family
• JX Series Number
• Package Identifier
E
Plastic eSIP-7C
V
Plastic eDIP-12
K
Plastic eSOP-12
• Pin Finish
G
Halogen Free and RoHS Compliant
• Tape & Reel and Other Options
TOP 264
E
G - TL
Blank
Standard Configurations
38
Rev. E 10/11
www.powerint.com
TOP264-271
Revision
A
B
B
B
C
D
E
Notes
Date
Release data sheet.
Added eDIP parts.
Page 4 “latching” changed to “hysteretic”. Table 3 updated.
Sentence in ‘Line Sense Resistor Values’ section updated.
Added K package parts.
Updated K and V package drawings.
Added eDIP-12B and eSOP-12B packages. Removed eDIP-12 and eSOP-12 packages.
01/10
01/10
03/10
07/10
11/10
06/11
10/11
39
www.powerint.com
Rev. E 10/11
For the latest updates, visit our website: www.powerint.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power
Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES
NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered
by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A
complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under
certain patent rights as set forth at http://www.powerint.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant
injury or death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS, HiperTFS, HiperLCS,
Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other
trademarks are property of their respective companies. ©2011, Power Integrations, Inc.
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