K7Z167288B K7Z163688B Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM Document Title 512Kx36 & 256Kx72 DLW(Double Late Write) RAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. Feb. 10, 2003 Preliminary 0.1 1. Correct the ZQ to programmable. Mar. 8, 2003 Preliminary The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Mar. 2003 Rev 0.1 Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM K7Z167288B K7Z163688B 512Kx36 & 256Kx72-Bit DLW(Dobule Late Write) RAM FEATURES GENERAL DESCRIPTION • Double Late Write mode , Pipelined Read mode. • Compatible with Double Late Write Sigma RAMT M x36/x72. • 1.8V+150/-100 mV Power Supply. • I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O • HSTL I/O • Byte Writable Function. • Single READ/WRITE control pin. • Self-Timed Write Cycle. • Complement echo clock outputs • Programmable impedance output buffer(ZQ) • 2 User programmable chip enable inputs for easy depth expansion.(EP2, EP3) • Supports linear burst mode only. • Slow Down Function.(SD) • IEEE 1149.1 JTAG Compatible Boundary Scan • 209 bump, 14mm x 22mm, 1mm bump pitch BGA package • 209BGA(11x19 Ball Grid Array Package). FAST ACCESS TIMES PARAMETER Symbol -35 Unit Cycle Time tCYC 2.85 ns Clock Access Time tCD 1.7 ns The K7Z163688B & K7Z167288B is 18,874,368-bits Synchronous Static SRAMs. The Double Late Write RAM utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except EP2, EP3, and SD are synchronized to input clock. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles,the SRAM output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock. The K7Z163688B & K7Z167288B are implemented with SAMSUNG ′s high performance CMOS technology and is available in 209BGA packages. Multiple power and ground pins minimize ground bounce. LOGIC BLOCK DIAGRAM A [0:18] A [0:17] ADDRESS REGISTER A 2~A 17 or A 2~A 18 CO NTRO L LOG IC CK BURST ADDRESS COUNTER A 0 ~ A1 WE BWx (x=a ~ h) (x=a ~ d) CONTROL ADV EP2 EP3 K REGISTER E1 E2 E3 WRITE ADDRESS REGISTER A ′0 ~A′1 512K x 36 & 256K x 72 MEMORY ARRAY WRITE ADDRESS REGISTER K DATA-IN REGISTER K DATA-IN REGISTER CONTROL LOGIC K OUTPUT REGISTER BUFFER K Echo Clock OUTPUT BUFFER 36 / 72 DQa0 ~ DQh7 or DQa0 ~ DQd7 DQPa ~ DQPh DQPa ~ DQPd 4 CQ1, CQ1 CQ2, CQ2 -2- Mar. 2003 Rev 0.1 Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM K7Z167288B K7Z163688B 209BGA PACKAGE PIN CONFIGURATIONS (TOP VIEW) 512Kx36 Common I/O-Top View 1 2 4 5 6 7 A NC NC B NC NC A E2 A ADV A BWc NC A WE A C NC NC D NC NC NC B Wd NC(128M) E1 NC V SS Vref NC MCL NC E NC DQPc F DQc DQc V DDQ V DDQ V DD V DD V DD V SS V SS V SS ZQ V SS G DQc H DQc DQc V DDQ V DDQ V DD EP2 DQc V SS V SS V SS EP3 3 8 9 10 11 E3 A DQb DQb BW b NC DQb DQb NC BWa DQb DQb Vref V SS DQb DQb V DDQ V DDQ NC DQPb V SS V SS NC NC V DD V DDQ V DDQ NC NC V SS V SS V SS NC NC J DQc DQc V DDQ V DDQ V DD MCH V DD V DDQ V DDQ NC NC K CQ2 CQ2 CK Vref V SS MCL V SS NC NC CQ1 CQ1 L NC NC V DDQ V DDQ V DD MCH V DD V DDQ V DDQ DQa DQa M NC NC V SS V SS V SS MCL V SS V SS V SS DQa DQa N NC NC V DDQ V DDQ V DD SD V DD V DDQ V DDQ DQa DQa P NC NC V SS V SS V SS MCL V SS V SS V SS DQa DQa R DQPd NC V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQPa NC T DQd DQd V SS Vref NC MCL NC Vref V SS NC NC U DQd DQd NC A NC(64M) A NC(32M) A NC NC NC V DQd DQd A A A A1 A A A NC NC W DQd DQd TMS TDI A A0 A TDO TCK NC NC -3- Mar. 2003 Rev 0.1 Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM K7Z167288B K7Z163688B 209BGA PACKAGE PIN CONFIGURATIONS (TOP VIEW) 256Kx72 Common I/O-Top View 1 2 5 6 7 A DQg DQg A B DQg DQg BWc E2 A ADV A B Wg NC WE A C DQg DQg BWh B Wd D DQg DQg V SS Vref NC(128M) E1 NC NC MCL NC E DQPg DQPc V DDQ F DQc DQc V SS V DDQ V DD V DD V SS V SS ZQ G DQc DQc H DQc DQc V DDQ V DDQ V DD V SS V SS V SS 3 4 8 9 10 11 E3 A DQb DQb BW b BWf DQb DQb BW e BWa DQb DQb Vref V SS DQb DQb V DD V DDQ V DDQ DQPf DQPb V SS V SS V SS DQf DQf EP2 V DD V DDQ V DDQ DQf DQf EP3 V SS V SS V SS DQf DQf J DQc DQc V DDQ V DDQ V DD MCH V DD V DDQ V DDQ DQf DQf K CQ2 CQ2 CK Vref V SS MCL V SS NC NC CQ1 CQ1 L DQh DQh V DDQ V DDQ V DD MCH V DD V DDQ V DDQ DQa DQa M DQh DQh V SS V SS V SS MCL V SS V SS V SS DQa DQa N DQh DQh V DDQ V DDQ V DD SD V DD V DDQ V DDQ DQa DQa P DQh DQh V SS V SS V SS MCL V SS V SS V SS DQa DQa R DQPd DQPh V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQPa DQPe T DQd DQd V SS Vref NC MCL NC Vref V SS DQe DQe U DQd DQd NC A NC(64M) A NC(32M) A NC DQe DQe V DQd DQd A A A A1 A A A DQe DQe W DQd DQd TMS TDI A A0 A TDO TCK DQe DQe -4- Mar. 2003 Rev 0.1 K7Z167288B K7Z163688B Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM Pin Description Table Pin Name Description Type Comments A Address Input - ADV Advance Input Active High BWx(x=a~h or a~d) Byte Write Enable Input Active Low CK Clock Input Active High DQ Data I/O Input/Output - CQ Echo Clock Outputs Output Active High CQ Echo Clock Outputs Output Active Low E1 Chip Enable Input Active Low E 2 & E3 Chip Enable Input Programmable Active High or Low EP2 & EP3 Chip Enable Program Pin Input - SD Slow Down Input Input Active Low TCK Test Clock Input Active High TDI Test Data In Input - TDO Test Data Out Output - TMS Test Mode Select Input - MCH Must Connect High Input Active High MCL Must Connect Low Input Active Low NC No Connect - Not connected to die WE Write Input Active Low V DD Core Power Supply Input 1.8V V DDQ Output Driver Power Supply Input 1.5V V SS Ground Input - ZQ Output Impedance Control Input Programmable ZQ Vref Input Reference Voltage Input - -5- Mar. 2003 Rev 0.1 K7Z167288B K7Z163688B Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM FUNCTION DESCRIPTION The K7Z163688B & K7Z167288B are Double Late Write RAM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. Because a Double Late Write RAM is a synchronous device, address, data Inputs, and read/write control inputs are captured on the rising edge of the input clock. EP2 , EP3 and SD are asynchronous control input. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, all three chip enables(E1, E2, E3) are active, the write enable input signals WE are driven high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. At the second clock edge the data is driven out of the SRAM. Write operation occurs when WE is driven low at the rising edge of the clock. BWx[h:a] can be used for byte write operation. The Double Late Write RAM uses a double-late write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, W E and address are registered, and the data associated with that address is required two cycle later. Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is provided by the external address. The burst address counter wraps around to its initial state upon completion. Double Late Write RAM supports linear burst sequence only. BURST SEQUENCE TABLE (Linear Burst Order ) A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 Slow Down Function S D is helpful to prevent to bus contention in read operation after write operation , especially high frequency application. When SD is Low, the SRAM is operated in a slow down mode. In a slow down mode, the enable/disable timings of output data become slower , which are defined as tKHQV,tKHQZ,tKHQX,tKHQX1/tKHCH and tKLCL. The valid data window in slow down mode is same with normal operation mode , so it will be helpful in read operation after write operation When SD is High , the SRAM returns to normal operation node. The state of SD must be fixed before operation , and it can not be changed during operation. -6- Mar. 2003 Rev 0.1 Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM K7Z167288B K7Z163688B Programmable Enables Double Late Write RAM features two user programmable chip enable inputs, E2 and E3. The sense of the inputs, whether they function as active low or active high inputs, is determined by the state of the programming inputs, EP2 and E P3. For example, if EP2 is held at VDD, E2 functions as an active high enable. If EP2 is held to VSS, E2 functions as an active low chip enable input. Programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By programming the enable inputs of four Double Late Write RAMs in binary sequence(00, 01, 10, 11)and driving the enable inputs with two address inputs. Four Double Late Write RAM can be made to look like one larger RAM to the system. Deselection of the RAM via E1 does not deactive the Echo Clocks. Programmable Impedance Output Driver The data output and echo clock driver impedance are adjusted by an external resistor, RQ, connected between ZQ pin and V SS , and are equal to RQ/5. For example, 250Ω resistor will give an output impedance of 50Ω. Output driver impedance tolerance is 15% by test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. They may also occur in cycles initiated with G high. In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM. Impedance updates occur no more often than every 32 clock cycles. Clock cycles are counted whether the SRAM is selected or not and proceed regardless of the type of cycle being executed. Therefore, the user can be assured that after 33 continuous read cycles have occurred, an impedance update will occur the next time G are high at a rising edge of the K clock. There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles. Example Four Bank Depth Expansion Schematic A0 - An E1 CK WE DQ 0 - DQ n A 0 - An-2 Bank 0 A Bank 1 A 0 - A n-2 A Bank 2 A 0 - A n-2 Bank 3 A A 0 - A n-2 A A n-1 E3 A n-1 E3 An-1 E3 An-1 E3 An E2 An E2 An E2 An E2 E1 E1 E1 E1 CK CK CK CK W W W W DQ DQ DQ DQ Bank Enable Truth Table EP2 EP3 E2 E3 Bank 0 V SS V SS Active Low Active Low Bank 1 V SS V DD Active Low Active High Bank 2 V DD V SS Active High Active Low Bank 3 V DD V DD Active High Active High -7- Mar. 2003 Rev 0.1 Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM K7Z167288B K7Z163688B STATE DIAGRAM FOR Double Late Write RAM X,F,L,X, or X,X,H,X Bank Deselect L,T,L,H L,T,L,L H,T,L,X X,F,L,X Deselect L,T,L,H L,T,L,L H,T,L,X, or X,X,H,X H,T,L,X H,T,L,X L,T,L,L Read X,F,L,X Write L,T,L,H L,T,L,H X,X,H,X X,X,H,X L,T,L,L L,T,L,H L,T,L,H H,T,L,X X,F,L,X Read Continue Write Continue X,X,H,X X,X,H,X X,F,L,X L,T,L,L H,T,L,X X,F,L,X Notes: 1. The notation "X,X,X,X" controlling the state transitions above indicate the states of inputs E 1,E,ADV, and WE respectively. 2. If (E2=EP2 and E3=EP3) then E="T" else E="F". 3. "H"=input "high"; "L"=input"low"; "X"=input"don’t care"; "T"=input "true"; "F"=input "false". -8- Mar. 2003 Rev 0.1 Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM K7Z167288B K7Z163688B TRUTH TABLES Previous Cycle Input Type E1 (tn) E (tn) ADV WE (tn) (tn) BW x (tn) Current Operation Address DQ/CQ (tn) DQ/CQ (tn+1) Notes N/A D H T L X X Deselect Cycle None * Hi-Z/CQ 4 Deselect C X X H X X Deselect Cycle, Continue Next Hi-Z/CQ Hi-Z/CQ 4 N/A D X F L X X Bank Deselect Cycle None * Hi-Z 4, 5 Bank Deselect C X X H X X Bank Deselect Cycle, Continue Next Hi-Z Hi-Z 4,5 N/A R L T L H X Read Cycle, Begin Burst External * Q/CQ 2 Read C X X H X X Read Cycle, Continue Burst Next Q /CQ Q/CQ N/A W L T L L X Write Cycle, Begin Burst External * D/CQ 2, 3 N/A W L T L L F Non-Write Cycle, Begin Burst External * * 2, 3 Write C X X H X T Write Cycle, Continue Burst Next D/CQ D/CQ 3 Write C X X H X F Non-Write Cycle, Continue Burst Next * D/CQ 3, 4, 5 Note: 1. X=Don’t Care, H=High, L=Low. 2. E=T(True) if E2=active and E3=active; E=F(False) if E2=inactive or E3=inactive . 3. " * " indicates that the DQ input requirement / output state and CQ output state are determined by the previous operation. 4. BWx= F(False) if all Byte Write Enable pins are high. B Wx=T(True) if any one Byte Write Enable pin is low. 5. DQs are tri-state in response to Bank Deselect, Deselect, and Write commands . 6. Deassertion of E1 does not deactive the echo clock outputs( CQ1, CQ1 , CQ2, CQ2 ). Echo clock outputs are tri-stated in response to Bank Deselect Commands only. WRITE TRUTH TABLE(x36) WE BW a BW b BWc BWd OPERATION H X X X X READ L L H H H WRITE BYTE a L H L H H WRITE BYTE b L H H L H WRITE BYTE c L H H H L WRITE BYTE d L L L L L WRITE ALL BYTEs L H H H H WRITE ABORT/NOP Notes : 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑). WRITE TRUTH TABLE(x72) WE BW a BW b BWc BWd BWe BW f BW g BWh H X X X L L H H X X H H L H L L H H H H L H L H H L H H H H L H L H H H H H H H L H H H H OPERATION X X X READ H H H WRITE BYTE a H H H H WRITE BYTE b H H H H WRITE BYTE c L H H H H WRITE BYTE d H L H H H WRITE BYTE e H L H H WRITE BYTE f H H L H WRITE BYTE g H H H L WRITE BYTE h L L L L L L L L L WRITE ALL BYTEs L H H H H H H H H WRITE ABORT/NOP Notes : 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑). -9- Mar. 2003 Rev 0.1 K7Z167288B K7Z163688B Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM ABSOLUTE MAXIMUM RATINGS* SYMBOL RATING UNIT Voltage on V DD Supply Relative to V SS PARAMETER V DD -0.5 to 2.9 V Voltage on V DDQ Supply Relative to V SS V DDQ -0.5 to VDD V Voltage on Any Other Pin Relative to VSS VI N -0.5 to VDD+ 0.3 V Power Dissipation PD 1.6 W Storage Temperature TSTG -65 to 150 °C Operating Temperature T OPR 0 to 70 °C Storage Temperature Range Under Bias TBIAS -10 to 85 °C *Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING CONDITIONS (0°C ≤ TA ≤ 70°C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. MAX UNIT V DD 1.7 1.8 1.95 V V DDQ 1.4 1.5 1.6 V V SS 0 0 0 V *Note : V DD and VDDQ must be supplied with identical v ol tage levels. DC ELECTRICAL CHARACTERISTICS (VDD =1.8V + 150/-100mV, TA=0°C to +70°C) PARAMETER SYM. TEST CONDITIONS MIN MAX UNIT NOTE Input Leakage Current IIL V DD=Max ; V IN=VSS to V DD -2 +2 µA Output Leakage Current IOL Output Disabled, -2 +2 µA Operating Current ICC x72 - TBD x36 - TBD - TBD mA - TBD mA - TBD mA ISB1 Standby Current ISB2 ISB3 V DD=Max , I OUT =0mA Cycle Time ≥ tCYC Min -35 E2 or E3 False, IOUT=0mA , f=Max All Inputs ≤V IL or ≥V IH E1 ≥V IH, IOUT=0mA, f=Max, All Inputs ≤V IL or ≥V IH Device deselected, I OUT=0mA, f=0, All Inputs=fixed (VDD-0.2V or 0.2V) mA 1,2 Input Low Voltage V IL -0.3 V ref * 0.1 V 3,5,6 Input High Voltage V IH V ref +0.1 V DD+0.3 V 3,5,7 Output High Voltage(Programmable Impedance) V OH1 V DDQ /2 V DDQ V 8 Output Low Voltage(Programmable Impedance) V OL1 V SS V DDQ/2 V 9 Output High Voltage(IOH=-0.1mA) V OH2 V DDQ-0.2 V DDQ V 10 Output Low Voltage(IOL =0.1mA) V OL2 V SS 0.2 V 10 Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing. 2. Data states are all zero. 3. In Case of I/O Pins, the Max. V I H=VDDQ+0.3V 4. The EP2, EP3 pins must not be changed during operation. 5. These are DC test criteria. DC design criteria is V R E F±50mV. The AC V IH /VIL levels are defined separately for measuring timing parameters. 6. V IL (Min)DC= - 0.3V, VIL (Min)AC=-1.5V(pulse width ≤ 3ns). 7. VIH (Max)DC=V DDQ+0.3, V IH (Max)AC=V DDQ+0.85V(pulse width ≤ 3ns). 8. |I OH |=(VDDQ /2)/(RQ/5)±15% @VOH =VDDQ /2 for 175Ω ≤ RQ ≤ 350 Ω. 9. |I OL |=(VDDQ /2)/(RQ/5)±15% @VOL =V DDQ /2 for 175Ω ≤ RQ ≤ 350Ω. 10. Minimum Impedance Mode when ZQ pin is connected to VSS . - 10 - Mar. 2003 Rev 0.1 Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM K7Z167288B K7Z163688B CAPACITANCE*(TA =25°C, f=1MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL TEST CONDITION MIN MAX UNIT C IN V I N=0V - TBD pF COUT V OUT=0V - TBD pF *Note : Sampled not 100% tested. Overershoot Timing Undershoot Timing 20% tKHKH (MIN) V IH V DDQ +0.5V V DDQ +0.25V V SS V DDQ V SS-0.25V V SS -0.5V 20% t KHKH(MIN) V IL Note: For power-up, VIH ≤ VDDQ +0.3V and VD D ≤ 1.7V and VDDQ ≤ 1.4V t ≤ 200ms AC TEST CONDITIONS Parameter Symbol Value Unit V DD 1.7~1.9 V Core Power Supply Voltage Output Power Supply Voltage V DDQ 1.4~1.6 V Input High/Low Level V IH/VIL 1.25/0.25 V Input Reference Level V REF 0.75 V Input Rise/Fall Time TR/T F 0.3/0.3 ns V DDQ/2 V Output Timing Reference Level Note: Parameters are tested with RQ=250 Ω AC TEST OUTPUT LOAD 50 Ω 50 Ω 0.75V 5pF 25 Ω DQ 0.75V 50 Ω 50 Ω 0.75V 5pF - 11 - Mar. 2003 Rev 0.1 K7Z167288B K7Z163688B Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM AC TIMING CHARACTERISTICS (VDD =1.8V + 150/-100mV, TA =0 to 70°C) -35 SD=VDD PARAMETER SYMBOL -35 S D=VSS UNIT MIN MAX MIN MAX 2.85 - 2.85 - ns Cycle Time tKHKH Clock High to Output Valid tKHQV - 1.7 - 2.6 ns Clock High to Output High-Z tKHQZ 0.5 1.7 1.4 2.6 ns Output Hold from Clock High tKHQX 0.5 - 1.4 - ns Clock High to Output Low-Z tKHQX1 0.5 - 1.4 - ns Clock High to CQ High tKHCH 0.5 1.7 1.4 2.6 ns Clock Low to CQ Low tKLCL 0.5 1.7 1.4 2.6 ns Output Hold from CQ High tCHQX -0.4 - -0.4 - ns CQ High to Output Low-Z tCHQX1 -0.4 - -0.4 - ns CQ High to Output Valid tCHQV - 0.4 - 0.4 ns Clock High to CQ Low-Z tKHCX1 0.5 - 1.4 - ns Clock High to CQ High-Z tKHCZ 0.5 1.5 1.4 2.4 ns Clock High Pulse Width tKHKL 1.2 - 1.2 - ns Clock Low Pulse Width tKLKH 1.2 - 1.2 - ns Address Setup to Clock High tAVKH 0.6 - 0.6 - ns Chip Enable Setup to Clock High tEVKH 0.6 - 0.6 - ns Write Setup to Clock High(WE, BW X) tWVKH 0.6 - 0.6 - ns Data Setup to Clock High tDVKH 0.6 - 0.6 - ns Address Advance Setup to Clock High tadvVKH 0.6 - 0.6 - ns Address Hold from Clock High tKHAX 0.4 - 0.4 - ns Chip Enable Hold from Clock High tKHEX 0.4 - 0.4 - ns Write Hold from Clock High(WE, BW X ) tKHWX 0.4 - 0.4 - ns Data Hold from Clock High tKHDX 0.4 - 0.4 - ns Address Advance Hold from Clock High tKHadvX 0.4 Notes : 0.4 ns 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and E 1 i s sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this devi ce is chip selected. 2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled. 3. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low, Both cases must meet setup and hold times. 4. To avoid bus contention, At a given voltage and temperature t KHQX1 is more than tKHQZ. The specs as shown do not imply bus contention because tKHQX1 is a Min. parameter that is worst case at totally different test conditions ( 0°C,1.95V) than tK H Q Z, which is a Max. parameter(worst case at 70 °C,1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature. - 12 - Mar. 2003 Rev 0.1 Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM K7Z167288B K7Z163688B IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left unconnected. JTAG Block Diagram JTAG Instruction Coding IR2 IR1 SRAM CORE TDI BYPASS Reg. TDO Identification Reg. Instruction Reg. Control Signals TMS TCK TAP Controller IR0 Instruction TDO Output Notes 0 0 0 EXTEST Boundary Scan Register 1 0 0 1 IDCODE Identification Register 3 0 1 0 SAMPLE-Z Boundary Scan Register 2 0 1 1 BYPASS Bypass Register 4 1 0 0 SAMPLE Boundary Scan Register 5 1 0 1 RESERVED Do Not Use 6 1 1 0 BYPASS Bypass Register 4 1 1 1 BYPASS Bypass Register 4 NOTE : 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. This instruction is not IEEE 1149.1 compliant. 2. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 3. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 4. Bypass register is initiated to V SS when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 5. SAMPLE instruction dose not places DQs in Hi-Z. 6. This instruction is reserved for future use. TAP Controller State Diagram 1 Test Logic Reset 0 0 Run Test Idle 1 1 Select DR 0 Exit2 DR 1 1 Update DR 0 - 13 - 1 Capture IR 0 0 Shift IR 1 1 Exit1 DR 0 Pause DR 1 Select IR 0 1 Capture DR 0 Shift DR 1 1 1 0 0 0 Exit1 IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 0 Mar. 2003 Rev 0.1 Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM K7Z167288B K7Z163688B SCAN REGISTER DEFINITION Part Instruction Register Bypass Register ID Register Boundary Scan 512Kx36 3 bits 1 bits 32 bits 121 bits 256Kx72 3 bits 1 bits 32 bits 121 bits ID REGISTER DEFINITION Part Revision Number (31:28) Part Configuration (27:18) Vendor Definition (17:12) Samsung JEDEC Code (11: 1) Start Bit(0) 512Kx36 0000 00111 00100 XXXXXX 00001001110 1 256Kx72 0000 00110 00101 XXXXXX 00001001110 1 BOUNDARY SCAN EXIT ORDER Order Pin ID Order Pin ID Order Pin ID Order Pin ID 1 6W 36 11H 71 4A 106 2R 2 6V 37 10H 72 3C 107 1R 3 6U 38 10G 73 3B 108 1T 4 7V 39 11G 74 3A 109 2T 5 7U 40 11F 75 2A 110 2U 6 7W 41 10F 76 1A 111 1U 7 8U 42 10E 77 1B 112 1V 8 8V 43 11E 78 2B 113 2V 9 9V 44 11D 79 2C 114 2W 10 10W 45 10D 80 1C 115 1W 11 11W 46 10C 81 1D 116 3V 12 11V 47 11C 82 2D 117 4V 13 10V 48 11B 83 1E 118 4U 14 10U 49 10B 84 2E 119 5U 15 11U 50 10A 85 2F 120 5V 16 11T 51 11A 86 1F 121 5W 17 10T 52 9C 87 1G 18 11R 53 9B 88 2G 19 10R 54 9A 89 2H 20 10P 55 8C 90 1H 21 11P 56 8B 91 1J 22 11N 57 8A 92 2J 23 10N 58 7B 93 1K 24 10M 59 7A 94 6N 25 11M 60 6H 95 3K 26 11L 61 6G 96 4K 27 10L 62 6D 97 2K 28 11K 63 6C 98 2L 29 6M 64 6B 99 1L 30 6L 65 6A 100 1M 31 6J 66 5C 101 2M 32 6F 67 5A 102 2N 33 10K 68 4C 103 1N 34 10J 69 4B 104 1P 35 11J 70 5B 105 2P NOTE, NC,MCL and MCH ; Don′t Care - 14 - Mar. 2003 Rev 0.1 K7Z167288B K7Z163688B Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM JTAG DC OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Power Supply Voltage V DD 1.7 Input High Level V IH 1.3 1.8 1.95 V - V DD+0.3 V Input Low Level V IL -0.3 Output High Voltage(IOH=-2mA) V OH 1.5 - 0.5 V - V DD V Output Low Voltage(I OL=2mA) V OL V SS - 0.45 V Note 1 *Note : 1. In Case of I/O Pins, the Max. VIH =VDDQ +0.3V JTAG AC TEST CONDITIONS Parameter Symbol Min Unit Input High/Low Level V IH/VIL 1.3/0.5 V Input Rise/Fall Time TR/TF 1.0/1.0 ns 0.9 V Input and Output Timing Reference Level Note JTAG AC Characteristics Parameter Symbol Min Max Unit TCK Cycle Time tCHCH 20 - ns TCK High Pulse Width tCHCL 10 - ns TCK Low Pulse Width tCLCH 10 - ns TMS Input Setup Time tMVCH 5 - ns TMS Input Hold Time tCHMX 5 - ns TDI Input Setup Time tDVCH 5 - ns TDI Input Hold Time tCHDX 5 - ns SRAM Input Setup Time tSVCH 5 - ns SRAM Input Hold Time tCHSX 5 - ns Clock Low to Output Valid tCLQV 0 10 ns Note JTAG TIMING DIAGRAM TCK t CHCH t CHCL t MVCH t CHMX tD V C H t CHDX t SVCH t CHSX t CLCH TMS TDI PI (SRAM) t CLQV TDO - 15 - Mar. 2003 Rev 0.1 - 16 - CQ CQ Data Out Data In ADV E1 WE Address Clock tADVVKH tEVKH tWVKH tAVKH A1 tKHQX tKHQX1 CHQX1 Q1-1 tKHQZ A2 Read tKHQV Deselect tCHQV tKHADVX tKHEX tKHWX tKHAX Read t KH KH Q2-1 Q 2-2 t KH K L tK LK H tKLCL Q2-3 A3 Write tKHCH Q2-4 tDVKH A4 Wr ite D3-1 D4-1 tKHDX TIMING WAVEFORM OF READ/WRITE CYCLE with Continue operation D4-2 D4-3 Un defined Do n′t Care D4-4 K7Z167288B K7Z163688B Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM Mar. 2003 Rev 0.1 - 17 - CQ CQ Data In Data Out ADV E1 WE Address Clock A1 Read A2 Write Q1-1 A3 tDVKH Read D2-1 tKHDX Deselect Q 3-1 A4 Read A5 Write Q4-1 A6 Read D5-1 A7 TIMING WAVEFORM OF SINGLE READ/WRITE Read Q6-1 A8 Write Q7-1 A9 W rite Undefined Don′t Ca re D8-1 A10 K7Z167288B K7Z163688B Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM Mar. 2003 Rev 0.1 - 18 - Dout Bank2 CQ Bank2 CQ1+CQ2 CQ Bank1 Dout Bank1 E2 Bank1 E2 Bank2 ADV WE E1 Address Clock Hi A2 Read tKHCX1 Q1-1 A3 Read Q2-1 A5 Read Q 3-1 A4 NOTE: E1 does not desele ct the Echo Clock Outputs. E ch o Clock Ou tpu ts a re de se lected by E2 o r E 3 b eing sa mp led false. A1 Read Read Q4-1 A5 Read Q5-1 A6 Read ECHO CLOCK CONTROL IN TWO BANKS Q6-1 A7 Read Q 7-1 A8 tCYC Read Q 8-1 A9 Read Undefined Don′t Ca re Q9-1 A10 K7Z167288B K7Z163688B Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM Mar. 2003 Rev 0.1 - 19 - Dout Bank2 CQ Bank2 CQ1+CQ2 CQ Bank1 Dout Bank1 E2 Bank1 E2 Bank2 ADV WE E1 Address Clock A1 Read Hi-Z A2 tKLCX1 Q1-1 Deselect Read A3 Hi-Z Read Q 2-1 A4 Read Q 3-1 A5 Read Q 4-1 A6 Read BANK SWITCH WITH E1 DESELECT Q 5-1 A7 Read Q6-1 A8 Read Q7-1 A9 Read Undefined Don′t Ca re Q8-1 A10 K7Z167288B K7Z163688B Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM Mar. 2003 Rev 0.1 Preliminary 512Kx36 & 256Kx72 DLW(Double Late Write) RAM K7Z167288B K7Z163688B 209 Bump BGA PACKAGE DIMENSIONS 14mm x 22mm Body, 1.0mm Bump Pitch, 11x19 Bump Array 1.00x10=10.00(BSC) 14.00 1.00(BSC) 20 .50± 0.0 5 22.00 C1.00 1.00x18=1 8.0 0(BSC) 1.0 0(BSC) Indicator of Ball(1A) Location C0.70 2.20 MAX 1.50 12.50 0.90 0.50±0 .05 209-∅0.06±0.10 NOTE : 1. All Dimensions are in Millimeters. 2. Solder Ball to PCB Offset: 0.10 MAX. 3. PCB to Cavity Offset: 0.10 MAX. - 20 - Mar. 2003 Rev 0.1