SAMSUNG S3F49FAX

S3F49FAX
for Compact Flash
SPECIFICATION
Revision 1.0
HELP DESK
Sejin, Ahn ([email protected])
Sanghun, Song ([email protected])
SPECIFICATION
S3F49FAX
Table of Contents
1.1
1.2
1.3
2.1
2.2
Introduction ..............................................................................................................................2
Features...................................................................................................................................3
Block Diagram .........................................................................................................................4
Controller Package Drawing....................................................................................................5
Controller Pin Assignments and Pin Type ...............................................................................6
Table of Figures
1
2
3
S3F49FAX Block Diagram.......................................................................................................4
S3F49FAX Pin Assignment .....................................................................................................5
100-TQFP-1414 Package Dimension......................................................................................26
Table of Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
100-Pin TSOP Pin Assignment ...............................................................................................6
I/O Type Description ................................................................................................................10
Signal Description for PCMCIA/IDE Interface .........................................................................11
Signal Description for Flash Memory Interface .......................................................................17
Signal Description for Miscellaneous Part ...............................................................................20
Signal Description for Power Signal ........................................................................................21
Signal Description for USB Device ..........................................................................................21
Signal Description for Internal NOR Flash Memory ................................................................21
Absolute Maximum Ratings.....................................................................................................22
Recommended Operating Conditions .....................................................................................22
Thermal Characteristics...........................................................................................................22
D.C. Electrical Characteristics (In case of 3.3V Interface I/O) ................................................23
D.C. Electrical Characteristics (In case of 5.0V Interface I/O) ................................................24
System Clock Timing ...............................................................................................................25
POR(power on reset) Detection Level.....................................................................................25
1
SPECIFICATION
S3F49FAX
1.1 INTRODUCTION
Samsung's S3F49FAX is NAND flash memory controller which can control flash memories as solid state disk. It
provides PC Card ATA/IDE/USB interface, host and flash transfer rates up to 20.0MB/S. S3F49FAX can control
flash memory maximum 8 pieces. The device is designed using 0.35um CMOS process, assembled as 100-TQFP
package. It supports operation in both 5.0V and 3.3V.
An outstanding feature of the S3F49FAX flash disk controller is its CPU core: the ARM7TDMI 16/32-bit RISC
processor, designed by Advanced RISC Machine (ARM), Ltd. The ARM core is a low-power, general purpose,
microprocessor macro-cell that was developed for use in application-specific and customer-specific integrated
circuit. It is simple, elegant, and fully static design is particularly suitable for cost and power sensitive application.
•
PC Card-ATA/True IDE/CompactFlash/USB compatible host interface
•
Automatic sensing of PC Card ATA and IDE
•
Full Speed USB Function Controller compatible with the USB Specification Version 1.1
•
Included 256-byte CIS RAM
•
Five PC Card ATA addressing modes
•
Host data transfer rate: 20MB/s
•
Flash data transfer rate: 20MB/s
(It depends on the characteristics of flash memory)
•
Host Interface: 8/16-bit Access
•
Flash Interface: 8-bit Access
•
Support 3 power save mode: SLEEP/ACTIVE mode
(Auto power down function)
•
Support 128/256/512Mbit, 1Gbit, 2Gbit, 4Gbit NAND flash memory made by Samsung
NAND Flash Density
Min. / Max. Capacity (number of flash)
128M/256M/512M/1G bit (512Byte/page)
16MB / 1 G Byte (Up to 8EA)
1G / 2G / 4G bit (2048Byte/page)
256MB / 4 G Byte (Up to 8EA)
•
ECC function (Error correction algorithm): 2bit correction
•
Available 100-pin TQFP
•
Interface Voltage Range : 3.0 to 5.5V
•
Interface Support
Controller Part Number
Host interface
S3F49FAXZZ
CompactFlash
S3F49FAXZA
USB 1.1
2
SPECIFICATION
S3F49FAX
1.2 FEATURES
Microprocessor Architecture
USB Device
•
16/32bit RISC architecture
•
•
Efficient and powerful ARM7TDMI CPU core
•
Full Speed USB Function Controller
compatible with the USB Specification
Version 1.1
Cost-effective JTAG based debug solution
•
DMA Interface for Bulk Transfer
Internal Memory
•
5 Endpoint with FIFO
•
Included 48KB internal NOR FLASH
•
•
Included 16KB internal SRAM
Integrated USB Transceiver
(ASIC Full speed USB Pad)
DMA Controller
•
Two-channel,general-purpose DMA controller
•
Data transfer between SRAM and Flash,
SRAM and USB without CPU Intervention
•
Support for 8/16/32bit data transfers
•
Increment or decrement of source
or destination address
Programmable Timer
•
channel 16bit programmable timer
ECC Engine
•
Correct 2-bit Error
64bit Counter
•
64bit timer by cascading the 32-bit timers.
Interface Voltage Range
•
3.0 to 5.5 volts
Package Type
•
100-TQFP
Interrupts
•
8 interrupt sources
•
Normal or fast interrupt modes (IRQ, FIQ)
PC-Card/ATA Interface
•
Include 256Bytes SRAM for CIS
•
Support memory and I/O addressing mode
•
Support True IDE mode
3
SPECIFICATION
S3F49FAX
1.3 BLOCK DIAGRAM
NAND
FLASH
LocalBUS
USB
Host
ARM7TDMI
NOR FLASH
(48KB)
BUS CNTL
USB Device
ARBITER
FLASH
Controller
CF
Host
16bit
TIMER
Reset CNTL
PCMCIA
IDE
Power MAN
SFR for
ECC/FTL
ECC
Engine
DMA0
DMA1
64bit
Counter
SRAM
(16KB)
POR
PLL
VCO
Figure 1. S3F49FAX Block Diagram
4
PIN INFORMATION
2
S3F49FAX
SPECIFICATION
2.1 CONTROLLER PACKAGE DRAWING
XRESET
XA3
-XWAIT
84
83
82
81
76
XA4
85
-XREG
XA5
86
77
-XCSEL/XDS
87
PVDD1
XA6
88
78
XRDY
89
XA1
XA7
90
79
-XWE
91
80
XA8
92
XA2
-XIOWR
93
-XINPACK
XA9
15
94
TDI
PVDD2
14
95
-TRST
-XIORD
13
96
VDD1
-XOE
12
97
DN
XA10
11
98
DP
-XCE2
10
99
GND
100
-FRE
9
XD15
-FWE
25
51
GPIO[8] / RSOUT
-FWP
24
52
GPIO[9] / CKOUT
VDD5
53
23
FD0
54
HWP
FD1
55
22
FD2
56
XOUT
FD3
57
21
FD4
58
XIN
FD5
59
20
FD6
60
TDO
FD7
61
19
GND
62
VDD2
VDD6
63
18
XD10
64
GND
65
17
XWP/XIOIS16
TCK
66
16
XD9
TMS
67
XD3
S3F49FAX
100TQFP
XD2
8
-XCE1
7
68
XD11
XD8
XD4
XD1
6
BVD1/XSTSCHG
XD12
70
5
69
XD0
XD5
71
4
72
XD13
XA0
BVD2/XDASP
3
73
XD6
GND
2
74
1
75
XD7
XD14
40
41
42
43
FCE6 / GPIO[4]
FCE5 / GPIO[3]
FCE4 / GPIO[2]
FCE3 / GPIO[1]
FCE2 / GPIO[0]
FCE1
FALE
39
FCE7 / GPIO[5]
FCLE
38
FCE8 / GPIO[6]
50
37
FCE9 / GPIO[7]
VDD4
36
VDD3
49
35
TEST2
GND
34
TEST1
48
33
TEST0
FRDY1 / SDATA
32
VCON
47
31
MODE_SET
46
30
VSSA
FCE0
29
PLLCAP
FRDY0 / SCLK
28
VDDA
45
27
44
26
Figure 2. S3F49FAX Pin Assignment
5
SPECIFICATION
S3F49FAX
2.2 CONTROLLER PIN ASSIGNMENTS AND PIN TYPE
Table 1. 100-Pin TSOP Pin Assignment
Pin No.
Pin Name
I/O State
I/O Type
Function
1
XD7
I/O
pvbct83
Data bus of PCMCIA
2
XD14
I/O
pvbct83
Data bus of PCMCIA
3
XD6
I/O
pvbct83
Data bus of PCMCIA
4
XD13
I/O
pvbct83
Data bus of PCMCIA
5
XD5
I/O
pvbct83
Data bus of PCMCIA
6
XD12
I/O
pvbct83
Data bus of PCMCIA
7
XD4
I/O
pvbct83
Data bus of PCMCIA
8
XD11
I/O
pvbct83
Data bus of PCMCIA
9
XD3
I/O
pvbct83
Data bus of PCMCIA
10
GND
P
11
DP
I/O
pbusb1
Positive data for USB
12
DN
I/O
pbusb1
Negative data for USB
13
VDD1
P
14
-TRST
I
pis
Test reset for JTAG
15
TDI
I
pis
Test data input for JTAG
16
TMS
I
pis
Test mode select for JTAG
17
TCK
I
pis
Test clock for JTAG
18
GND
P
Ground
19
VDD2
P
Power
20
TDO
O
21
Ground
Power
pob4
Test data output for JTAG
XIN
psoscm26
Crystal Input
22
XOUT
psoscm26
Crystal Output
23
HWP
I
pic
Disable write command
24
CKOUT /
GPIO[9]
I/O
pbct4
Output of Clock signal /
General I/O pin
25
RSOUT /
GPIO[8]
I/O
pbct4
Output of Rest signal /
General I/O pin
6
SPECIFICATION
S3F49FAX
Table 1. 100-Pin TSOP Pin Assignment (Continued)
Pin No.
Pin Name
I/O State
I/O Type
Function
26
VDDA
P
27
PLLCAP
28
VSSA
P
29
MODE_DET
I
pic
Select Interface Mode
30
VCON
I
pica
Reference Voltage for VCO
31
TEST0
I
pic
Select test mode
32
TEST1
I
pic
Select test mode
33
TEST2
I
pifsn
Select test mode
34
VDD3
P
35
FCE9 /
GPIO[7]
I/O
pbct4sm
Enable 9 chip of nand flash /
General I/O PIN
36
FCE8 /
GPIO[6]
I/O
pbct4sm
Enable 8 chip of nand flash /
General I/O PIN
37
FCE7/
GPIO[5]
I/O
pbct4sm
Enable 7 chip of nand flash /
General I/O PIN
38
FCE6/
GPIO[4]
I/O
pbct4sm
Enable 6 chip of nand flash /
General I/O PIN
39
FCE5/
GPIO[3]
I/O
pbct4sm
Enable 5 chip of nand flash /
General I/O PIN
40
FCE4/
GPIO[2]
I/O
pbct4sm
Enable 4 chip of nand flash /
General I/O PIN
41
FCE3/
GPIO[1]
I/O
pbct4sm
Enable 3 chip of nand flash /
General I/O PIN
42
FCE2 /
GPIO[0]
I/O
pbct4sm
Enable 2 chip of nand flash /
General I/O PIN
43
FCE1
O
pob4sm
Enable 1 chip of nand flash
44
FCE0
O
pob4sm
Enable 0 chip of nand flash
45
FRDY0 /
SCLK
I
Picu
Ready/Busy signal of nand flash /
Serial data for internal flash
46
FRDY1 /
SDATA
I/O
Pbcut4
Ready/Busy signal of nand flash /
Serial clock for internal flash
47
GND
P
Analog Power for PLL
apad_80
Capacitor for PLL
Analog Ground for PLL
Power
Ground
7
SPECIFICATION
S3F49FAX
Table 1. 100-Pin TSOP Pin Assignment (Continued)
Pin No.
Pin Name
I/O State
I/O Type
Function
48
VDD4
P
49
FCLE
O
pob4sm
Command latch enable in nand flash
50
FALE
O
pob4sm
Address latch enable in nand flash
51
-FRE
O
pob8
Read enable in nand flash
52
-FWE
O
pob4
Write enalbe in nand flash
53
-FWP
O
pob4sm
Write protect in nand flash
54
VDD5
P
55
FD0
I/O
pbcdt4
I/O of nand flash memory
56
FD1
I/O
pbcdt4
I/O of nand flash memory
57
FD2
I/O
pbcdt4
I/O of nand flash memory
58
FD3
I/O
pbcdt4
I/O of nand flash memory
59
FD4
I/O
pbcdt4
I/O of nand flash memory
60
FD5
I/O
pbcdt4
I/O of nand flash memory
61
FD6
I/O
pbcdt4
I/O of nand flash memory
62
FD7
I/O
pbcdt4
I/O of nand flash memory
63
GND
P
Ground
64
VDD6
P
Power
65
XD10
I/O
pvbct83
Data bus of PCMCIA
66
XWP / IOIS16
O
pvot83
IOIS16 of PCMCIA (XIOSI16)
67
XD9
I/O
pvbct83
Data bus of PCMCIA
68
XD2
I/O
pvbct83
Data bus of PCMCIA
69
XD8
I/O
pvbct83
Data bus of PCMCIA
70
XD1
I/O
pvbct83
Data bus of PCMCIA
71
BVD1 / XSTSCHG
I/O
pvbcut43
STSCHG of PCMCIA (XIOIS16)
72
XD0
I/O
pvbct83
Data bus of PCMCIA
73
BVD2 / XDASP
I/O
pvbcut43
DASP for IDE (XDASP)
74
XA0
I
pvic3
Address bus of PCMCIA
75
GND
P
Power
Power
Ground
8
SPECIFICATION
S3F49FAX
Table 1. 100-Pin TSOP Pin Assignment (Continued)
Pin No.
Pin Name
I/O State
I/O Type
76
-XREG
I
77
PVDD1
P
78
XA1
I
pvic3
Address bus of PCMCIA
79
-XINPACK
O
pvob43
INPACK of PCMCIA
80
XA2
I
pvic3
Address bus of PCMCIA
81
-XWAIT
O
pvob43
Wait signal of PCMCIA
82
XA3
I
pvic3
Address bus of PCMCIA
83
XRESET
I
pvit3
Host reset signal in PCMCIA
84
XA4
I
pvic3
Address bus of PCMCIA
85
XA5
I
pvic3
Address bus of PCMCIA
86
-XCSEL/XDS
I
pvitu3
Master/Slave selection signal (XDS)
87
XA6
I
pvic3
Address bus of PCMCIA
88
XRDY
O
pvot43
Ready/Busy signal of PCMCIA
89
XA7
I
pvic3
Address bus of PCMCIA
90
-XWE
I
pvisu3
Wrtie enable in PCMCIA
91
XA8
I
pvic3
Address bus of PCMCIA
92
-XIOWR
I
pvisu3
IO write signal in PCMCIA
93
XA9
I
pvic3
Address bus of PCMCIA
94
PVDD2
P
95
-XIORD
I
pvisu3
IO read signal in PCMCIA
96
-XOE
I
pvisu3
Output enable in PCMCIA
97
XA10
I
pvic3
Address bus of PCMCIA
98
-XCE2
I
pvisu3
Card enable 2 in PCMCIA
99
-XCE1
I
pvisu3
Card enable 1 in PCMCIA
100
XD15
I/O
pvbct83
Data bus of PCMCIA
pvisu3
Function
REG of PCMCIA
Power
Power
9
SPECIFICATION
S3F49FAX
Table 2. I/O Type Description
I/O Type
Description
pic
3.3V LVCMOS Level Input Buffers
picu
3.3V LVCMOS Level Input Buffer with pull-up register
picd
3.3V LVCMOS Level Input Buffer with pull-down register
pica
VCO output frequency control PAD
pvic3
5V/3.3V LVCMOS Level PCMCIA Input Buffer
pvisu3
5V/3.3V LVCMOS Schmitt Trigger Level PCMCIA Input Buffer with Pull-up Resistor
pvitu3
5V/3.3V TTL Level PCMCIA Input Buffer with Pull-up Resistor
pvit3
5V/3.3V TTL Level PCMCIA Input Buffer
pfisn_80
High voltage Input tolerant pad
pob4
4mA LVCMOS Normal Output Buffers
pob4sm
4mA LVCMOS Normal Output Buffers with Medium Slew-Rate
pob8
8mA LVCMOS Normal Output Buffers
pvot43
5V/3.3V 4mA Tri-State PCMCIA Output Buffer without SRC
pvot83
5V/3.3V 8mA Tri-State PCMCIA Output Buffer without SRC
Apad_80
Analog Output for PLL capacitor
Pbct4
3.3V LVCMOS Level Input Buffer and 4mA Tri-State Output Buffers
pbcut4
3.3V LVCMOS Level Input Buffer with Pull-up Resistor and 4mA LVCMOS
Tri-State Output Buffer
pbcdt4
3.3V LVCMOS Level Input Buffer with Pull-down Resistor and 4mA LVCMOS
Tri-State Output Buffer
pbct4sm
3.3V LVCMOS level input buffer and 4mA tri-state output buffer
with Medium Slew-Rate
pbusb1
3.3V USB differential input receiver, a differential output driver.
pvbct83
5V/3.3V LVCMOS Level PCMCIA Input Buffer and 8mA Tri-State
PCMCIA Output Buffer without SRC
pvbcut43
5V/3.3V LVCMOS Level PCMCIA Input Buffer with Pull-up Resistor and
4mA Tri-State PCMCIA Output Buffer without SRC
psoscm26
Oscillator cell with enable and register
pvob43
5V/3.3V 4mA PCMCIA Output Buffer witout SRC
10
SPECIFICATION
S3F49FAX
2.3 Signal descriptions
Table 3. Signal Description for PCMCIA/IDE Interface
Signal Name
100-Pin Number
XA0
74
XA1
78
XA2
80
XA3
82
XA4
84
XA5
85
XA6
87
XA7
89
XA8
91
XA9
93
XA10
97
XD0
72
XD1
70
XD2
68
XD3
9
XD4
7
XD5
5
XD6
3
XD7
1
XD8
69
XD9
67
XD10
65
XD11
8
XD12
6
XD13
4
XD14
2
XD15
100
I/O
Description
ADDRESS BUS[10:0]:
These address lines along with the –REG signal
are used to select the following:
I
The I/O port address registers within the PC
Storage Card, the memory mapped port address
registers within the PC Storage Card, a byte in
the Card's information structure and its
configuration control and status registers.
This signal is the same as the PC Card Memory
Mode signal in PC Card I/O mode.
In True IDE Mode only A[2:0] are used to select
the one of eight registers in the Task File, the
remaining address lines should be grounded by
the host.
DATA BUS[15:0]:
These lines carry the Data, Commands and
Status information between the host and the
controller. XDB0 is the LSB of the even byte of
the word. XDB8 is the LSB of the odd byte of the
word.
This signal is the same as the PC Card memory
mode signal in PC Card I/O mode.
I/O
In True IDE mode, all Task File operations occur
in byte mode on the low order bus XDB0-XDB7
while all data transfers are 16 bit using XDB0XDB15
11
SPECIFICATION
S3F49FAX
Table 3. Signal Description for PCMCIA/IDE Interface (Continued)
Signal Name
XREG
100-Pin Number
76
I/O
I
Description
ATTRIBUTE MEMORY AREA SELECTION:
This signal is used during memory cycles to distinguish
between common memory and register (Attribute) memory
accesses. High for Common memory, low for attribute
memory.
The signal must also be active (low) during I/O cycles when
the I/O address is on the Bus.
In True IDE mode, this input signal is not used and should be
connected to VCC by the host.
CARD ENABLE:
These input signals are used both to select the card and to
indicate to the card whether a byte or a word operation is
being performed.
XCE1
99
I
XCE2
98
-CE2 always accesses the odd byte of the word.
-CE1 accesses the even byte or the Odd byte of the
word depending on A0 and -CE2. A multi-plexing
scheme based on A0, -CE1, -CE2 allows 8 bit hosts
to access all data on XDB0-XDB7.
This signal is the same as the PC card memory mode signal
in PC Card I/O mode.In the True IDE mode, CS0 is the chip
select for the task file registers while CS1 is used to select
the alternate status register and the device control register.
XOE
96
I
OUTPUT ENABLE:
This is an output enable strobe generated by the host
interface. It is used to read data from the PC Card in memory
mode and to read the CIS and configuration registers.
In PC Card I/O mode, this signal is used to read the CIS and
configuration registers. To enable True IDE mode this input
should be grounded by the host.
12
SPECIFICATION
S3F49FAX
Table 3. Signal Description for PCMCIA/IDE Interface (Continued)
Signal Name
XWE
100-Pin Number
90
I/O
I
Description
WRITE ENABLE:
This is a signal driven by the host and used for strobing memory
write data to the registers of the PC Card when the card is
configured in the memory interface mode. It is also used for
writing the configuration registers.
In PC Card I/O mode, this signal is used for writing the
configuration registers. In True IDE mode, this input signal is not
used and should be connected to VCC by the host.
XWAIT
81
O
WAIT:
The -WAIT signal is driven low by the PC Card to signal the host
to delay completion of a memory or I/O cycle that is in progress.
IORDY:
In True IDE mode, this output signal may be used as IORDY.
I/O PORT IS 16 BITS:
Memory mode - The PC Card does not have a write protect
switch. This signal is held low after the completion of the reset
initialization sequence.
XWP/
XIOIS16
66
O
I/O operation - When the PC Card is configured for I/O operation
pin 24 is used for the -I/O selected is 16-Bit Port (-IOIS16)
function. A low signal indicates that a 16 bit or odd byte only
operation can be performed at the addressed port.
In True IDE mode, this output signal is asserted low when this
device is expecting a word data transfer cycle.
13
SPECIFICATION
S3F49FAX
Table 3. Signal Description for PCMCIA/IDE Interface (Continued)
Signal Name
XINPACK
100-Pin Number
79
I/O
Description
O
INPUT PORT ACKNOWLEDGE:
This signal is not used in memory mode. The Input
acknowledge signal is asserted by the PC Card when the card
is selected and responding to an I/O read cycle at the address
that is on the address bus.
This signal is used by the host to control the enable of any
input data buffers between the PC Card and the CPU.
In True IDE mode, this output signal is not used and should be
connected at the host.
READY/BUSY:
In memory mode, this signal is set high when the PC Card is
ready to accept a new data transfer operation and held low
when the card is busy. The host memory card socket must
provide a pull-up resistor. At power up and at reset, the RDY/BSY signal is held low (busy) until the PC Card has completed
its power up or reset function.
XRDY
88
O
No access of any type should be made to the PC Card during
this time. The RDY/-BSY signal is held high (disabled from
being busy) whenever the following condition is true:
The PC Card has been powered up with +RESET continuously
disconnected or asserted.
I/O operation - After the PC Card has been configured for I/O
operation, this signal is used as Interrupt request. This line is
strobed low to generate a pulse mode interrupt or held low for
a level mode interrupt.
In True IDE mode, this signal is the active high Interrupt
request to the host.
XIORD
95
I
I/O READ:
This signal is not used in memory mode.This is an I/O read
strobe generated by the host. This signal gates I/O data onto
the bus from the PC Card when the card is configured to use
the I/O interface.
In True IDE Mode, this signal has the same function as in PC
Card I/O Mode.
14
SPECIFICATION
S3F49FAX
Table 3. Signal Description for PCMCIA/IDE Interface (Continued)
Signal Name
XIOWR
100-Pin Number
92
I/O
I
Description
I/O WRITE:
This signal is not used in memory mode.The I/O write strobe
pulse is used to clock I/O data on the card data bus into the PC
Card controller registers when the PC Card is configured to use
the I/O interface.
The clocking will occur on the negative to positive edge of the
signal (trailing edge). In True IDE mode, this signal has the same
function as in PC Card I/O Mode
BVD1 /
XSTSCHG
71
I/O
STATUS CHANGED:
This signal is asserted high as the BVD1 signal since a battery is
not used with this product.This signal is asserted low to alert the
host to changes in the RDY/-BSY and write protect states, while
the I/O interface is configured. Its use is controlled by the Card
config and status.
In the True IDE mode, this input / output is the pass diagnostic
signal in the Master/Slave handshake protocol.
XCSEL /
XDS
86
I
CARD SELECT:
In True IDE mode, this signal is used for configure this device as
a master or slave. When it is grounded , the device is configured
as a master.
When this signal is open, the device is configured as a slave.
In I/O and memory mode, this signal is not used.
XRESET
83
I
RESET:
When the pin is high, this signal resets the PC Card. The PC Card
is reset only at Power up if this pin is left high or open from powerup. The PC Card is also reset when the soft reset bit in the Card
Configuration Option Register is set.
In the True IDE mode, this input pin is the active low hardware
reset from the host.
15
SPECIFICATION
S3F49FAX
Table 3. Signal Description for PCMCIA/IDE Interface (Continued)
Signal Name
100-Pin Number
I/O
Description
This output line is always driven to a high state in memory
mode since a battery is not required for this product.
BVD2/XDASP
73
I/O
This output line is always driven to a high state in I/O mode
since this product does not support the audio function.
In the True IDE mode, this input/output is the disk active/slave
present signal in the Master/Slave handshake protocol.
16
SPECIFICATION
S3F49FAX
Table 4. Signal Description for Flash Memory Interface
Signal Name
100-Pin Number
I/O
Description
FD0
55
FD1
56
FD2
57
FD3
58
FD4
59
FD5
60
FD6
61
FD7
62
FRDY0
45
I
FRDY1
46
I/O
FALE
50
O
FLASH ADDRESS LATCH ENABLE:
When this signal is asserted the controller can send an
address to the flash memory by asserting of FWE pin.
FCLE
49
O
FLASH COMMAND LATCH ENABLE:
When this signal is asserted, a command can be to the flash
memory.
FRE
51
O
FLASH READ ENABLE:
This signal is asserted to enable the reading of data from the
flash memory.
FWE
52
O
FLASH WRITE ENABLE:
When this signal is asserted , the controller can write data to
the flash memory.
FLASH DATA BUS[15:0]:
These lines are 16-bit data lines to/from the flash memory chip.
I/O
FLASH READY:
The signal is used for indicate to the controller, which flash
memory is ready to accept a command.
17
SPECIFICATION
S3F49FAX
Table 4. Signal Description for Flash Memory Interface (Continued)
Signal Name
100-Pin Number
I/O
FCE0
44
O
FCE1
43
O
FCE2
42
I/O
FCE3
41
I/O
FCE4
40
I/O
FCE5
39
I/O
FCE6
38
I/O
FCE7
37
I/O
FCE8
36
FCE9
35
FWP
53
Description
FLASH CHIP ENABLE:
These lines are flash memory enable signal.
I/O
I/O
O
PROTECTION OF WRITING FLASH MEMORY:
Write protect of flash chips
18
SPECIFICATION
S3F49FAX
Table 5. Signal Description for Miscellaneous Part
Signal Name
100-Pin Number
I/O
Description
TCK
17
I
TEST CLOCK:
The S3F49FAX contains internally in-circuit emulation block
for debugger mode which use standard JTAG protocol.
When the controller go into debugger mode, this signal is
provided from external debugger tool.
TMS
16
I
TEST MODE SELECT:
In the debugger mode, this signal select test mode. This pin
should be held to “1’, when do not use the JTAG block.
TDI
15
I
TEST DATA INPUT:
In the debugger mode, this signal is used for carry data.
from external debugger tool to the controller.
TRST
14
I
TEST RESET:
This signal should be sustained LOW first at the begging of
normal operation.
TDO
20
O
TEST DATA OUTPUT:
In the debugger mode, this signal is used for carry data.
from the controller to external debugger tool.
XI
21
–
INPUT CLOCK:
This signal is system clock.
XO
22
–
OUTPUT CLOCK:
This signal is system output clock.
TEST0
31
TEST1
32
I
SELECT TEST MODE:
Select the test mode of chip
TEST2
33
RSOUT
25
I/O
Output Internal Reset Signal
CKOUT
24
I/O
Output the PLL clock signal for checking PLL operation
HWP
23
I
Protect writing/erasing operation
19
SPECIFICATION
S3F49FAX
Table 5. Signal Description for Miscellaneous Part (Continued)
Signal Name
100-Pin Number
I/O
Description
VCON
30
I
Define reference voltage for VCO
MODE_SET
29
I
Select Controller Clock mode,
INPUT (high): VCO mode
INPUT (low): PLL mode
GPIO[0:9]
42
I/O
General Purpose Input/Output Port
If you use GPIO, you should set SFR(PortFun, PortDir,
PortDat)
41
40
39
38
37
36
35
25
24
PLLCAP
27
–
PLL Capacitor
20
SPECIFICATION
S3F49FAX
Table 6. Signal Description for Power Signal
Signal Name
100-Pin Number
I/O
Description
VDD
13
–
System power supply voltage
–
PCMCIA power supply voltage
–
Ground
19
34
48
54
64
PVDD1
77
PVDD2
94
GND
10
18
47
63
75
VDDA
26
–
Analog power supply voltage for PLL
VSSA
28
–
Analog ground for PLL
Table 7. Signal Description for USB Device
Signal Name
100-Pin Number
I/O
Description
DP
11
I/O
Positive data
DN
12
I/O
Negative data
Table 8. Signal Description for Internal NOR Flash Memory
Signal Name
100-Pin Number
I/O
Description
SDATA
46
I/O
Serial data for internal flash
SCLK
45
I
Serial clock for internal flash
21
SPECIFICATION
3
S3F49FAX
ELECTRICAL DATA
3.1 DC CHARACTERISTICS
Table 9. Absolute Maximum Ratings
Symbol
Parameter
VDD
DC Supply voltage
VIN
DC Input voltage
I IN
DC input current
TSTG
Storage temperature
Ratings
Unit
– 0.3 to 4.0
V
3.3V I/O
–0.3 to 3.6
5.0V I/O
–0.5 to 5.5
V
±10
mA
–40 to 125
°C
Table 10. Recommended Operating Conditions
Symbol
Parameter
Ratings
Unit
VDD
DC supply voltage
3.0 to 3.6
V
TA
Temperature range
–25 to 85
°C
Value
Unit
37-70
°C/W
Table 11. Thermal Characteristics
Symbol
θja
Parameter
Thermal Impedance of Samsung 100TQFP
Package
22
SPECIFICATION
S3F49FAX
Table 12. D.C. Electrical Characteristics (In case of 3.3V Interface I/O)
(VDD = 3.3 ± 0.3V, TA = -25 to 85 °C)
Symbol
Parameter
Conditions
VIH
High level input voltage
LVCMOS
Interface
VIL
Low level input voltage
LVCMOS
Interface
VT
Switching threshold
VT+
Switching trigger,
Switching trigger,
High level input current
IIL
VOH
VOL
Low level input current
High level output voltage
Low level output voltage
0.8
LVCMOS
Input buffer
Input buffer
with pulldown
1.4
VIN = VDD
Input buffer
with pull-up
Type B4, B8
IOH = –1 mA
Type B4
IOH = –4 mA
Type B8
IOH = –8 mA
Type B4, B8
IOL = 1 mA
Type B4
IOL = 4 mA
Tri-state output leakage current
IDD
Maximum operating current
IDS
Stop current
–60
VDD = 3.3 V,
VCON = 2.2 V
V
10
30
60
µA
10
–30
–10
µA
VDD–
0.05
V
2.4
0.05
V
0.4
IOL = 8 mA
VOUT =
VSS or VDD
V
V
–10
VIN = VSS
IOZ
0.8
10
Unit
V
2.0
–10
Input buffer
Type B8
Max
V
LVCMOS
negative-going threshold
IIH
Typ
2.0
LVCMOS
positive-going threshold
VT-
Min
10
µA
45
80
mA
100
150
µA
–10
23
SPECIFICATION
S3F49FAX
Table 13. D.C. Electrical Characteristics (In Case of 5V Interface I/O)
(VDD = 5.0 ± 0.5V, TA = -25 to 85 οC)
Symbol
Parameter
VIH
High level input voltage
VIL
Low level input voltage
VT
Switching threshold
VT+
VT-
Conditions
Min
CMOS
3.5
TTL
2.0
Typ
Max
V
CMOS
1.5
TTL
0.8
CMOS
2.45
TTL
1.45
Switching trigger, positivegoing threshold
CMOS
3.0
3.5
TTL
1.8
2.0
Switching trigger, negativegoing threshold
CMOS
1.5
2.0
TTL
0.8
1.1
Input buffer
IIH
High level input current
IIL
Low level input current
Input buffer
with pull-up
–10
VIN = VDD
Input buffer
VOH
High level output voltage
VOL
Low level output voltage
IOZ
Tri-state output leakage current
IDD
Maximum operating current
IDS
Stop current
10
Input buffer
with pull-up
Type B4
IOH = –4 mA
Type B8
IOH = –8 mA
Type B4
IOL = 4 mA
Type B8
IOL = 8 mA
VOUT =
VSS or VDD
VDD = 5.0 V,
VCON = 2.2 V
–200
V
V
V
V
10
100
–10
VIN = VSS
Unit
200
µA
10
–100
–10
VDD–0.8
µA
V
0.4
V
10
µA
55
80
mA
200
250
µA
–10
24
SPECIFICATION
S3F49FAX
3.2 AC CHARACTERISTICS
Table 14. System Clock Timing
Symbol
Parameter
Min
Typ
Max
Unit
TC
Clock cycle time
40
55
75
ns
Tlpd
Clock low pulse duration
0.4Tc
0.6Tc
ns
Thpd
Clock high pulse duration
0.4Tc
0.6Tc
ns
Tlpd
Thpd
TC
Table 15. POR(Power On Reset) Detection Level
Symbol
Parameter
Min
Typ
Max
Unit
PD
POR Detection Level
1.3
2.1
2.65
V
25
SPECIFICATION
4
S3F49FAX
MECHANICAL DATA
The S3F49FAX disk controller is available in a 100-pin TQFP package (Samsung part number 100-TQFP-1414).
16.00 BSC
0-7
14.00 BSC
14.00 BSC
+ 0.073
- 0.037
0.08 MAX
100-TQFP-1414
0.45-0.75
16.00 BSC
0.127
#100
#1
0.50
+ 0.07
0.20 - 0.03
0.08 MAX
0.05-0.15
(1.00)
1.00 ± 0.05
1.20 MAX
NOTE: Dimensions are in millimeters.
Figure 3. 100-TQFP-1414 Package Dimension
26