Ordering number : ENA0238 Monolithic Linear IC LA73024AV Double Scart Interface IC Overview This LA73024AV is a double scart interface IC. Functions • AV switches, • Changeable Gain AMP • 6dB AMP+driver • FSS output Specifications Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Allowable power dissipation Symbol Conditions Ratings Unit VCCV max 24, 29 pin VCCA max 14 pin 13.0 V Ta ≤ 80°C∗ 760 mW Pd max 6.0 V Operating temperature Topr -20 to +80 °C Storage temperature Tstg -55 to +150 °C ∗ When mounted on a 114.3×76.1×1.6mm3 glass epoxy board. Operating Conditions at Ta = 25°C Parameter Symbol Recommending operation voltage Operating voltage range Conditions VCCV pins 24 and 29 VCCA pin 14 VCCV op pins 24 and 29 VCCA op pin 14 Ratings Unit 5.0 V 12.0 V 4.5 to 5.5 V 11.5 to 12.5 V Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before usingany SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. 83006 / 60206 MS OT B8-6818 No.A0238-1/12 LA73024AV Electrical Characteristics at Ta = 25°C, VCC = ±5.0V, VCCA = 12.0V Ratings Parameter Symbol Conditions min typ Unit max Current dissipation 1 ICCV1 Pin 24 Flow in current when non-signal 16.0 24.0 32.0 mA Current dissipation 2 ICCV2 Pin 29 Flow in current when non-signal 12.0 18.0 24.0 mA Current dissipation 3 ICCA Pin 14 Flow in current when non-signal 17.0 25.0 33.0 mA FSS output H voltage VHFSS Serial control select FSS OUT H VCCA-1.0 VCCA-0.5 VCCA V FSS output M voltage VMFSS Serial control select FSS OUT M 5.0 6.0 7.0 V FSS output L voltage VLFSS Serial control select FSS OUT L 0 0.1 0.5 V FSS output cut off current ICUTOFF Flow out current when Pin 20 M 2.0 3.61 10.0 mA connecting to GND. H 2.0 3.78 10.0 mA VCC3-0.2 VCC3 0 0.7 1.0 V External control terminal H voltage VEXTH RL = 1.8kΩ, VCC3 < 13V External control terminal L voltage VEXTL RL = 1.8kΩ, VCC3 = 5V RL = 10kΩ, VCC3 = 5V 0 0.15 1.0 V IDR RL = 1.8kΩ, VCC3 = 5V 2.2 2.4 2.78 mA RL = 10kΩ, VCC3 = 5V 400 485 500 µA External control terminal drive current V External mute control H VMUTECTLH External mute H, control voltage of Pin 9. 4.0 VCCV V External mute control L VMUTECTLL External mute L, control voltage of Pin 9. 0 1.0 V dB Video switches part Voltage gain V1 VG1V Pins 25 and 26 output, 100% white 5.6 6.1 6.6 Voltage gain V2 VG2V Pin 5 output G2 D6-L, 100% white -0.4 0.1 0.6 dB Voltage gain V3 VG3V Pin 5 output G2 D6-H,100% white 5.6 6.1 6.6 dB dB Frequency characteristics VF f = 100kHz/7MHz -0.5 -0.0 0.5 DG differential gain DG VIN = 1Vp-p -1.0 0.0 1.0 % DP differential phase DP VIN = 1Vp-p -1.5 0.0 1.5 deg 1.15 2.0 V Output voltage VOUT Pins 25 and 26 DC voltage when non-signal. Audio switches part Voltage gain 1A VG1A Serial control select 0dB. -0.3 0.2 0.7 dB Voltage gain 2A VG2A Serial control select 2dB. 1.7 2.2 2.7 dB Voltage gain 3A VG3A Serial control select 4dB. 2.7 4.2 4.7 dB Voltage gain 4A VG4A Serial control select 6dB. 5.7 6.2 6.7 dB Voltage gain 5A VG5A Serial control select 6dB. 11.7 12.2 12.7 dB Maximum output level VOMAX 2 3.0 Output level at the time of f = 1kHz, Vrms THD = 2% Total harmonic distortion THD VIN = 1Vrms, f = 1kHz, AMP 0dB 0.06 0.20 % Output noise voltage VONOISE Rg = 1kΩ, JIS-A FILTER -100 -90 dBm Cross talk between channel VCTKA VIN = 1Vrms, f = 1kHz -90 -75 dB Mute attenuation VMUTEA VIN = 1Vrms, f = 1kHz -90 -75 dB Input impedance ZIN 40 50 60 kΩ Output off set voltage VOFSET -20 0 20 mV Off set voltage at the time of changeover SW. Design guarantee Items Ratings Parameter Mute attenuation Cross-talk between channel Symbol VMUTEV VCTKV Conditions min typ max Unit VIN = 1Vp-p, f = 4.43MHz -60 -50 dB VIN = 1Vp-p, f = 4.43MHz Driver output terminated with 75Ω. -60 -50 dB No.A0238-2/12 LA73024AV Package Dimensions unit : mm 3277 15.0 0.5 5.6 7.6 23 44 22 0.22 0.2 (1.5) 1.7max 0.65 0.1 1 (0.68) SANYO : SSOP44(275mil) No.A0238-3/12 LA73024AV Block Diagram and Sample Application Circuit No.A0238-4/12 LA73024AV Pin Functions Pin No. Pin name 1 AIN1R 2 AIN1L AIN2R 10 11 15 AIN2L AIN3R 16 AIN3L 33 AIN4L AIN4R 34 36 Function Audio input terminal. 37 AIN5L AIN5R 3 EXTCTL1 General purpose output. 4 EXTCTL2 Open collector. 19 EXTCTL3 35 EXTCTL4 DC voltage Equivalent circuit 5.58V 2.5mA, ON → 0.75V OFF → OPEN 5 VOUT Video output terminal. 1.10V Push-pull output Low-impedance. 0V 6 GND 17 GND 27 GND (EXT-75Ω Driver) 32 GND (DEC-75Ω Deiver) 38 GND Continued on next page. No.A0238-5/12 LA73024AV Continued from preceding page. Pin No. Pin name 7 VIN1 Video input terminal. Function 13 VIN2 Sync-tip clamp input 18 VIN3 Hi-impedance. 23 VIN4 28 VIN5 8 PWRSAV Power save mode select pin. DC voltage Equivalent circuit 1.8V 0.2V OPEN: L 9 AUMUTE Control terminal for audio mute. 0.05V OPEN: LOW 12 REFFIL Terminal for Ref_DC ripple 4.94V removing. 14 VCC12 VCC for audio. Continued on next page. No.A0238-6/12 LA73024AV Continued from preceding page. Pin No. Pin name Function 20 FSSOUT FSS control terminal. DC voltage Equivalent circuit H: VCC-0.5V Output H, M, L 3 values with serial control. M: 6V L: 0V 21 DATA Serial data input terminal. Conformed to I2C BUS. 22 CLOCK Serial clock input terminal. Conformed to I2C BUS. 24 VCC5A Control VCC for Video. 25 VOUT75A Video driver output terminal. 26 VOUT75B Push-pull output Power save → open 1.10V Low-impedance. 29 VCC5B Always VCC for Video. Continued on next page. No.A0238-7/12 LA73024AV Continued from preceding page. Pin No. Pin name Function 30 AOUT2L Audio output terminal 31 AOUT2R Push-pull output 42 AOUT3L Low-Impedance 43 AOUT3R 39 AOUT1L AOUT1R 40 Audio output terminal DC voltage Equivalent circuit 4.91V 4.91V Push-pull output Low-Impedance 41 PWRMUTE1 44 PWRMUTE2 Output terminal of audio muting 0V Power Save LA73024AV has two supplies 5V for Video part and 12V for audio part and FSS output. LA73024AV separates perfectly 5V system from 12V system, so it can be individually movement. For example when in the stand-by mode, if you open 14 pins but 5V supplies 24 and 29 pins, Video part and serial control part work normally. In this case audio part and FSS output don’t work normally. And when you pull up 8pin and open 24 pin , IC chooses automatically video sw3-B.Consequently Ext input and Decoder output only move , you can save more power dissipation . Audio Mute LA73024AV builds in two mute transistors for reduce audio pop-noise when occur at power on and off. You can control both on serial control and on external parallel control for audio mute. No.A0238-8/12 LA73024AV Serial Control Specification Slave address MSB 1 0 0 1 0 0 0 LSB 0 ↑ Slave receiver Data format S Slave address (8bit) ↑ Start condition A Sub address (8bit) ↑ Acknowledge A Data address (8bit) A P ↑ Stop condition Sub address and data byte table Data byte (Underline is initial setting.) Sub address Hexadecimal D8 01 (0000 0001) 02 (0000 0010) D7 D6 D5 D4 D3 D2 D1 SW1 SW2 SW3 FSSOUT 00: C 00: D 00: C 00: HIGH 01: B 01: C 01: B 01: HIGH 10: A 10: B 10: A 10: MID 11: A 11: A 11: * 11: LOW EXT EXT AMP GAIN AUDIO AMP GAIN1 AUDIO AMP GAIN2 CTL1 CTL2 VPS OUT (DEC OUT) (EXT OUT) 000: 0dB 00: 0dB 0: L 0: L 0: 0dB 001: 2dB 01: 2dB 1: H 1: H 1: 6dB 010: 4dB 10: 4dB 011: 6dB 11: 6dB 100:12dB MUTE1 MUTE2 MUTE3 MUTE4 MUTE5 MUTE6 EXT EXT VSW1 OUT VSW2 OUT VSW3 OUT ASW1 OUT ASW2 OUT ASW3 OUT CTL3 CTL4 03 (0000 0011) 0: through 0: through 0: through 0: through 0: through 0: through 0: L 0: L 1: MUTE 1: MUTE 1: MUTE 1: MUTE 1: MUTE 1: MUTE 1: H 1: H Data transfer I2C-BUS control system is adopted in SW IC and SW IC is controlled by SCL (Serial Clock) and SDA (Serial Data) At first, please set up the START condition*1 by these two terminals (SCL and SDA). And next, please input the 8bits data which should be synchronized with SCL into SDA terminal. Still more, please give priority to high rank bit at data transfer order (MSB → LSB). The 9th bit is called as ACK (Acknowledge), SW IC sends [0] to the SDA terminal during SCL [1] period. So, please open the port of micro-processor during this period. LA73024AV adopt auto-increment, so you input only first sub-address data (called as Group) and you can transfer data in order. As thus the Data transfer Stop condition*2 is finished. *1 SDA rise up during SCI is [1] *2 SDA fall down during SCL is [1] No.A0238-9/12 LA73024AV Transfer data format The transfer data is composed by START condition, Slave address data*3, and STOP condition. After setting up the START condition, please transfer the Slave Address (regulated as “1001000” in SW IC). Group and next control data (Please see the Fig. 1) Slave Address is composed by 7bits, and this bit 8th bit*4 should be set as [0]. But SW IC is not equipped with such a data out function, please keep this bit as [0]. The both of Group data and control data are composed by 8bits, and the one control action is defined with combination of these two data. And if you want to control 2 or more groups at the same mode, you can realize it by sending some control data together. The data makes meaning with all bits, so you cannot stop the sending until all data transfer is over. But LA73024AV adopt auto-increment, for example you can stop to transfer STOP condition after group 2 data . If you want to stop transfer action, please transfer the STOP condition without fail. *3 There are 3 control groups. *4 This 8th bit called as R/W bit, and this bit shows the data transmission direction. [0] means send mode (accept mode with SW IC) and [1] means accept mode (send mode with SW IC) fundamentally. Data structure START condition Slave Address R/W ACK Group ACK Control data ACK … STOP condition Initialize SW IC is initialized as the following mode for circuit protection. Please see “Sub address and data byte table” on page 9. Characteristics of the SDA and SCL 1/0 stages for SW IC Symbol min max LOW level input voltage Parameter VIL 0 1.5 V HIGH level input voltage VIH 3.5 5.0 V LOW level output current IOL 3.0 mA fSCL 100 kHz SCL clock frequency unit Set-up time for a repeated START condition tSU: STA 4.7 µs Hold time START condition. After this period, the first clock pulse is generated. tHD: STA 4.0 µs tLOW 4.7 tR 0 tHIGH 4.0 tF 0 LOW period of the SCL clock Rise time of both SDA and SDL signals HIGH period of the SCL clock Fall time of both SDA and SDL signals µs 1.0 µs µs 1.0 µs µs Data hold time tHD: DAT 0 Data set-up time tSU: DAT 250 ns Set-up time for STOP condition tSU: STO 4.0 µs tBUF 4.7 µs BUS free time between a STOP and START condition Definition of timing No.A0238-10/12 LA73024AV Test Circuit No.A0238-11/12 LA73024AV Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 2006. Specifications and information herein are subject to change without notice. PS No.A0238-12/12