SANYO LC72725KM_10

Ordering number : ENA0503
LC72725KM,
LC72725KV
CMOS IC
RDS(RBDS) Demodulation IC
Overview
The LC72725KM and LC72725KV are ICs that implement the signal processing required by the European Broadcasting
Union RDS (Radio Data System) standard and by the US NRSC (National Radio System Committee) RBDS (Radio
Broadcast Data System) standard. These ICs include band-pass filter, demodulator, and data buffer on chip. RDS data
can be read out from this on-chip memory by external clock input in slave operation mode.
Functions
• Bandpass filter: Switched capacitor filter (SCF)
• RDS Demodulation: 57KHz carrier and RDS data clock regeneration, biphase decode, differential decode.
• Buffer: 128 bit (about 100ms) can be restored in the on-chip data buffer RAM.
• Data output: Master or slave output mode can be selected.
• RDS-ID: Detect RDS signal which can be reset by RST signal input.
• Standby control: Crystal oscillator can be stopped.
• Fully adjustment free
• Low Voltage
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSSd = VSSa = 0V
Parameter
Symbol
Pin Name
Maximum supply voltage
VDD max
VDDd, VDDa *
Maximum input voltage
VIN1 max
Maximum output voltage
Maximum output current
Conditions
VDDa≤VDDd+0.3V
Ratings
Unit
-0.3 to +6.5
V
TEST, MODE, XIN, RDCL, RST
-0.3 to VDDd+0.3
V
VIN2 max
MPXIN, CIN
-0.3 to VDDa+0.3
V
VO1 max
RDS-ID(READY)
-0.3 to +6.5
V
VO2 max
XOUT, RDDA, RDCL
-0.3 to VDDd+0.3
V
VO3 max
FLOUT
-0.3 to VDDa+0.3
IO1 max
XOUT, FLOUT, RDDA, RDCL
+2.0
mA
IO2 max
RDS-ID(READY)
+8.0
mA
V
* VDDa≤VDDd+0.3V
Continued on next page.
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before usingany SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
91306HKIM 20060822-S00002,20060823-S00002 No.A0503-1/9
LC72725KM, 72725KV
Continued from preceding page.
Parameter
Symbol
Allowable power dissipation
Pd max
Operating temperature
Storage temperature
Pin Name
Conditions
Ratings
Unit
(Ta≤85°C)MFP16
140
mW
mW
(Ta≤85°C)SSOP16
100
Topr1
VDD = 2.7V to 5.5V
-20 to +70
Topr2
VDD = 3.0V to 5.5V
-40 to +85
°C
-40 to +125
°C
Tstg
°C
Allowable Operating Ranges at Ta = -20 to +70°C, VSSd = VSSa = 0V, VDDd = VDDa = 2.7V to 5.5V
Ta = -40 to +85°C, VSSd = VSSa = 0V, VDDd = VDDa = 3.0V to 5.5V
Parameter
Symbol
Pin Name
Ratings
Conditions
min
Supply voltage
Input high-level voltage
Input low-level voltage
Input amplitude
Guaranteed crystal
VDDd, VDDa
Ta = -20 to +70°C
2.7
5.5
VDD2
VDDd, VDDa
Ta = -40 to +85°C
3.0
5.5
VIH1
TEST, MODE, RST
0.7VDDd
6.5
V
VIH2
RDCL
0.7VDDd
VDDd
V
0
0.3VDDd
V
VDDd
V
VIL
TEST, MODE, RST,
VO1
RDDA, RDCL
VO2
RDS-ID(READY)
VIN
MPXIN
f = 57±2kHz
VXIN
XIN
Xtal
XIN, XOUT
CI≤120Ω
TXtal
XIN, XOUT
Fo = 4.332MHz
V
6.5
V
1.6
50
mVrms
400
1500
mVrms
4.332
oscillator frequencies
Crystal oscillator operating
unit
max
VDD1
RDCL
Output voltage
typ
MHz
±100
range
ppm
RDCL setup time
tCS
RDCL, RDDA
0
μs
RDCL high-level time
tCH
RDCL
0.75
μs
RDCL low-level time
tCL
RDCL
0.75
Data output time
tDC
RDCL, RDDA
0.75
μs
READY output time
tRC
RDCL, READY
0.75
μs
READY low-level time
tRL
READY
107
ms
μs
No.A0503-2/9
LC72725KM, 72725KV
Electrical Characteristics for the Allowable Operating Ranges
Parameter
Symbol
Pin Name
Ratings
Conditions
min
Input resistance
Rmpxin
Rcin
Internal feedback
unit
typ
max
MPXIN-VSSa
f = 57kHz
100
kΩ
CIN-VSSa
f = 57kHz
100
kΩ
1.0
MΩ
Rf
XIN
Center frequency
fc
FLOUT
56.5
57.0
57.5
kHz
-3dB band width
BW-3dB
FLOUT
2.5
3.0
3.5
kHz
31
34
dB
resistance
Gain
Gain
MPXIN-FLOUT
f = 57kHz
28
Stop band attenuation
Att1
FLOUT
Δf = ±7kHz
30
dB
Att2
FLOUT
F<45kHz, f>70kHz
40
dB
Att3
FLOUT
F<20kHz
50
dB
Reference voltage output
Vref
Vref
VDDa = 3V
Hysteresis
VHIS
TEST, MODE, RST,
RDCL
Output low-level voltage
VOL1
RDDA, RDCL
I = 2mA
VOL2
RDS-ID(READY)
I = 8mA
Output high-level voltage
VOH
RDDA, RDCL
I = 2mA
Input high-level current
IIH1
TEST, MODE, RST,
VI = 6.5V
1.5
V
0.1VDDd
V
0.4
0.4
VDDd-0.4
IIH2
XIN
VI = VDDd
IIL1
TEST, MODE, RST,
VI = 0V
2.0
RDCL
Output off leakage
IIL2
XIN
VI = 0V
IOFF
RDS-ID(READY)
VO = 6.5V
IDD
VDDd+VDDa
VDDd+VDDa
2.0
current
Current drain
Package Dimensions
Package Dimensions
unit : mm (typ)
3035B [LC72725KM]
unit : mm (typ)
3178B [LC72725KV]
μA
11
μA
5.0
μA
11
μA
5.0
μA
mA
5.2
10.0
9
9
4.4
0.63
4.4
6.4
16
8
1
6.4
16
0.15
1
8
0.65
(0.33)
0.15
0.22
1.5max
1.7max
(1.5)
0.5
0.35
0.1
(1.3)
SANYO : MFP16(225mil)
0.1
1.27
5.0
5
(VDDd = VDDa = 3V)
(0.56)
V
V
RDCL
Input low-level current
V
SANYO : SSOP16(225mil)
No.A0503-3/9
LC72725KM, 72725KV
16 15 14 13 12 11 10
TEST
MODE
VDDd
VSSd
XIN
XOUT
RDCL
RST
Pin Assignment
9
1
2
3
4
5
6
7
8
RDS-ID/READY
RDDA
VREF
MPXIN
VDDa
VSSa
FLOUT
CIN
LC72725KM,
LC72725KV
Top view
Block Diagram
VREF
+3V
FLOUT
CIN
+3V
VDDa
VSSa
MPXIN
PLL
(57kHz)
REFERENCE
VOLTAGE
CLOCK
RECOVERY
(1187.5Hz)
VSSd
VREF
ANTIALIASING
FILTER
57kHz
BPF
(SCF)
VDDd
DATA
DECODER
SMOOTHING
FILTER
RDDA
RDCL
RAM
(128bit)
RST
CLK(4.332MHz)
TEST
TEST
RDS-ID
DETECT
OSC
XIN
MODE
RDS-ID/
READY
XOUT
No.A0503-4/9
LC72725KM, 72725KV
Pin Descriptions
Pin No.
Pin Name
I/O
3
VREF
Output
Function
Reference voltage output (Vdda/2)
Pin Circuit
VDDa
VSSa
4
MPXIN
Input
Baseband (multiplexed) signal input
VDDd
VSSd
7
FLOUT
Output
8
CIN
Input
Subcarrier output (filter output)
Subcarrier input (comparator input)
VDDa
VSSa
5
VDDa
-
Analog system power supply (+3V)
6
VSSa
-
Analog system ground
14
XOUT
Output
13
XIN
Input
Crystal oscillator output (4.332MHz)
VREF
VDDd
Crystal oscillator input
(external reference signal input)
XIN
VSSd
XOUT
9
TEST
Test input
10
MODE
Read out mode (0:master, 1:slave)
15
RST
2
RDDA
S
RDS-ID/RAM reset (active high)
Output
VSSd
RDS data output
VDDd
VSSd
16
RDCL
I/O
RDS clock output (master mode) /
VDDd
RDS read out clock input (slave mode)
S
1
RDS-ID/
Output
READY
VSSd
RDS reliability data output
(High:data with high RDS reliability
Low: data with low RDS reliability)
READY output (active high)
12
VDDd
-
Digital system power supply (+3V)
11
VSSd
-
Digital system ground
VSSd
No.A0503-5/9
LC72725KM, 72725KV
Input/Output Data Format
TEST
MODE
RDCL Pin
RDS-ID/READY Pin
0
0
Master read out mode
Circuit Operation Mode
Clock output
RDS-ID output
0
1
Slave read out mode
Clock input
READY output
1
0
Standby mode (crystal oscillator stopped)
-
-
1
1
IC test mode which is not available to user applications.
-
-
RST Pin
RST = 0
Normal operation
RST = 1
RDS-ID • demodulation circuit clear + READY • memory clear (when slave mode)
RDS-ID/READY Pin
Master mode
RDS-ID output (Active-high)
Slave mode
READY output (Active-high)
Note: RDS-ID(READY) pin is an n-channel open-drain output, and requires an external pull-up resistor to output data.
RDCL/RDDA Output Timing in Master Mode
421μs
421μs
Tp1
RDCL output
RDDA output
17μs Tp21
17μs
RDS-ID Output Timing
RDS-ID
High/Low
High/Low
High/Low
High/Low
High/Low
High/Low
High/Low
RDCL
RDDA
Note: RDS-ID is High: data with high RDS reliability, Low: data with low RDS reliability
No.A0503-6/9
LC72725KM, 72725KV
RST Operation in Master Mode
Tp3≥250ns
RST
≈ ≈≈
RDSdetection circuit output
(IC internal)
RDCL
RDDA
Note: RDCL and RDDA outputs keep high level after input of RST until RDS detection circuit output is
detected.
RDCL Operation in Slave Mode
tRH
tCS
tCH
tDC
≈
RDCL
tCS
≈≈ ≈
READY
tRC
tCL
RDDA
Parameter
Symbol
Pin Name
Ratings
Conditions
min
typ
unit
max
RDCL setup time
tCS
RDCL,RDDA
0
μs
RDCL high-level time
tCH
RDCL
0.75
μs
RDCL low-level time
tCL
RDCL
0.75
Data output time
tDC
RDCL,RDDA
0.75
μs
READY output time
tRC
RDCL,READY
0.75
μs
READY high-level time
tRH
READY
107
ms
μs
No.A0503-7/9
LC72725KM, 72725KV
Notes: 1. RDCL input must be started after READY signal goes high. When READY signal is low, RDCL must be
low level.
2. READY status must be checked after tRC time from RDCL is set low. If the READY status is high, then next
read cycle can be continued. If the READY status is low, next RDCL clock input must be stopped.
3. If the above condition is satisfied, RDS data (RDDA) can be read out at both rising and falling edge of RDCL.
4. READY signal goes low after the last data is read out from on-chip memory. If one RDS data is stored in the
memory, READY signal goes high again.
5. When the reception channel is changed, a memory and READY reset must be applied using RST input. If a
reset is not applied, reception data from the previous channel may remain in memory. If RST input is applied,
reception data is not stored in memory until the first RDS-ID is detected, and READY output goes high after
the first RDS-ID is detected. After the first RDS-ID is detected, reception data is stored even if RDS-ID is not
detected.
6. The readout mode may be switched between master and slave modes during readout.
Applications must observe the following points to assure data continuity during this operation.
1) Data acquisition timing in master made
Data must be read on the falling edge of RDCL
2) Timing of the switch from master mode to slave mode
After the RDCL output goes low and the RDDA data has been acquired, the application must set MODE
high immediately.
Then, the microcontroller starts output by setting the RDCL signal low.
The microcontroller RDCL output must start within 840μs (tms) after RDCL went low.
In this case, if the last data read in master mode was data item n, then data starting with item n+1
will be written to memory.
3) Timing of the switch from slave mode to master mode
After all data has been read from memory and READY has gone high, the application must then wait
until READY goes low once again the next time (timing A in the figure), immediately read out one bit of
data and input the RDCL clock.
Then, at the point READY goes high, the microcontroller must terminate RDCL output and then set
MODE low.
The application must switch MODE to low within 840μs (tms) after READY goes low (timing A in the
figure).
RDCL (microcontroller status)
RDCL (IC status)
INPUT
OUTPUT
OUTPUT
INPUT
≈ ≈≈ ≈
tms
INPUT
OUTPUT
undefined
≈≈
RDCL
MODE
ts m
READY
RDDA
n-2
n-1
n
n+1
≈≈
≈
Timing A
m
m+1
m+2
No.A0503-8/9
LC72725KM, 72725KV
Sample Application Connection Circuit (for master mode operation)
VDDd
10kΩ
RDSID/READY
1
RDSID/READY
2
RDDA
10μF
VSSa
+
MPXIN
3
RDDA
RST
VREF
XOUT
16
5
15
RST
14
MPXIN
XIN
VDDa
VDDd
VSSa
VSSd
13
12
0.1μF
6
VSSa
7
560pF
RDCL
4.332MHz
4
330pF
VDDa
RDCL
8
FLOUT
CIN
MODE
TEST
VDDd
0.1μF
22pF
22pF
VSSd
VSSd
11
VSSd
10
9
VSSd
Note: If the RST pin is unused, it must be connected to ground.
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performance, characteristics, and functions of the described products in the independent state, and are
not guarantees of the performance, characteristics, and functions of the described products as mounted
in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an
independent device, the customer should always evaluate and test devices mounted in the customer's
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and all semiconductor products fail with some probability. It is possible that these probabilistic failures
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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
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This catalog provides information as of September, 2006. Specifications and information herein are subject
to change without notice.
PS No.A0503-9/9