Ordering number : ENA1948 CMOS IC LC749403BG Silicon gate LCD Picture Quality Improvement IC Overview LC749403BG is a IC which enables higher picture quality in LCD products by improving the signals outputed to the LCD panel. In addition to the function to improve the picture quality of the color equation and the brightness correction, smooth picture quality is realized by converting One Seg video from 15fps to 30fps using flame interpolation technique. It supports up to WVGA resolution. * Features (1) Digital Input/Output • Supports digital video input: YCbCr/YPbPr 24bit,16bit (4: 2: 2) signals or ITU-R BT.656 (8bit) input • Digital RGB 24 bit signal input • Digital RGB 18bit/24bit signal output • Digital YCbCr 16bit/24bit signal output (2) Picture Quality Improvement Function • Y signal picture quality improvement: brigntness adjustment, contour correction,CDEX (Color Depth Expander), • C signal picture quality improvement: color exciter,skin color correction,color and hue adjustment • RGB signal picture quality improvement: brightness, contrast, white balance, black balance, gamma correction (3) Panel Interface • Embedded timing controller for panel driver • Automtic timing signal generation for panel protection • PWM for backlight control (video adaptation low power consumtion processing) (4) Frame interpolation (×2) for One-Seg broadcast • Double-speed (×2) mode (15fps ⇒ 30fps) Intermediate image is predicted from the previous and next image. *: Video input of the LC749403BG meets the following conditions: (1) horizontal resolution is under 880 dots, and (2) vertical resolution is under 480 lines. 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To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 41311HKPC 20110318-S00006 No.A1948-1/13 LC749403BG LSI Specifications • Power supply voltage (typ) Core block: 1.2V SDRAM I/F block: 1.8V I/O block: 1.8V/2.85V/3.3V selectable • Maximum operating frequency internal: 36MHz SDRAM I/F block: 80MHz • Package: FBGA144 11mm × 11mm (stacked MCP with SDRAM) Target Application • LCD display devices, One-Seg broadcast receiver (Car-Navigation, One-Seg TV, Portable DVD player, etc) Frame interpolation (×2) example Smooth image quality is realized by converting One Seg video from 15fps to 30fps using flame interpolation technique Jumpy motion Smooth motion Intermediate image is predicted from the previous and next image Interpolation OFF (15frame/s) Interpolation ON (30frame/s) Actual image Interpolated image Actual image No.A1948-2/13 LC749403BG CDEX (Color Depth Expander) Example This specification may be changed without any notices for product improvement. Original CDEX Specifications Absolute Maximum Ratings at Ta = 25°C, DVSS = 0V, AVSS_PLL = 0V, AVSS_OSC = 0V, SDVSS = 0V, SDVSSQ = 0V Parameter Symbol Conditions Ratings unit Maximum supply voltage (I/O) DVDD_IO -0.3 to +3.96 Maximum supply voltage (SDRAM, SDRAMIF I/O, PLL) DVDD_SDIO, AVDD_PLL, V Maximum supply voltage (core, osc) SDVDD, SDVDDQ DVDD_CORE -0.3 to +2.6 V Digital input voltage AVDD_OSC VI -0.3 to +1.8 V -0.3 to DVDD_IO+0.3 V Digital output voltage VO -0.3 to DVDD_IO+0.3 V Operating temperature Topr -40 to +85 °C Storage temperature Tstg -55 to +125 °C Allowable Operation Ranges at Ta = -40 to +85°C, DVSS = 0V, AVSS_PLL = 0V, AVSS_OSC = 0V, SDVSS = 0V, SDVSSQ = 0V Parameter Symbol Ratings Conditions min Supply voltage (I/O) DVDD_IO typ unit max 2.6 2.85 3.6 V 1.7 1.8 1.95 V Supply voltage (SDRAMIF I/O) DVDD_SDIO 1.7 1.8 1.95 V Supply voltage (SDRAM, PLL) SDVDD, SDVDDQ AVDD_PLL 1.7 1.8 1.95 V Supply voltage (core, osc) DVDD_CORE 1.14 1.2 1.26 V Input voltage range AVDD_OSC VIN DVDD_IO V 0 No.A1948-3/13 LC749403BG DC Characteristics at Ta = -40 to +85°C, DVSS = 0V, AVSS_PLL = 0V, AVSS_OSC = 0V, SDVSS = 0V, SDVSSQ = 0V, DVDD_IO = 1.7 to 3.6V, DVDD_SDIO = 1.7 to 1.95V, DVDD_CORE = 1.14 to 1.26V, SDVDD = 1.7 to 1.95V, SDVDDQ = 1.7 to 1.95V Parameter Symbol Ratings Conditions min Input high-level voltage VIH Input low-level voltage VIL Input high-level current IIH unit typ CMOS level inputs 0.7DVDD_IO CMOS level schmitt inputs 0.7DVDD_IO max V V CMOS level inputs 0.3DVDD_IO V CMOS level schmitt inputs 0.3DVDD_IO V VI=DVDD_IO VI=DVDD_IO, with pull-down resistor Input low-level current IIL Output high-level voltage VOH VI=DVSS 10 μA 100 μA -10 μA DVDD_IO-0.4 V CMOS voltage: 2.6V to 3.6V, 1.7V to 1.9V I/O type D: IOH = -1mA I/O type E: IOH = -1mA (2mA mode) IOH = -2mA (4mA mode) I/O type F: IOH = -2mA (4mA mode) IOH = -4mA (8mA mode) I/O type G: IOH = -2mA I/O type H: IOH = -1mA (2mA mode) IOH = -2mA (4mA mode) Output low-level voltage VOL CMOS Output leakage current IOZ In high-impedance output mode Pull-down resistance RDN condition : typ Ta = 25°C DVDD_IO = 2.85V DVDD_CORE = 1.2V 0.4 V 3 μA 98 kΩ 69 kΩ 25 mA 112 mA 35 μA condition : typ Ta = 25°C DVDD_IO = 1.8V DVDD_CORE = 1.2V Operating current drain IDDOP condition : typ Ta = 25°C DVDD_IO = 2.85V DVDD_CORE = 1.2V QVGA, tck = 6.6MHz 10step condition : typ Ta = 25°C DVDD_IO = 2.85V DVDD_CORE = 1.2V WVGA, tck = 34.24MHz 10step Static current drain *1 IDDST condition : typ Ta = 25°C DVDD_IO = 2.85V DVDD_CORE = 1.2V Output open, VI = DVSS or DVDD_IO *1: Certain input pins have build-in pull-down resistors. Thus there are cases where, due to the circuit sturucture, the static current drain can not beguranteed. No.A1948-4/13 LC749403BG Package Dimensions unit : mm (typ) 3409 TOP VIEW BOTTOM VIEW 0.8 1.1 1 2 3 0.8 4 5 6 7 11.0 8 9 11 10 12 1.1 11.0 0.4 SIDE VIEW ML K J HGFEDCBA 1.4 MAX 0.5 SANYO : FBGA144(11.0X11.0) Pin Assignment LC749403BG 1 2 3 4 5 6 7 8 9 10 11 12 A B C D E F G H J K L M Top View No.A1948-5/13 Ocillator PDWN INTO TEST SCK_SCL SRXD_SDA STXD SCS_I2SEL SIOSEL XRST BLCON PWM DHSI DVSI DDEI DCKI XTALI DCRIN[7:0] Panel Protection DCBIN[7:0] Dynamic γ W/BL stretch H/V contour LTI TCON Bypass Dither OSD Mix RGB γ Brightness/contrast White/black balance Color Space Convert Color Exciter Color Gain FTI HUE CTI Color Depth Expander Frame Interpolation (×2) Color Space Convert DYGIN[7:0] Timing Controler LC749403BG Block Diagram SDRAM LC749403BG SDRAM Controler DYGOUT[7:0] DCBOUT[7:0] delay DCROUT[7:0] DVSO DHSO DDEO DCKO GRST FLM OE CPV STRB SP DEXR POL OSDBL PWM I²C/SIO MPU No.A1948-6/13 LC749403BG Pin Functions Pin No. I/O Format Pin symbol Connecting destination I/O Format A1 AVDD_OSC P - Core voltage Analog A2 RC_BIAS I J Resistor Analog A3 AVSS_OSC P - GND Analog A4 DHSI I C CMOS Digital Remarks Bias resistor connection (connect this pin to GND with a 20kΩ) Horizontal synchronizing signal. Data enable signal. Connect this pin to GND in the internal A5 DDEI I C CMOS Digital A6 STXD O D CMOS Digital SIO data A7 SCK_SCL I C CMOS Digital Bus clock (common to SIO and I2C) A8 XTALI I C CMOS Digital A9 TEST I B CMOS Digital A10 AVDD_PLL P - PLL voltage Analog A11 PDO O J A12 AVSS_PLL P - GND B1 DCRIN2 I C CMOS Digital B2 DVDD_CORE P - Core voltage Digital B3 DVSS P - GND Digital B4 DVSS P - GND Digital B5 DVSI I C CMOS Digital Vertical synchronizing signal B6 SRXD_SDA I/O G CMOS Digital SIO data input/I2C data input/output B7 XRST I A CMOS Digital System reset (“L” reset) B8 DCKI I C CMOS Digital Video clock. B9 DVDD_SDIO P - IO voltage Digital B10 DVSS P - GND Digital B11 DVSS P - GND Digital B12 DCKO O F CMOS Digital Video clock output C1 DCRIN1 I C CMOS Digital R/Cr video. Connect this pin to GND when not to be used. C2 DCRIN0 I C CMOS Digital R/Cr video. Connect this pin to GND when not to be used. C3 SDVSS P - GND Digital SDRAM ground C4 SDVSS P - GND Digital SDRAM ground C5 DVDD_CORE P - Core voltage Digital C6 INTO O D CMOS Digital C7 PDWN I A CMOS Digital C8 SIOSEL I C CMOS Digital C9 DVSS P - GND Digital C10 DVSS P - GND Digital C11 DHSO/SP2 O E CMOS Digital C12 DVSO/FLM2 O E CMOS Digital Analog generation mode. Panel protection, PWM generation clock Connect this pin to GND when not to be used. Test (Normally, connect this pin to GND) Test (Normally, connect this pin to GND) Analog R/Cr video. Connect this pin to GND when not to be used. Interrupt “L” power down Connect this pin to GND when not to be used. ”L”: I2C slave, ”H”: 3 wire SIO Horizontal synchronizing signal/Start pulse signal for source driver Vertical synchronizing signal/Start pulse signal for gate driver Continued on next page. No.A1948-7/13 LC749403BG Continued from preceding page. Pin No. Pin symbol Input/output format I/O Format Connecting destination Remarks D1 DCRIN3 I C CMOS Digital R/Cr video. Connect this pin to GND when not to be used. D2 DCRIN4 I C CMOS Digital R/Cr video. Connect this pin to GND when not to be used. D3 DCRIN5 I C CMOS Digital R/Cr video. Connect this pin to GND when not to be used. D4 DVSS P - GND Digital D5 SDVSS P - GND Digital D6 SDVSS P - GND Digital SDRAM ground D7 SDVDD P - IO voltage Digital SDRAM power D8 SDVDD P - IO voltage Digital SDRAM power D9 PWM O D CMOS Digital D10 OSDBL I C CMOS Digital D11 SCS_I2SEL I A CMOS Digital D12 DDEO O E CMOS Digital E1 DCRIN7 I C CMOS Digital E2 DCRIN6 I C CMOS Digital E3 DYGIN1 I C CMOS Digital SDRAM ground Pulse width modulation waveform Data enable signal for external OSD. (Connect to GND when not used.) SIO chip enable/I2C slave select Data enable signal R/Cr video(MSB). Connect this pin to GND when not to be used. R/Cr video. Connect this pin to GND when not to be used. G/Y/656 video. Connect this pin to GND when not to be used. G/Y/656 video (LSB). E4 DYGIN0 I C CMOS Digital E5 DVDD_IO P - IO voltage Digital E6 DVDD_IO P - IO voltage Digital E7 DVDD_IO P - IO voltage Digital E8 DVDD_CORE P - Core voltage Digital E9 DBOUT4 O E CMOS Digital B/Cb/C video E10 DBOUT5 O E CMOS Digital B/Cb/C video E11 DBOUT6 O E CMOS Digital B/Cb/C video E12 DBOUT7 O E CMOS Digital B/Cb/C video (MSB) F1 DYGIN3 I C CMOS Digital G/Y/656 video. Connect this pin to GND when not to be used. F2 DYGIN2 I C CMOS Digital G/Y/656 video. Connect this pin to GND when not to be used. F3 DYGIN5 I C CMOS Digital G/Y/656 video. Connect this pin to GND when not to be used. G/Y/656 video. Connect this pin to GND when not to be used. Connect this pin to GND when not to be used. F4 DYGIN4 I C CMOS Digital F5 DVDD_CORE P - Core voltage Digital F6 DVDD_CORE P - Core voltage Digital F7 DVDD_IO P - IO voltage Digital F8 DVDD_CORE P - Core voltage Digital F9 DBOUT1 O E CMOS Digital B/Cb/C video F10 DBOUT3 O E CMOS Digital B/Cb/C video F11 DBOUT0 O E CMOS Digital B/Cb/C video (LSB) F12 DBOUT2 O E CMOS Digital B/Cb/C video Continued on next page. No.A1948-8/13 LC749403BG Continued from preceding page. Pin No. Pin symbol Input/output format I/O Format Connecting destination Remarks G1 DCBIN0 I C CMOS Digital B/Cb/C video G2 DYGIN6 I C CMOS Digital G/Y/656 video G3 DYGIN7 I C CMOS Digital G/Y/656 video G4 DCBIN1 I C CMOS Digital B/Cb/C video. Connect this pin to GND when not to be used. G5 DVDD_CORE P - Core Voltage Digital G6 DVDD_CORE P - Core Voltage Digital G7 DVDD_SDIO P - IO voltage Digital G8 DVDD_SDIO P - IO voltage Digital G9 DGOUT5 O E CMOS Digital G/Y/656 video G10 DGOUT6 O E CMOS Digital G/Y/656 video G11 DGOUT3 O E CMOS Digital G/Y/656 video G12 DGOUT7 O E CMOS Digital G/Y/656 video (MSB) H1 DCBIN4 I C CMOS Digital B/Cb/C video H2 DCBIN3 I C CMOS Digital B/Cb/C video H3 DCBIN2 I C CMOS Digital B/Cb/C video H4 DCBIN5 I C CMOS Digital B/Cb/C video H5 DVDD_SDIO P - IO voltage Digital H6 DVDD_SDIO P - IO voltage Digital H7 DVDD_SDIO P - IO voltage Digital H8 DVDD_SDIO P - IO voltage Digital H9 DGOUT0 O E CMOS Digital G/Y/656 video (LSB) H10 DGOUT1 O E CMOS Digital G/Y/656 video H11 DGOUT2 O E CMOS Digital G/Y/656 video H12 DGOUT4 O E CMOS Digital G/Y/656 video J1 CPV I/O H CMOS Digital Clock signal for gate driver J2 STRB I/O H CMOS Digital Data strobe signal for source driver J3 DEXR O E CMOS Digital Video inverse signal output for DTR J4 DVSS P - GND Digital J5 DVSS P - GND Digital J6 DVSS P - GND Digital J7 DVSS P - GND Digital J8 DVSS P - GND Digital J9 DVSS P - GND Digital J10 DVSS P - GND Digital J11 DVSS P - GND Digital J12 DROUT7 I/O H CMOS Digital R/Cr video (MSB) Continued on next page. No.A1948-9/13 LC749403BG Continued from preceding page. Pin No. Pin symbol Input/output format Connecting destination I/O Format FLM I/O H CMOS K2 OE I/O H K3 DVSS P - K4 DVSS P K5 DVSS P K6 DVSS K7 DVSS K8 DVSS K1 Remarks Digital Start pulse signal for gate driver CMOS Digital Output enable signal for gate driver GND Digital - GND Digital - GND Digital P - GND Digital P - GND Digital P - GND Digital K9 DVSS P - GND Digital K10 DVSS P - GND Digital K11 DROUT0 I/O H CMOS Digital K12 DROUT6 I/O H CMOS Digital R/Cr video (LSB) R/Cr video B/Cb/C video (MSB). L1 DCBIN7 I C CMOS Digital L2 SP I/O H CMOS Digital Start pulse signal for source driver L3 SDVDDQ P - IO voltage Digital SDRAM power *1 L4 SDVDDQ P - IO voltage Digital SDRAM power *1 L5 SDVDDQ P - IO voltage Digital SDRAM power *1 L6 SDVDDQ P - IO voltage Digital SDRAM power *1 L7 SDVDDQ P - IO voltage Digital SDRAM power *1 L8 SDVDDQ P - IO voltage Digital SDRAM power *1 SDRAM power *1 Connect this pin to GND when not to be used. L9 SDVDDQ P - IO voltage Digital L10 DVSS P - GND Digital L11 DROUT2 I/O H CMOS Digital R/Cr video L12 DROUT5 I/O H CMOS Digital R/Cr video M1 DCBIN6 I C CMOS Digital B/Cb/C video. Connect this pin to GND when not to be used. M2 POL O E CMOS Digital Voltage polarity selection signal for source driver M3 GRST I/O H CMOS Digital Reset signal for gate driver M4 SDVSSQ P - GND Digital SDRAM ground *2 M5 SDVSSQ P - GND Digital SDRAM ground *2 M6 SDVSSQ P - GND Digital SDRAM ground *2 M7 SDVSSQ P - GND Digital SDRAM ground *2 M8 SDVSSQ P - GND Digital SDRAM ground *2 M9 SDVSSQ P - GND Digital SDRAM ground *2 M10 DROUT1 I/O H CMOS Digital R/Cr video M11 DROUT3 I/O H CMOS Digital R/Cr video M12 DROUT4 I/O H CMOS Digital R/Cr video *1: We recommend isolated power to be supplied to SDRAM for improved noise immunity. *2: We recommend isolated ground to be supplied to SDRAM for improved noise immunity. No.A1948-10/13 LC749403BG Pin Circuits In/output form A Function Schmitt trigger Equivalent circuit Application Terminal XRST, PDWN, SCS_I2SEL CMOS input B CMOS input with built-in TEST pull-down resister C CMOS input SCK_SCL, SIOSEL, DVSI, DHSI, DDEI, OSDBL, DYGIN7, DYGIN6, DYGIN5, DYGIN4, DYGIN3, DYGIN2, DYGIN1, DYGIN0, DCBIN7, DCBIN6, DCBIN5, DCBIN4, DCBIN3, DCBIN2, DCBIN1, DCBIN0, DCRIN7, DCRIN6, DCRIN5, DCRIN4, DCRIN3, DCRIN2, DCRIN1, DCRIN0 D 2mA 3-STATE drive STXD, PWM, INTO CMOS output E 2mA/4mA switching DBOUT7, DBOUT6, DBOUT5, DBOUT4, 3-STATE drive DBOUT3, DBOUT2, DBOUT1, DBOUT0, CMOS output DGOUT7, DGOUT6, DGOUT5, DGOUT4, DGOUT3, DGOUT2, DGOUT1, DGOUT0, DHSO/SP2, DVSO/FLM2, DDEO FLM, DEXR, POL F 4mA/8mA switching DCKO 3-STATE drive CMOS output G 4mA 3-STATE drive SRXD_SDA CMOS input/output H J 2mA/4mA switching DROUT7, DROUT6, DROUT5, DROUT4, 3-STATE DROUT3, DROUT2, DROUT1, DROUT0, CMOS input/output GRST, CPV, SP, OE, STRB Analog input/output RC_BIAS No.A1948-11/13 LC749403BG Input/Output Timing (1) Input data timing tHI tCK DVDD_IO/2 DCKI tSU tLI tHD DVDD_IO/2 Input data Pin Name Parameter Clock cycle DCKI Symbol min tCK typ 50 Input data set up time DCBIN*, DVSI, DHSI, DDEI, OSDBL unit ns Duty DCRIN*, DYGIN*, max 25 (DVDD_IO=2.6 to 3.6V) Input data set up time (DVDD_IO=1.7 to 1.95V) Input data hold time (DVDD_IO=2.6 to 3.6V) Input data hold time (DVDD_IO=1.7 to 1.95V) % tSU 3 ns tSU 3 ns tHD 2 ns tHD 2 ns *: We recommend a 50% duty cycle for the input clock. (2) Output data timing tHO tCK DVDD_IO/2 DCKO tAC tLO DVDD_IO/2 Output data Pin Name Parameter Clock cycle DCKO Symbol tCK min typ max unit 25 Duty ns 50 % Output data delay time (DVDD_IO=2.6 to 3.6V) I/O typ E: 4mA setting tAC -3 3 ns tAC -3 6 ns tAC -5 4 ns tAC -6 9 ns I/O typ F: 8mA setting Output data delay time DROUT*, DGOUT*, DBOUT*, DVSO, DHSO, DDEO, DEXR, POL, SP, STRB, CPV, OE, FLM, GRST (DVDD_IO=2.6 to 3.6V) I/O typ E: 2mA setting I/O typ F: 4mA setting Output data hold time (DVDD_IO=1.7 to 1.95V) I/O typ E: 4mA setting I/O typ F: 8mA setting Output data hold time (DVDD_IO=1.7 to 1.95V) I/O typ E: 2mA setting I/O typ F: 4mA setting *: When DCKO is set to the forward rotation output. Output load capacity: 5pF No.A1948-12/13 LC749403BG SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of April, 2011. Specifications and information herein are subject to change without notice. PS No.A1948-13/13